CN101957525B - TFT-LCD array substrate and making method thereof - Google Patents
TFT-LCD array substrate and making method thereof Download PDFInfo
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- CN101957525B CN101957525B CN 200910088290 CN200910088290A CN101957525B CN 101957525 B CN101957525 B CN 101957525B CN 200910088290 CN200910088290 CN 200910088290 CN 200910088290 A CN200910088290 A CN 200910088290A CN 101957525 B CN101957525 B CN 101957525B
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Abstract
The invention relates to a TFT-LCD array substrate and a making method thereof. The array substrate comprises a gate line, a data line, a thin film transistor, a pixel electrode and a common electrode line, wherein the gate line, the data line and the thin film transistor are formed on the substrate, and the pixel electrode and the common electrode line form a storage capacitor, a pulse electrode is arranged between the common electrode line and the pixel electrode and is used for enabling the storage capacitor to have a first capacitance value when the pixel electrode is started to be charged and enabling the storage capacitor to have a second capacitance value when pixel electrode charging is finished, and the first capacitance value is smaller than the second capacitance value. In the invention, because the pulse electrode is arranged between the common electrode line and the pixel electrode, on the one hand, the storage capacitor has the smaller capacitance value when pixel electrode charging is started so as to lower load of the thin film transistor and enhance the charging capability of the thin film transistor, and on the other hand, the storage capacitor has the larger capacitance value when pixel electrode charging is finished to strengthen the holding property of voltage of the pixel electrode and lower the leaping voltage of the pixel electrode at the moment that the thin film transistor is closed.
Description
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD and manufacture method thereof, especially a kind of TFT-LCD array base palte and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid CrystalDisplay, be called for short TFT-LCD) mainly by to box together and array base palte and color membrane substrates that the liquid crystal folder is established therebetween constitute, wherein be formed with thin film transistor (TFT) and pixel electrode that matrix form is arranged on the array base palte, each pixel electrode is controlled by thin film transistor (TFT), adjust two electric fields between substrate by charging, discharge to pixel electrode, thereby the upset of control liquid crystal reaches display effect.
During TFT-LCD work, pixel electrode charges when thin film transistor (TFT) is opened, and thin film transistor (TFT) closes has no progeny, and pixel electrode voltage will be maintained to when scanning next time and charge again.Because there is the self-characteristic of leakage current in amorphous silicon film transistor, the electric charge on the pixel electrode can run off by thin film transistor (TFT), makes the sustaining voltage of pixel electrode present the trend that reduces gradually, and then changes display brightness, reduces the contrast of TFT-LCD.In addition, owing to have coupling capacitance (also claiming stray capacitance) between source electrode and the gate electrode in the thin film transistor (TFT), when thin film transistor (TFT) turn-offs, pixel electrode can produce a leaping voltage Δ Vp, the existence of leaping voltage Δ Vp can make the polarity of pixel electrode change, cause the voltage difference of positive-negative polarity inconsistent, influence display quality equally.Prior art is in order to slow down charge loss and the reduction leaping voltage Δ Vp of pixel electrode at the thin film transistor (TFT) blocking interval, usually on the TFT-LCD array base palte, storage capacitor construction is set, and increase the retention performance of pixel electrode voltage by the capacitance that increases memory capacitance, reduce the leaping voltage Δ Vp of pixel electrode simultaneously at the thin film transistor (TFT) shutdown moment.
But find in the practical application, though increase the retention performance that the capacitance of memory capacitance can reduce leaping voltage and strengthen pixel electrode voltage, but when capacitance is big, with the corresponding increase of load that makes as the thin film transistor (TFT) of switch, cause the thin film transistor (TFT) charging ability to reduce, the duration of charging increases.
Summary of the invention
The purpose of this invention is to provide a kind of TFT-LCD array base palte and manufacture method thereof,, effectively improve thin film transistor (TFT) to charging ability strengthening the pixel electrode voltage retention performance and reducing under the prerequisite of pixel electrode leaping voltage.
For achieving the above object, the invention provides a kind of TFT-LCD array base palte, comprise grid line, data line, thin film transistor (TFT) that is formed on the substrate and pixel electrode and the public electrode wire that constitutes memory capacitance, be provided with pulsed electrode between described public electrode wire and the pixel electrode, described pulsed electrode is used for making when described pixel electrode begins to charge described memory capacitance to have first capacitance, make described memory capacitance have second capacitance when the pixel electrode charging finishes, described first capacitance is less than second capacitance.
Described grid line and public electrode wire are formed on the substrate, are formed with gate insulation layer on it, and described pulsed electrode is formed on the described gate insulation layer, and are positioned at the top of public electrode wire.Further, described pulsed electrode is formed by semiconductive thin film.
On the technique scheme basis, described public electrode wire is connected with the pulse voltage module that pulse voltage is provided, described pulse voltage module is used for applying first voltage to public electrode wire when pixel electrode begins to charge, make described pulsed electrode present insulation characterisitic, the memory capacitance that has described first capacitance with formation, when finishing, the pixel electrode charging applies second voltage to public electrode wire, make described pulsed electrode present metallic character, have the memory capacitance of described second capacitance with formation, the magnitude of voltage of described first voltage is less than the magnitude of voltage of second voltage.Further, the magnitude of voltage of described first voltage is 0.2V～0.4V, and the magnitude of voltage of described second voltage is 10V～12V.
To achieve these goals, the present invention also provides a kind of TFT-LCD manufacturing method of array base plate, comprising:
Described step 2 can comprise:
Using plasma strengthens chemical gaseous phase depositing process, deposits gate insulation layer, semiconductive thin film and doped semiconductor films successively;
Adopt the method for magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Leak coating one deck photoresist on the metallic film in described source;
Adopt the exposure of shadow tone or gray mask plate, make photoresist form photoresist and remove zone, the complete reserve area of photoresist and photoresist part reserve area fully; The complete reserve area of photoresist is corresponding to the figure region of data line, source electrode and drain electrode, photoresist part reserve area is corresponding to the figure region of TFT channel region and pulsed electrode, and photoresist is removed the zone fully corresponding to the zone beyond the above-mentioned figure; After the development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and photoresist is removed the photoresist in zone fully and removed fully, and the photoresist thickness of photoresist part reserve area reduces;
By the first time etching technics etch away photoresist fully and remove the source in zone fully and leak metallic film, doped semiconductor films and semiconductive thin film, form the figure that comprises active layer and data line;
Photoresist by cineration technics removal photoresist part reserve area exposes this regional source and leaks metallic film;
Leak metallic film and doped semiconductor films by the source that the second time, etching technics etched away photoresist part reserve area fully, and etch away the semiconductive thin film of segment thickness, formation comprises the figure of TFT channel region and pulsed electrode, pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire;
Peel off remaining photoresist.
Described step 2 also can comprise:
Using plasma strengthens chemical gaseous phase depositing process, deposits gate insulation layer, semiconductive thin film and doped semiconductor films successively;
Adopt the normal masks plate to form the figure that comprises active layer and pulsed electrode by composition technology, described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire, is coated with doped semiconductor films on it;
Adopt the method for magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Adopt the normal masks plate to form the figure that comprises data line, drain electrode, source electrode and TFT channel region, remove the doped semiconductor films that covers pulsed electrode simultaneously by composition technology.
The invention provides a kind of TFT-LCD array base palte and manufacture method thereof, between as the pixel electrode of two battery lead plates of memory capacitance and public electrode wire, pulsed electrode is set, pulsed electrode cooperates the load signal on the public electrode wire to realize the variation of memory capacitance capacitance, make memory capacitance when pixel electrode begins to charge, have less capacitance on the one hand, reduce the load of thin film transistor (TFT), improve the charging ability of thin film transistor (TFT), accelerate the charging of pixel electrode, make memory capacitance when the pixel electrode charging finishes, have bigger capacitance on the other hand, strengthen the retention performance of pixel electrode voltage, reduce the charge loss of pixel electrode, be reduced in the leaping voltage of thin film transistor (TFT) shutdown moment pixel electrode simultaneously.The present invention has improved the operating characteristic of TFT-LCD array base palte on the whole, is with a wide range of applications.
Description of drawings
Fig. 1 is the planimetric map of TFT-LCD array base palte first embodiment of the present invention;
Fig. 2 be among Fig. 1 A1-A1 to sectional view;
Fig. 3 be among Fig. 1 B1-B1 to sectional view;
Fig. 4 is the planimetric map after TFT-LCD array base palte first embodiment composition technology first time of the present invention;
Fig. 5 be among Fig. 4 A2-A2 to sectional view;
Fig. 6 be among Fig. 4 B2-B2 to sectional view;
Fig. 7 is the planimetric map after TFT-LCD array base palte first embodiment composition technology second time of the present invention;
Fig. 8 be among Fig. 7 A3-A3 to sectional view;
Fig. 9 be among Fig. 7 B3-B3 to sectional view;
Figure 10 is TFT-LCD array base palte first embodiment of the present invention planimetric map after the composition technology for the third time;
Figure 11 be among Figure 10 A4-A4 to sectional view;
Figure 12 be among Figure 10 B4-B4 to sectional view;
Figure 13 is the planimetric map of TFT-LCD array base palte second embodiment of the present invention;
Figure 14 be among Figure 13 C1-C1 to sectional view;
Figure 15 be among Figure 13 D1-D1 to sectional view;
Figure 16 is the planimetric map after TFT-LCD array base palte second embodiment composition technology second time of the present invention;
Figure 17 be among Figure 16 C3-C3 to sectional view;
Figure 18 be among Figure 16 D3-D3 to sectional view;
Figure 19 is TFT-LCD array base palte second embodiment of the present invention planimetric map after the composition technology for the third time;
Figure 20 be among Figure 19 C4-C4 to sectional view;
Figure 21 be among Figure 19 D4-D4 to sectional view;
Figure 22 is the planimetric map after the 4th composition technology of TFT-LCD array base palte second embodiment of the present invention;
Figure 23 be among Figure 22 C5-C5 to sectional view;
Figure 24 be among Figure 22 D5-D5 to sectional view;
Figure 25 is the process flow diagram of TFT-LCD manufacturing method of array base plate of the present invention;
Figure 26 is the process flow diagram of TFT-LCD manufacturing method of array base plate first embodiment of the present invention;
Figure 27 is the process flow diagram of TFT-LCD manufacturing method of array base plate second embodiment of the present invention.
Description of reference numerals:
The 1-substrate; The 2-gate electrode; The 3-gate insulation layer;
The 4-semiconductor layer; The 5-doping semiconductor layer; 6-source electrode;
The 7-drain electrode; The 8-passivation layer; The 8a-passivation layer via hole;
The 9-pixel electrode; The 11-grid line; The 12-data line;
The 13-public electrode wire; The 14-pulsed electrode; The 15-doped semiconductor films.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the planimetric map of TFT-LCD array base palte first embodiment of the present invention, and what reflected is the structure of a pixel cell, Fig. 2 be among Fig. 1 A1-A1 to sectional view, Fig. 3 be among Fig. 1 B1-B1 to sectional view.As Fig. 1～shown in Figure 3, present embodiment TFT-LCD array base palte is a kind of structure that adopts four composition technology formation, agent structure comprises the grid line 11 that is formed on the substrate 1, data line 12, public electrode wire 13, pixel electrode 9 and thin film transistor (TFT), orthogonal grid line 11 and data line 12 have defined pixel region, thin film transistor (TFT) and pixel electrode 9 are formed in the pixel region, grid line 11 is used for providing start signal to thin film transistor (TFT), data line 12 is used for providing data-signal to pixel electrode 9, public electrode wire 13 is used for constituting memory capacitance with pixel electrode 9, and be provided with pulsed electrode 14 between pixel electrode 9 and the public electrode wire 13, pulsed electrode 14 is formed by semiconductive thin film, be used to cooperate the load signal on the public electrode wire 13 to realize the variable memory capacitance of capacitance, make pixel electrode memory capacitance when beginning to charge have the first less capacitance of capacitance on the one hand, reduce the charging load of thin film transistor (TFT), accelerate the charging of pixel electrode, make pixel electrode memory capacitance when charging finishes have the second bigger capacitance of capacitance on the other hand, strengthen the retention performance of pixel electrode voltage, reduce the leaping voltage of pixel electrode simultaneously at the thin film transistor (TFT) shutdown moment.Particularly, present embodiment TFT-LCD array base palte comprises gate electrode 2, grid line 11 and the public electrode wire 13 that is formed on the substrate 1, and gate electrode 2 is connected with grid line 11; Gate insulation layer 3 is formed on gate electrode 2, grid line 11 and the public electrode wire 13 and covers whole base plate 1; Active layer (comprising semiconductor layer 4 and doping semiconductor layer 5) is formed on the gate insulation layer 3 and is positioned at the top of gate electrode 2; The pulsed electrode of being made by semiconductor film material 14 is formed on the gate insulation layer 3 and is positioned on the public electrode wire 13; Source electrode 6 and drain electrode 7 are formed on the active layer, one end of source electrode 6 is positioned at the top of gate electrode 2, the other end is connected with data line 12, one end of drain electrode 7 is positioned at the top of gate electrode 2, the other end is connected with pixel electrode 9, forms the TFT channel region between source electrode 6 and the drain electrode 7, and the doping semiconductor layer 5 of TFT channel region is etched away fully, and etch away the semiconductor layer 4 of segment thickness, the semiconductor layer 4 of TFT channel region is come out; Passivation layer 8 is formed on data line 12, source electrode 6, drain electrode 7 and the TFT channel region and covers whole base plate 1, offers the passivation layer via hole 8a that drain electrode 7 is connected with pixel electrode 9 in drain electrode 7 positions; Pixel electrode 9 is formed on the passivation layer 8, and pixel electrode 9 is connected with drain electrode 7 by passivation layer via hole 8a.
In technique scheme, public electrode wire 13 is connected with pulse voltage module (not shown), the pulse voltage module is used for providing pulse voltage to public electrode wire 13, when promptly opening (pixel electrode begins charging) at thin film transistor (TFT), the pulse voltage module applies first voltage to public electrode wire 13, when disconnecting (the pixel electrode charging finishes) at thin film transistor (TFT), the pulse voltage module applies second voltage to public electrode wire 13.In the practical application, relating to parameters such as the numerical value of first voltage and second voltage and the material character of pulsed electrode and thickness, for the thickness that adopts usually at present is the amorphous silicon material of 230 μ m, first voltage can be the DC voltage of 0.2V～0.4V, and second voltage can be the DC voltage of 10V～12V.
Further specify technical scheme of the present invention below by the course of work of the present invention.When grid line when the gate electrode of thin film transistor (TFT) applies cut-in voltage (as high voltage), thin film transistor (TFT) is opened, thin film transistor (TFT) begins to pixel electrode charging, this moment, the pulse voltage module applied first voltage of 0.2V～0.4V to public electrode wire 13.According to semiconductor material characteristic as can be known, when public electrode wire 13 voltages are low, electric charge in the semiconductor layer can not polarize, therefore the pulsed electrode 14 between public electrode wire 13 and pixel electrode 9 will present insulation characterisitic, making the distance between two battery lead plates of memory capacitance is gate insulation layer, pulsed electrode and passivation layer thickness sum, and memory capacitance has first capacitance.For the existing storage capacitor construction, this stage has increased the distance between two battery lead plates, has reduced the capacitance of memory capacitance.Because the capacitance of liquid crystal capacitance is constant substantially, therefore the reduction of this stage memory capacitance capacitance means the load that has reduced thin film transistor (TFT), the charging ability of thin film transistor (TFT) is improved, help the charging of thin film transistor (TFT) to pixel electrode, pixel electrode voltage can reach required magnitude of voltage rapidly, has shortened the duration of charging.When grid line when the gate electrode of thin film transistor (TFT) applies shutoff voltage (as low-voltage), thin film transistor (TFT) cuts out, pixel electrode charging finishes, this moment, the pulse voltage module applied second voltage of 10V～12V to public electrode wire 13.Be subjected to the influence of thin film transistor (TFT) self character, i.e. the existence of coupling capacitance between gate electrode and the source electrode, when being opened to the moment of shutoff, the voltage of pixel electrode can produce a leaping voltage Δ Vp at thin film transistor (TFT).Equally according to semiconductor material characteristic, when public electrode wire 13 voltages are higher, electric charge in the semiconductor layer is polarized, therefore the pulsed electrode 14 between public electrode wire 13 and pixel electrode 9 will present metallic character, and because pulsed electrode 14 is vacant state (promptly not having the on-load voltage signal), therefore the specific inductive capacity of pulsed electrode 14 is close to 0, and making the distance between two battery lead plates of memory capacitance is gate insulation layer and passivation layer thickness sum, and memory capacitance has second capacitance.With respect to the pixel electrode charging stage, this stage has reduced the distance between two battery lead plates, has increased the capacitance of memory capacitance, and promptly second capacitance is greater than first capacitance, and this capacitance is identical with the capacitance of existing storage capacitor construction.Owing to apply high voltage to public electrode wire 13 always in thin film transistor (TFT) blocking interval pulse voltage module, be that storage capacitors is in big capacitance state always, therefore the memory capacitance of big capacitance of this stage can reduce the saltus step low pressure of pixel electrode at the thin film transistor (TFT) shutdown moment on the one hand, can increase the maintenance of pixel electrode voltage on the other hand effectively, slow down the charge loss of pixel electrode, electric field is constant between the maintenance two substrates, keeps display brightness.Said process lasts till that always thin film transistor (TFT) is opened next time, and the pulse voltage module applies first voltage to public electrode wire 13, promptly becomes first voltage by second voltage, finishes above-mentioned circulation.
Fig. 4～Figure 12 is the synoptic diagram of the TFT-LCD array base palte first embodiment manufacture process of the present invention, can further specify the technical scheme of present embodiment, in the following description, the alleged composition technology of the present invention comprises technologies such as photoresist coating, mask, exposure, etching and photoresist lift off, and photoresist is example with the positive photoresist.
Fig. 4 is TFT-LCD array base palte first embodiment of the present invention planimetric map after the composition technology for the first time, and what reflected is the structure of a pixel cell, Fig. 5 be among Fig. 4 A2-A2 to sectional view, Fig. 6 be among Fig. 4 B2-B2 to sectional view.Adopt the method for magnetron sputtering or thermal evaporation, go up deposition one deck grid metallic film at substrate 1 (as glass substrate or quartz base plate), adopt the normal masks plate to form the figure that comprises gate electrode 2, grid line 11 and public electrode wire 13, as Fig. 4～shown in Figure 6 by composition technology.
Fig. 7 is TFT-LCD array base palte first embodiment of the present invention planimetric map after the composition technology for the second time, and what reflected is the structure of a pixel cell, Fig. 8 be among Fig. 7 A3-A3 to sectional view, Fig. 9 be among Fig. 7 B3-B3 to sectional view.On the substrate of finishing above-mentioned Fig. 4 structure graph, using plasma strengthens chemical vapor deposition (being called for short PECVD) method, deposit gate insulation layer, semiconductive thin film and doped semiconductor films successively, then adopt the method for magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film.Adopt shadow tone or gray mask plate to form the figure that comprises active layer, data line 12, source electrode 6, drain electrode 7 and pulsed electrode 14, as Fig. 7～shown in Figure 9 by composition technology.Wherein, active layer comprises semiconductor layer 4 and doping semiconductor layer 5, is formed on the gate insulation layer 3 and is positioned at the top of gate electrode 2; Source electrode 6 and drain electrode 7 are formed on the active layer, one end of source electrode 6 is positioned at the top of gate electrode 2, the other end is connected with data line 12, one end of drain electrode 7 is positioned at the top of gate electrode 2, be oppositely arranged with source electrode 6, form the TFT channel region between source electrode 6 and the drain electrode 7, the doping semiconductor layer 5 of TFT channel region is etched away fully, and etch away the semiconductor layer 4 of segment thickness, the semiconductor layer 4 of TFT channel region is come out; The pulsed electrode 14 of semiconductor film material is formed on the gate insulation layer 3, and is positioned on the public electrode wire 13.In the present embodiment, pulsed electrode 14 is arranged on the top of public electrode wire 13, and covers the public electrode wire 13 in the pixel region scope fully.In the practical application, the size of pulsed electrode and shape can be provided with as required, and for example, the size of pulsed electrode and shape also can be basic identical with pixel electrode.
This composition technology is a kind of multistep etching technics, basic identical with the process that forms active layer, data line, source electrode, drain electrode and TFT channel region figure in four composition technologies of prior art, be specially: deposit gate insulation layer, semiconductive thin film and doped semiconductor films at first successively, then sedimentary origin leaks metallic film.Leak coating one deck photoresist on the metallic film in the source.Adopt the exposure of shadow tone or gray mask plate, make photoresist form complete exposure area, unexposed area and partial exposure area; Unexposed area is corresponding to data line, source electrode and drain electrode figure region, and partial exposure area is corresponding to pulsed electrode and TFT channel region figure region, and complete exposure area is corresponding to the zone beyond the above-mentioned figure.After the development treatment, the photoresist thickness of unexposed area does not change, and forms the complete reserve area of photoresist, the photoresist of complete exposure area is removed fully, form photoresist and remove the zone fully, the photoresist thickness of partial exposure area reduces, and forms photoresist part reserve area.By the first time etching technics etch away photoresist fully and remove the source in zone fully and leak metallic film, doped semiconductor films and semiconductive thin film, form the figure that comprises active layer and data line.Photoresist by cineration technics removal photoresist part reserve area exposes this regional source and leaks metallic film.Leak metallic film and doped semiconductor films by the source that the second time, etching technics etched away photoresist part reserve area fully, and etch away the semiconductive thin film of segment thickness, form the figure that comprises source electrode, drain electrode, TFT channel region and pulsed electrode.At last, peel off remaining photoresist, finish this composition technology.In this composition technology, the pulsed electrode figure and the TFT channel region figure that are positioned at pixel region form simultaneously, are etched away fully by source leakage metallic film and doped semiconductor films above the film formed pulsed electrode of semiconductor film.
Figure 10 is TFT-LCD array base palte first embodiment of the present invention planimetric map after the composition technology for the third time, and what reflected is the structure of a pixel cell, Figure 11 be among Figure 10 A4-A4 to sectional view, Figure 12 be among Figure 10 B4-B4 to sectional view.On the substrate of finishing above-mentioned Fig. 7 structure graph, adopt PECVD method deposition one deck passivation layer 8, adopt the normal masks plate to form the figure that comprises passivation layer via hole 8a by composition technology, passivation layer via hole 8a is positioned at drain electrode 7 positions, expose the surface of drain electrode 7 in the passivation layer via hole 8a, as Figure 10～shown in Figure 12.In this composition technology, go back the figure that (grid line PAD) is formed with the grid line interface via hole and (data line PAD) is formed with the data line interface via hole in the data line interface zone in the grid line interface zone simultaneously.The technology and the structure that form grid line interface via hole and data line interface via pattern have been widely used in repeating no more in the present composition technology.
At last, on the substrate of finishing Figure 10 structure graph, adopt the method deposition layer of transparent conductive film of magnetron sputtering or thermal evaporation, adopt the normal masks plate to form the figure that comprises pixel electrode 9 by composition technology, pixel electrode 9 is positioned at pixel region, be connected with drain electrode 7 by passivation layer via hole 8a, as Fig. 1～shown in Figure 3.
Figure 13 is the planimetric map of TFT-LCD array base palte second embodiment of the present invention, and what reflected is the structure of a pixel cell, Figure 14 be among Figure 13 C1-C1 to sectional view, Figure 15 be among Figure 13 D1-D1 to sectional view.As Figure 13～shown in Figure 15, present embodiment TFT-LCD array base palte is a kind of structure that adopts five composition technology formation, agent structures such as grid line 11, data line 12, public electrode wire 13, pulsed electrode 14 and pixel electrode 9 are identical with aforementioned first embodiment, and different is the structure of thin film transistor (TFT).Particularly, present embodiment TFT-LCD array base palte comprises gate electrode 2, grid line 11 and the public electrode wire 13 that is formed on the substrate 1, and gate electrode 2 is connected with grid line 11; Gate insulation layer 3 is formed on gate electrode 2, grid line 11 and the public electrode wire 13 and covers whole base plate 1; Active layer (comprising semiconductor layer 4 and doping semiconductor layer 5) is formed on the gate insulation layer 3 and is positioned at the top of gate electrode 2; The pulsed electrode of being made by semiconductor film material 14 is formed on the gate insulation layer 3 and is positioned at pixel region; One end of source electrode 6 is positioned on the active layer, the other end is connected with data line 12, one end of drain electrode 7 is positioned on the active layer, the other end is connected with pixel electrode 9, form the TFT channel region between source electrode 6 and the drain electrode 7, the doping semiconductor layer 5 of TFT channel region is etched away fully, and etches away the semiconductor layer 4 of segment thickness, and the semiconductor layer 4 of TFT channel region is come out; Passivation layer 8 is formed on data line 12, source electrode 6, drain electrode 7 and the TFT channel region and covers whole base plate 1, offers the passivation layer via hole 8a that drain electrode 7 is connected with pixel electrode 9 in drain electrode 7 positions; Pixel electrode 9 is formed on the passivation layer 8, and pixel electrode 9 is connected with drain electrode 7 by passivation layer via hole 8a.Principle of work, the course of work and technique effect that present embodiment is provided with pulsed electrode and pulse voltage module are identical with aforementioned first embodiment, repeat no more.
Figure 16～Figure 24 is the synoptic diagram of the TFT-LCD array base palte second embodiment manufacture process of the present invention, can further specify the technical scheme of present embodiment.Present embodiment for the first time composition technology is used to form the figure that comprises gate electrode 2, grid line 11 and public electrode wire 13, and its process and formed structure are identical with aforementioned first embodiment, referring to Fig. 4～shown in Figure 6.
Figure 16 is TFT-LCD array base palte second embodiment of the present invention planimetric map after the composition technology for the second time, and what reflected is the structure of a pixel cell, Figure 17 be among Figure 16 C3-C3 to sectional view, Figure 18 be among Figure 16 D3-D3 to sectional view.On the substrate that forms gate electrode, grid line and public electrode line graph, adopt the PECVD method to deposit gate insulation layer, semiconductive thin film and doped semiconductor films successively, adopt the normal masks plate to form the figure that comprises active layer and pulsed electrode 14, as Figure 16～shown in Figure 180 by composition technology.Wherein, active layer comprises semiconductor layer 4 and doping semiconductor layer 5, is formed on the gate insulation layer 3 and is positioned at the top of gate electrode 2; The pulsed electrode 14 of semiconductor film material is formed on the gate insulation layer 3, and is positioned at the top of public electrode wire 13, and at this moment, pulsed electrode 14 tops also are coated with doped semiconductor films 15.
Figure 19 is TFT-LCD array base palte second embodiment of the present invention planimetric map after the composition technology for the third time, and what reflected is the structure of a pixel cell, Figure 20 be among Figure 19 C4-C4 to sectional view, Figure 21 be among Figure 19 D4-D4 to sectional view.On the substrate of finishing above-mentioned Figure 16 structure graph, adopt the method sedimentary origin of magnetron sputtering or thermal evaporation to leak metallic film, adopt the normal masks plate to form the figure that comprises data line 12, source electrode 6, drain electrode 7 and TFT channel region, as Figure 19～shown in Figure 21 by composition technology.Wherein, one end of source electrode 6 is positioned on the active layer, the other end is connected with data line 12, one end of drain electrode 7 is positioned on the active layer, be oppositely arranged with source electrode 6, form the TFT channel region between source electrode 6 and the drain electrode 7, the doping semiconductor layer 5 of TFT channel region is etched away fully, and etch away the semiconductor layer 4 of segment thickness, the semiconductor layer 4 of TFT channel region is come out.When the etching doped semiconductor films formed the TFT channel region, the doped semiconductor films that pulsed electrode 14 tops cover also was etched away.
Figure 22 is the planimetric map after the 4th composition technology of TFT-LCD array base palte second embodiment of the present invention, and what reflected is the structure of a pixel cell, Figure 23 be among Figure 22 C5-C5 to sectional view, Figure 24 be among Figure 22 D5-D5 to sectional view.On the substrate of finishing above-mentioned Figure 19 structure graph, adopt PECVD method deposition one deck passivation layer 8, adopt the normal masks plate to form the figure that comprises passivation layer via hole 8a by composition technology, passivation layer via hole 8a is positioned at drain electrode 7 positions, expose the surface of drain electrode 7 in the passivation layer via hole 8a, as Figure 22～shown in Figure 24.In this composition technology, also the while is formed with the figure of interface via hole in grid line interface zone and data line interface zone.
At last, on the substrate of finishing Figure 22 structure graph, adopt the method deposition layer of transparent conductive film of magnetron sputtering or thermal evaporation, adopt the normal masks plate to form the figure that comprises pixel electrode 9 by composition technology, pixel electrode 9 is positioned at pixel region, be connected with drain electrode 7 by passivation layer via hole 8a, as Figure 13～shown in Figure 15.
As seen, present embodiment is that the composition technology second time that will adopt shadow tone or gray mask plate among aforementioned first embodiment is divided into two composition technologies that adopt the normal masks plate, promptly form the figure that comprises active layer and pulsed electrode, adopt the composition technology of normal masks plate to form the figure that comprises data line, source electrode, drain electrode and TFT channel region by another time by the composition technology that once adopts the normal masks plate.
The invention provides a kind of TFT-LCD array base palte, between as the pixel electrode of two battery lead plates of memory capacitance and public electrode wire, pulsed electrode is set, pulsed electrode cooperates the load signal on the public electrode wire to realize the variation of memory capacitance capacitance, variation by the memory capacitance capacitance, make memory capacitance when pixel electrode begins to charge, have less capacitance on the one hand, reduce the load of thin film transistor (TFT), improve the charging ability of thin film transistor (TFT), accelerate the charging of pixel electrode, make memory capacitance when the pixel electrode charging finishes, have bigger capacitance on the other hand, strengthen the retention performance of pixel electrode voltage, reduce the charge loss of pixel electrode, be reduced in the leaping voltage of thin film transistor (TFT) shutdown moment pixel electrode simultaneously.Comprehensive These characteristics, technical solution of the present invention has improved the operating characteristic of TFT-LCD array base palte on the whole, is with a wide range of applications.
Figure 25 is the process flow diagram of TFT-LCD manufacturing method of array base plate of the present invention, comprising:
In the technique scheme of the present invention, by between public electrode wire and pixel electrode, pulsed electrode being set, pulsed electrode is used to realize the memory capacitance that changes, make one aspect of the present invention capacitance of memory capacitance when pixel electrode begins to charge less, reduce the charging load of thin film transistor (TFT), accelerate the charging of pixel electrode, the capacitance of memory capacitance is bigger when the pixel electrode charging finishes on the other hand, strengthened the retention performance of pixel electrode voltage, reduce the charge loss of pixel electrode, be reduced in the leaping voltage of thin film transistor (TFT) shutdown moment pixel electrode simultaneously.
Further specify the technical scheme of TFT-LCD manufacturing method of array base plate of the present invention below by specific embodiment.
Figure 26 is the process flow diagram of TFT-LCD manufacturing method of array base plate first embodiment of the present invention, comprising:
The method of step 11, employing magnetron sputtering or thermal evaporation, deposition grid metallic film on substrate adopts the normal masks plate to form the figure that comprises gate electrode, grid line and public electrode wire by composition technology;
The method of step 18, employing magnetron sputtering or thermal evaporation, the deposit transparent conductive film adopts the normal masks plate to form by composition technology and comprises pattern of pixel electrodes, and described pixel electrode is connected with drain electrode by passivation layer via hole.
Present embodiment is a kind ofly to prepare the technical scheme of TFT-LCD array base palte by four composition technology, and its preparation process is introduced in earlier figures 4～technical scheme shown in Figure 12 in detail, repeats no more here.
Figure 27 is the process flow diagram of TFT-LCD manufacturing method of array base plate second embodiment of the present invention, comprising:
The method of step 21, employing magnetron sputtering or thermal evaporation, deposition grid metallic film on substrate adopts the normal masks plate to form the figure that comprises gate electrode, grid line and public electrode wire by composition technology;
Step 22, using plasma strengthen chemical gaseous phase depositing process, deposit gate insulation layer, semiconductive thin film and doped semiconductor films successively;
Step 23, employing normal masks plate form the figure that comprises active layer and pulsed electrode by composition technology, and described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire, is coated with doped semiconductor films on it;
The method of step 24, employing magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
The method of step 27, employing magnetron sputtering or thermal evaporation, the deposit transparent conductive film adopts the normal masks plate to form by composition technology and comprises pattern of pixel electrodes, and described pixel electrode is connected with drain electrode by passivation layer via hole.
Present embodiment is a kind ofly to prepare the technical scheme of TFT-LCD array base palte by five composition technology, and its preparation process is introduced in aforementioned Figure 16～technical scheme shown in Figure 24 in detail, repeats no more here.
It should be noted that at last: above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (6)
1. TFT-LCD array base palte, comprise grid line, data line, thin film transistor (TFT) that is formed on the substrate and pixel electrode and the public electrode wire that constitutes memory capacitance, it is characterized in that, be provided with pulsed electrode between described public electrode wire and the pixel electrode, described pulsed electrode is used for making when described pixel electrode begins to charge described memory capacitance to have first capacitance, make described memory capacitance have second capacitance when described pixel electrode charging finishes, described first capacitance is less than second capacitance;
Wherein, described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire;
Described public electrode wire is connected with the pulse voltage module that pulse voltage is provided, described pulse voltage module is used for applying first voltage to public electrode wire when pixel electrode begins to charge, make described pulsed electrode present insulation characterisitic, the memory capacitance that has described first capacitance with formation, when finishing, the pixel electrode charging applies second voltage to public electrode wire, make described pulsed electrode present metallic character, have the memory capacitance of described second capacitance with formation, the magnitude of voltage of described first voltage is less than the magnitude of voltage of second voltage.
2. TFT-LCD array base palte according to claim 1 is characterized in that described grid line and public electrode wire are formed on the substrate, is formed with gate insulation layer on it, and described pulsed electrode is formed on the described gate insulation layer.
3. TFT-LCD array base palte according to claim 1 is characterized in that, the magnitude of voltage of described first voltage is 0.2V～0.4V, and the magnitude of voltage of described second voltage is 10V～12V.
4. a TFT-LCD manufacturing method of array base plate is characterized in that, comprising:
Step 1, on substrate deposition grid metallic film, form the figure that comprises gate electrode, grid line and public electrode wire by composition technology;
Step 2, form the figure of active layer, data line, drain electrode, source electrode and pulsed electrode by depositional texture layer and composition technology on the substrate of completing steps 1, described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire;
Step 3, on the substrate of completing steps 2 deposit passivation layer, form the figure comprise passivation layer via hole by composition technology, described passivation layer via hole is positioned at the position of drain electrode;
Step 4, on the substrate of completing steps 3 the deposit transparent conductive film, form by composition technology and to comprise pattern of pixel electrodes, described pixel electrode is connected with drain electrode by passivation layer via hole;
Wherein, described public electrode wire is connected with the pulse voltage module that pulse voltage is provided, described pulse voltage module is used for applying first voltage to public electrode wire when pixel electrode begins to charge, make described pulsed electrode present insulation characterisitic, the memory capacitance that has first capacitance with formation, when finishing, the pixel electrode charging applies second voltage to public electrode wire, make described pulsed electrode present metallic character, have the memory capacitance of second capacitance with formation, the magnitude of voltage of described first voltage is less than the magnitude of voltage of second voltage.
5. TFT-LCD manufacturing method of array base plate according to claim 4 is characterized in that, described step 2 comprises:
Using plasma strengthens chemical gaseous phase depositing process, deposits gate insulation layer, semiconductive thin film and doped semiconductor films successively;
Adopt the method for magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Leak coating one deck photoresist on the metallic film in described source;
Adopt the exposure of shadow tone or gray mask plate, make photoresist form photoresist and remove zone, the complete reserve area of photoresist and photoresist part reserve area fully; The complete reserve area of photoresist is corresponding to the figure region of data line, source electrode and drain electrode, photoresist part reserve area is corresponding to the figure region of TFT channel region and pulsed electrode, and photoresist is removed the zone fully corresponding to the zone beyond the above-mentioned figure; After the development treatment, the photoresist thickness of the complete reserve area of photoresist does not change, and photoresist is removed the photoresist in zone fully and removed fully, and the photoresist thickness of photoresist part reserve area reduces;
By the first time etching technics etch away photoresist fully and remove the source in zone fully and leak metallic film, doped semiconductor films and semiconductive thin film, form the figure that comprises active layer and data line;
Photoresist by cineration technics removal photoresist part reserve area exposes this regional source and leaks metallic film;
Leak metallic film and doped semiconductor films by the source that the second time, etching technics etched away photoresist part reserve area fully, and etch away the semiconductive thin film of segment thickness, formation comprises the figure of TFT channel region and pulsed electrode, described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire;
Peel off remaining photoresist.
6. TFT-LCD manufacturing method of array base plate according to claim 4 is characterized in that, described step 2 comprises:
Using plasma strengthens chemical gaseous phase depositing process, deposits gate insulation layer, semiconductive thin film and doped semiconductor films successively;
Adopt the normal masks plate to form the figure that comprises active layer and pulsed electrode by composition technology, described pulsed electrode is formed by semiconductive thin film, and is positioned at the top of public electrode wire, is coated with doped semiconductor films on it;
Adopt the method for magnetron sputtering or thermal evaporation, sedimentary origin leaks metallic film;
Adopt the normal masks plate to form the figure that comprises data line, drain electrode, source electrode and TFT channel region, remove the doped semiconductor films that covers pulsed electrode simultaneously by composition technology.
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| US8883572B2 (en) | 2011-05-27 | 2014-11-11 | Boe Technology Group Co., Ltd. | Manufacturing method of low temperature poly-silicon TFT array substrate |
| CN104808409B (en) * | 2015-05-18 | 2018-03-27 | 京东方科技集团股份有限公司 | Array base palte, manufacturing method of array base plate and display device |
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| CN101000417A (en) * | 2006-01-10 | 2007-07-18 | 三星电子株式会社 | Gate driver, and thin film transistor substrate and liquid crystal display having the same |
| CN101369077A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | LCD array substrates and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101000417A (en) * | 2006-01-10 | 2007-07-18 | 三星电子株式会社 | Gate driver, and thin film transistor substrate and liquid crystal display having the same |
| CN101369077A (en) * | 2007-08-17 | 2009-02-18 | 北京京东方光电科技有限公司 | LCD array substrates and manufacturing method thereof |
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| JP特开平10-48664A 1998.02.20 |
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