CN101943926A - Voltage reference circuit with temperature compensation - Google Patents

Voltage reference circuit with temperature compensation Download PDF

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Publication number
CN101943926A
CN101943926A CN2010102225798A CN201010222579A CN101943926A CN 101943926 A CN101943926 A CN 101943926A CN 2010102225798 A CN2010102225798 A CN 2010102225798A CN 201010222579 A CN201010222579 A CN 201010222579A CN 101943926 A CN101943926 A CN 101943926A
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China
Prior art keywords
nmos pass
pass transistor
pmos
grid
drain electrode
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CN2010102225798A
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Chinese (zh)
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CN101943926B (en
Inventor
黄明杰
杨天骏
隋彧文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Abstract

A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. The voltage reference circuit is advantaged by obviously improved precision of output voltage, small size and constant transconductance of power.

Description

Reference circuits with temperature compensation
Technical field
The present invention relates to a kind of reference circuits, relate in particular to the reference voltage circuit that is used for constant mutual conductance (GM) design with temperature compensation.
Background technology
No matter reference circuits is load, technology, power supply variation and temperature, can produce the electronic installation (circuit or assembly) of fixing (constant) voltage.Reference circuits is one of important analogue means among the integrated circuit.
A kind of reference circuits that is usually used in integrated circuit is a bandgap voltage reference circuit.The reference circuit on band gap basis uses mimic channel to increase the several times voltage difference of skew between the bipolar interface of different current densities to the voltage across diode.Diode voltage is negative temperature coefficient (that is along with temperature reduces), and the face voltage difference of connecing is a positive temperature coefficient (PTC).When the ratio that increases made that these coefficients are eliminated, constant value was that voltage equals semi-conductive band gap voltage as a result.Yet the band gap design needs big relatively area and power.
Another reference circuits design is constant mutual conductance design.Figure 1A is the traditional constant mutual conductance reference circuits with temperature compensation.Be connected to two PMOS transistors 102 and 104 common grids of VDD. Nmos pass transistor 106 and 108 be connected to PMOS transistor 102 and 104 and common grid be connected to output voltage V REF, yet the grid of PMOS 104 and drain electrode connect, and the grid of NMOS106 and drain electrode connect.Transistor 106 and 108 NMOS channel dimensions ratio are W/L: K (W/L)=1: K, wherein W/L is that the channel width of nmos pass transistor compares length.The source electrode that the source electrode of NMOS106 is connected to ground connection (VSS) and NMOS 108 is connected to ground connection (VSS) via resistor R s 110.Constant mutual conductance design needs relatively little area and power, but strong temperature dependence is arranged.
With V THAs the critical voltage of NMOS 108, the electric current and the following formulate of voltage of the reference circuits that Figure 1A shows:
Iref = 2 μ N C OX ( W L ) * RS 2 ( 1 - 1 K ) 2 - - - ( 1 )
Iref = 2 μ N C OX ( W L ) * RS 2 ( 1 - 1 K ) 2 - - - ( 2 )
μ wherein NBe the mobility of NMOS, C OXBe gate oxidation electric capacity, W/L is the Aspect Ratio of NOMS raceway groove.
Along with temperature increases, mobility μ NIncrease, therefore cause equational I RefHigher.In other words, along with temperature increases, critical voltage V THIncrease, cause equational VREF lower.Therefore VREF demonstrates the strong dependence with temperature.For instance, contrast circuit layout area 77*53 μ m 2With the band gap design voltage reference circuit of the example of 180 μ A electric current demands, be presented at-40 and spend to 125 degree and have the variation of 3mV, at circuit layout area 24*7.3 μ m 2Be presented at the variation that 18mV is arranged under the same temperature range with the band gap design voltage reference circuit of the example of 10 μ A electric current demands, as Figure 1B (temperature of the example reference circuits that Figure 1A shows is exported plot to voltage).
Therefore, new temperature compensation structure has needs for the Voltage Reference that the constant mutual conductance designs.
Summary of the invention
For overcoming the defective of above-mentioned prior art, the embodiment of the invention provides a kind of reference circuits with temperature compensation, comprising: a power supply; One reference voltage; One the one PMOS transistor has one source pole and is connected to this power supply; One the 2nd PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of a PMOS; One first nmos pass transistor has a grid and one source pole and is connected to transistorized this drain electrode of a PMOS; One second nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 2nd PMOS, and a grid is connected to this grid and this reference voltage of this first nmos pass transistor; One resistor is connected to this source electrode and the ground connection of this second nmos pass transistor; And an operational amplifier, have a reverse input end, a non-inverting input and an output terminal; Wherein this reverse input end connects this source electrode of this output terminal and this first nmos pass transistor, and this non-return input is connected to ground connection.
The embodiment of the invention provides a kind of reference circuits with temperature compensation in addition, comprising: a power supply; One reference voltage; One the one PMOS transistor has one source pole and is connected to this power supply; One the 2nd PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of a PMOS; One first nmos pass transistor has a grid and a drain electrode is connected to transistorized this drain electrode of a PMOS; One second nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 2nd PMOS, and a grid is connected to this grid and this reference voltage of this first nmos pass transistor; One resistor is connected to this source electrode and the ground connection of this second nmos pass transistor; One second reference voltage; One the 3rd PMOS transistor has one source pole and is connected to this power supply; One the 4th PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of the 3rd PMOS; One the 3rd nmos pass transistor has a grid and a drain electrode is connected to transistorized this drain electrode of the 3rd PMOS; One the 4th nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 4th PMOS, and a grid is connected to this grid and this second reference power source of the 3rd nmos pass transistor; One the 5th nmos pass transistor has this source electrode that a drain electrode is connected to the 4th nmos pass transistor, and one source pole is connected to ground connection, and a grid is connected to this first reference voltage.
The embodiment of the invention is by increasing the temperature compensation feedback element can control the transformation variation, compared to the band gap design, can finish the output voltage precision with obvious improvement and need the very constant mutual conductance reference circuits of small size and power.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperate attached showing, be described in detail as follows.
Description of drawings
Figure 1A is the circuit diagram that does not have traditional constant mutual conductance reference circuits of temperature compensation;
Figure 1B is the plot of the temperature of the shown example reference circuits of Figure 1A to voltage output;
Fig. 2 A is the circuit diagram of reference circuits that is used for the example with temperature compensation of constant mutual conductance design according to the present invention;
Fig. 2 B is the plot that the temperature of the embodiment of the reference circuits shown in Fig. 2 A is exported voltage;
Fig. 3 A is the circuit diagram of reference circuits that is used for the example with temperature compensation of constant mutual conductance design according to the present invention; And
Fig. 3 B is the plot that the temperature of the embodiment of the reference circuits shown in Fig. 3 A is exported voltage.
Wherein, description of reference numerals is as follows:
102～the one PMOS transistors;
104～the 2nd PMOS transistors;
106～the first nmos pass transistors;
108～the second nmos pass transistors;
110～resistor;
202～operational amplifier;
300～additional circuit;
302～the 3rd PMOS transistors;
304～the 4th PMOS transistors;
306～the 3rd nmos pass transistors;
308～the 4th nmos pass transistors;
310～the 5th nmos pass transistors;
Embodiment
Various embodiment that disclose in graphic or example use language-specific to describe.Can recognize, be not to limit scope of invention whereby.Any variation and the change of the embodiment that discloses, and the further application of the principle that discloses in the file can be expected to those skilled in the art easily.Reference number may be reused in an embodiment, though their shared same reference numbers, but may not be that the feature application of an embodiment is to other embodiment.
Fig. 2 A is the circuit diagram of reference circuits that is used for the example with temperature compensation of constant mutual conductance design according to the present invention.The output that is couple to an operational amplifier 202 of non-inverting input is connected to the source electrode of NMOS 106 (virtual VSS).Operational amplifier 202 noninverting inputs are connected to ground connection (VSS).Ideally, operational amplifier has and infinitely opens loop gain and zero output resistance.Yet, the actual operation amplifier be finite gain and the non-zero output resistance.Operational amplifier 202 has adjustable finite gain.
With V THAs the critical voltage of NMOS 108, VREF NEW1And the relationship description between the VirtualVSS is as follows:
VREF NEW 1 - VirtualVSS = 2 I out μ N C ox K ( W L ) + I ref R S + V TH , - - - ( 3 )
Wherein I ref R S = 2 I ref μ N C ox ( W L ) ( 1 - 1 k ) - - - ( 4 )
Therefore, at equation 4, as the I of equation 1 RefIncrease, because finite gain, first VirtualVSS increases and increases along with temperature, and operational amplifier 202 can not keep the accurate position of VirtualVSS to ground connection.Because critical voltage V THDescend, second of equation 4 increases and reduces along with temperature.Therefore, VREF NEW1Have little temperature variations because first of equation 4 (VirtualVSS) rise along with temperature and increase and second rise along with temperature and reduce.The gain of adjusting operational amplifier 202 is to find the performance of suitable temperature compensation.
In the embodiment of an integrated circuit, electric current I ref is set at 5 μ A, and the nmos pass transistor dimension scale is 1: K=1: 4 (K is the number greater than 1), and resistance R s is 8k ohm.In other embodiment, electric current I ref scope is at 2-10 μ A, and K is between 4-16, and Rs is at 1-40k ohm.Yet circuit can different numerical Design under spirit of the present invention and the scope not breaking away from.
Fig. 2 B is the plot that the temperature of the embodiment of the reference circuits shown in Fig. 2 A is exported voltage.Be presented at-10 temperature range 5mV changes of spending, do not have the reference circuits of temperature compensation to show that the 18mV change is significantly improved with respect to Figure 1A to 125 degree.
Fig. 3 A is the circuit diagram of reference circuits that is used for the example with temperature compensation of constant mutual conductance design according to the present invention.Under this structure, be connected to the grid of the NMOS 310 of right side additional circuit 300 from the VREF of left side constant mutual conductance Voltage Reference.The constant mutual conductance reference circuits that the similar left sides of additional circuit 300 show, but be substituted in the Rs110 of constant mutual conductance reference circuits with NMOS 310.Grid by the VREF that connects the left side circuit to right side NMOS 310 rises along with temperature and the VREF that reduces by the source electrode that increases NMOS310-resistance compensation.
With R TXAs source electrode-resistance of NMOS 310, output voltage is represented as follows:
VREF NEW 2 = V TH 2 + 2 I out μ N C ox K ( W L ) N + I ref + R TX - - - ( 5 )
VREF NEW 2 = V TH 2 + 2 I out μ N C ox K ( W L ) N + I ref + R TX - - - ( 6 )
When increasing temperature,, therefore increase the resistance R of NMOS 310 from VREF bias voltage NMOS 310 grids of the reduction of left side circuit TXThe advantage of this structure comprises by increasing the simple and easy enforcement elasticity of similar circuit to the Voltage Reference design.The size of NMOS 310 can be designed to have the resistance R of wanting TX
At an integrated circuit embodiment, electric current I ref is set at 5 μ A, the nmos pass transistor dimension scale is between 1 between nmos pass transistor 106 and 108 and/or between 306 and 308: N=1: 4 (N is the number greater than 1), resistance R s is that the source electrode-drain resistance Rds of 8k ohm and nmos pass transistor 310 is 8k ohm.In other embodiment, electric current I ref scope is at 2-10 μ A, and N is between 4-16, and Rs is at 1-40k ohm.Yet circuit can different numerical Design under spirit of the present invention and the scope not breaking away from.
Fig. 3 B is the plot that the temperature of the embodiment of the reference circuits shown in Fig. 3 A is exported voltage.VREF OLDTemperature change-40 spend to 125 the degree temperature ranges are 18mV, but the VREF of temperature compensation NEW2The 3mV change is only arranged.
Therefore, by increasing the temperature compensation feedback element to control the transformation variation,, can finish output voltage precision and need the very constant mutual conductance reference circuits of small size and power with obvious improvement compared to the band gap design.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.

Claims (10)

1. reference circuits with temperature compensation comprises:
One power supply;
One reference voltage;
One the one PMOS transistor has one source pole and is connected to this power supply;
One the 2nd PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of a PMOS;
One first nmos pass transistor has a grid and one source pole and is connected to transistorized this drain electrode of a PMOS;
One second nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 2nd PMOS, and a grid is connected to this grid and this reference voltage of this first nmos pass transistor;
One resistor is connected to this source electrode and the ground connection of this second nmos pass transistor; And
One operational amplifier has a reverse input end, a non-inverting input and an output terminal;
Wherein this reverse input end connects this source electrode of this output terminal and this first nmos pass transistor, and this non-return input is connected to ground connection.
2. the reference circuits with temperature compensation as claimed in claim 1, wherein this first nmos pass transistor and this second nmos pass transistor have 1: the dimension scale of K, wherein this dimension scale be defined as a transistorized raceway groove a width divided by a length, and K is the number greater than 1.
3. the reference circuits with temperature compensation as claimed in claim 1, wherein K is between 4-6.
4. the reference circuits with temperature compensation as claimed in claim 1, wherein the resistance of this resistor is between 1-40k ohm.
5. reference circuits with temperature compensation comprises:
One power supply;
One reference voltage;
One the one PMOS transistor has one source pole and is connected to this power supply;
One the 2nd PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of a PMOS;
One first nmos pass transistor has a grid and a drain electrode is connected to transistorized this drain electrode of a PMOS;
One second nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 2nd PMOS, and a grid is connected to this grid and this reference voltage of this first nmos pass transistor;
One resistor is connected to this source electrode and the ground connection of this second nmos pass transistor;
One second reference voltage;
One the 3rd PMOS transistor has one source pole and is connected to this power supply;
One the 4th PMOS transistor has one source pole and is connected to this power supply, and a grid and a drain electrode are connected to this grid of the 3rd PMOS;
One the 3rd nmos pass transistor has a grid and a drain electrode is connected to transistorized this drain electrode of the 3rd PMOS;
One the 4th nmos pass transistor has a drain electrode and be connected to transistorized this drain electrode of the 4th PMOS, and a grid is connected to this grid and this second reference power source of the 3rd nmos pass transistor;
One the 5th nmos pass transistor has this source electrode that a drain electrode is connected to the 4th nmos pass transistor, and one source pole is connected to ground connection, and a grid is connected to this first reference voltage.
6. the reference circuits with temperature compensation as claimed in claim 5, wherein the dimension scale of this first nmos pass transistor and second nmos pass transistor is 1: K, wherein dimension scale be the width that is defined as a transistorized raceway groove divided by a length and K is a number greater than 1.
7. the reference circuits with temperature compensation as claimed in claim 6, wherein the scope of K is between 4-16.
8. the reference circuits with temperature compensation as claimed in claim 5, wherein the dimension scale of the 3rd nmos pass transistor and the 4th nmos pass transistor is 1: N, wherein dimension scale be the width that is defined as a transistorized raceway groove divided by a length and N is a number greater than 1.
9. the reference circuits with temperature compensation as claimed in claim 8, wherein the scope of N is between 4-16.
10. the reference circuits with temperature compensation as claimed in claim 5, wherein the resistance range of this resistor is between 1-40K ohm, and the source electrode of the 5th nmos pass transistor-drain resistance scope is between 1-40K ohm.
CN201010222579.8A 2009-07-02 2010-07-02 Voltage reference circuit with temperature compensation Expired - Fee Related CN101943926B (en)

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US22285209P 2009-07-02 2009-07-02
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US12/825,652 US8575998B2 (en) 2009-07-02 2010-06-29 Voltage reference circuit with temperature compensation
US12/825,652 2010-06-29

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US9312280B2 (en) * 2014-07-25 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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US10185337B1 (en) * 2018-04-04 2019-01-22 Qualcomm Incorporated Low-power temperature-insensitive current bias circuit
US11752306B2 (en) 2021-01-22 2023-09-12 Luther Needlesafe Products, Llc Low profile passive protector for an I.V. catheter
USD979746S1 (en) 2021-02-26 2023-02-28 Luther Needlesafe Products, Llc Over-the-needle catheter insertion device
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US20140035553A1 (en) 2014-02-06
US9442506B2 (en) 2016-09-13
US8575998B2 (en) 2013-11-05
US20110001557A1 (en) 2011-01-06
CN101943926B (en) 2014-01-29

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