CN101943811B - Flat panel display panel - Google Patents
Flat panel display panel Download PDFInfo
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- CN101943811B CN101943811B CN2009101588043A CN200910158804A CN101943811B CN 101943811 B CN101943811 B CN 101943811B CN 2009101588043 A CN2009101588043 A CN 2009101588043A CN 200910158804 A CN200910158804 A CN 200910158804A CN 101943811 B CN101943811 B CN 101943811B
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Abstract
A flat panel display panel comprises a thin-film transistor (TFT) array substrate and a color filter substrate arranged oppositely, wherein a plurality of first electrodes and second electrodes are arranged on the TFT array substrate; the first electrodes receive a plurality of scanning signals from a drive circuit; each second electrode is connected with a corresponding scanning line; a plurality of signal lines are formed on the color filter substrate and are configured in an active area; a plurality of third electrodes and fourth electrodes are arranged on the color filter substrate; each third electrode is electrically connected with a corresponding first electrode and a corresponding signal line; and each fourth electrode is electrically connected with a corresponding second electrode and a corresponding signal line.
Description
Technical field
The present invention relates to a kind of flat display panel, particularly about a kind of flat display panel of narrow margo frontalis.
Background technology
Please refer to Fig. 1, it shows the schematic top plan view of known flat display panel.Show among the figure that display panels 10 comprises a plurality of groups of substrates of thin-film transistor (TFT array substrate) 102 and stacks on the filter sheet base plate (color filter substrate) 104 on the membrane transistor multiple substrate 102.Membrane transistor multiple substrate 102 is provided with the data line (not illustrating) that scanning linear 106 that many horizontal directions arrange and vertical direction are arranged, and scanning linear 106 intersects with data line and defines a viewing area (Active Area, AA) 112.Each bar scanning linear 106 is to interconnect with a lead 108 and one drive circuit 110, to receive the signal that scans from driving circuit 110.
For example, (its resolution is 640*480 for Video Graphics Array, a VGA) panel of LCD of standard to be suitable for the visual graphic array.If with this standard design, can lead 108 configurations be needed the dual-side at display panels 10 usually, then each side has 320 lead 108.The live width of supposing each bar lead 108 is 2.5 μ m, and the spacing between two adjacent wires 108 is 3 μ m, then the overall width of 320 leads 108 be 2.5*320+3*319=1757 μ m=1.757mm (centimetre).In prediction on such basis, the width W of margo frontalis approximately needs about 2mm just enough.In other words, the width that the margo frontalis total of the dual-side of display panels 10 needs to reserve 4mm so can reduce the area of viewing area 102 in order to lay lead 108 and other circuit.
Summary of the invention
Embodiments of the invention provide a kind of flat display panel that the width of margo frontalis is effectively dwindled.
According to the design of one embodiment of the invention, a kind of flat display panel comprises the filter sheet base plate that a membrane transistor multiple substrate, subtend are provided with.Be formed with many sweep trace and many data lines of arranging along a second direction of arranging along a first direction on the membrane transistor multiple substrate.A plurality of first electrodes and second electrode are located on the membrane transistor multiple substrate, and those first electrodes receive a plurality of sweep signals from one drive circuit, and each second electrode connects a corresponding sweep trace.Be formed with many signal line on the filter sheet base plate, and these signal wires be disposed at the viewing area (active area, AA) in.A plurality of third electrodes and the 4th electrode are located on the filter sheet base plate, and wherein each third electrode electrically connects first a corresponding electrode and a corresponding signal line, and each the 4th electrode electrically connects second a corresponding electrode and a corresponding signal line.
In an embodiment, filter sheet base plate has a black matrix", and this black matrix" is made up of the black matrix" of part by the signal wire of conductive material and connection third electrode and the 4th electrode.The black matrix" material can be the material that is doped with black in chromium (Cr) or chromium oxide (CrO) or the metal.At this moment, each signal line has along two line segments of first direction and second direction configuration.
In an embodiment, filter sheet base plate has a black matrix", and this black matrix" is the resin material, and preferably, the signal wire that connects third electrode and the 4th electrode is arranged on the surface of black matrix".At this moment, each signal line has along two line segments of first direction and second direction configuration.In addition, when the signal wire that connects third electrode and the 4th electrode was transparency electrode, then signal wire can be along the surface distributed of black matrix".
In an embodiment, first electrode is to electrically conduct through conductive gap (conductive spacer) and third electrode, and likewise, second electrode is to electrically conduct with the 4th electrode through conductive gap.Usually, be provided with a frame glue between membrane transistor multiple substrate and this filter sheet base plate, and this frame glue is doped with conductive gap and covers first electrode, second electrode, third electrode and the 4th electrode.
In an embodiment, second electrode can be distributed in the dual-side of viewing area, for example is limit, the left and right sides, and the some of second electrode neighbor configuration are in left side, and corresponding each bar odd number bar sweep trace that connects.Remaining second electrode neighbor configuration is in right edge, and the corresponding even number bar sweep trace that connects.
In an embodiment, be provided with a liquid crystal layer between membrane transistor multiple substrate and the filter sheet base plate to form a panel of LCD.Yet; Aforementioned each embodiment is not limited to panel of LCD; Also go for having other display pannel of filter sheet base plate; Electrophoretic display device (EPD) (electrophoresis display, EPD) panel, electric wet-type display (electrowetting display, EWD) panel, organic LED panel (OLED) for example.
Other purpose of the present invention and advantage can further be understood from the technical characterictic that the present invention disclosed.For let above and other objects of the present invention, feature and advantage can be more obviously understandable, special embodiment and the conjunction with figs. of lifting of hereinafter elaborates as follows.
Description of drawings
Fig. 1 is the schematic top plan view of a known flat display panel.
Fig. 2 is the schematic top plan view according to the flat display panel of one embodiment of the invention.
Fig. 3 is the subregion enlarged diagram according to the membrane transistor multiple substrate of Fig. 2.
Fig. 4 is the subregion enlarged diagram according to the filter sheet base plate of Fig. 2.
Fig. 5 is along Fig. 3 A-A line and along the diagrammatic cross-section of Fig. 4 B-B line.
Fig. 6 is the schematic top plan view according to the flat display panel of another embodiment of the present invention.
Symbol description
10,20,30 flat display panels, 102,202,302 membrane transistor multiple substrates
104,204,304 filter sheet base plates, 106,206 sweep traces
108,216 leads, 110,210,303 driving circuits
112 viewing area AA, 114,220 frame glue
201,203 transparency carriers, 207,209 insulation courses
205 black matrix"s, 208 data lines
211 conductive gap, 212,306 first electrodes
213,308 second electrodes, 214,310 third electrodes
215,312 the 4th electrodes, 218,316 signal wires
W, W ' margo frontalis width
Embodiment
Please refer to Fig. 2, this is the schematic top plan view according to the flat display panel of one embodiment of the invention.Flat-panel screens 20 comprises a filter sheet base plate 204 of a membrane transistor multiple substrate 202 and subtend setting.Between membrane transistor multiple substrate and filter sheet base plate, be provided with a liquid crystal layer and then form a panel of LCD.Yet; The present invention also go for other have filter sheet base plate but do not comprise liquid crystal layer other display pannel; For example electrophoretic display device (EPD) (EPD) panel, electric wet-type display (EWD) panel, organic LED panel (OLED) etc. do not limit at this.For the convenience on explaining, following embodiment all is the example explanation with the panel of LCD.
Be formed with many sweep trace 206 and many data lines of arranging along a second direction 208 of arranging along a first direction on the membrane transistor multiple substrate 202.At this, first direction is the horizontal direction D1 shown in figure, and second direction is vertical direction D2.And because membrane transistor multiple substrate 202 repeatedly places the below of filter sheet base plate 204, so sweep trace 206 data lines 208 all are represented by dotted lines.In addition, membrane transistor multiple substrate 202 is provided with a plurality of first electrodes 212 and second electrode 213, and correspondence is arranged at a plurality of third electrodes 214 and the 4th electrode 215 on the filter sheet base plate 204.Preferably, each first electrode 212 is provided with corresponding to a third electrode 214, and each second electrode 213 is provided with corresponding to one the 4th electrode 215.Wherein, first electrode 212 is conductings with corresponding third electrode 214, and second electrode 213 also is conducting with the 4th corresponding electrode 215.The mode of conducting has a variety of, for example can be through conductive gap with two electrode mutual conduction, and this part is waited until the back and is detailed.Be provided with one drive circuit 210 near contiguous second electrode 212, and the output signal of driving circuit 210 can be connected to first electrode 212 with as scanning signal through lead 216 thus.Because; The two ends of each signal line 218 are to connect a third electrode 214 and one the 4th electrode 215; Therefore; By each of driving circuit 210 output scan signal can be in regular turn via the 4th electrode 215 on first electrode 212 on lead 216, the membrane transistor multiple substrate 202, the third electrode 214, signal wire 218, filter sheet base plate 204 on the filter sheet base plate 204, second electrode 213 on the membrane transistor multiple substrate 202; Be input to each bar scanning linear 206 at last to drive viewing area (active area, the picture element switch in AA).In addition; Driving circuit 210 can be a chip for driving (chip) or (the system on glass of system on glass; SOG) the formed circuit of processing procedure for example is to be formed directly into driving circuit on glass with low temperature polycrystalline silicon (LTPS), microcrystal silicon (Micro-C), amorphous silicon processing procedures such as (a-Si).
Therefore present embodiment, is different from lead as shown in fig. 1 108 laying modes owing to be that the signal wire 218 that transmission scans signal is laid on the filter sheet base plate 204.Because signal wire 218 can't connect the scanning linear 206 in the AA of viewing area via the frontal border area of viewing area AA side, so the frontal border area width W ' is dwindled significantly.In other words, the frontal border area of present embodiment has only second electrode 213 and other circuit is set, and lays the lead that connects driving circuit and scanning linear, so can reach the effect of narrow margo frontalis.The panel that with resolution is 640*480 is an example, is 4mm with respect to the margo frontalis width 2W of total panel both sides shown in Figure 1, the total both sides margo frontalis width 2W ' of present embodiment can be reduced to 1.2mm with interior or even littler, the amount of decrease Da Gaoda of margo frontalis is more than 70%.
Please be simultaneously with reference to figure 3～Fig. 5; Wherein, Fig. 3 is the subregion enlarged diagram according to the membrane transistor multiple substrate of Fig. 2, and Fig. 4 is the subregion enlarged diagram according to the filter sheet base plate of Fig. 2, and Fig. 5 is along Fig. 3 A-A line and along the diagrammatic cross-section of Fig. 4 B-B line.
In Fig. 3, the right side edge position of membrane transistor multiple substrate 202 is provided with first electrode 212, and AA below in viewing area is near being provided with second electrode 213 near the driving circuit 210.First electrode 212 connects lead 216, the second electrodes 213 and connects sweep trace 206.Wherein, first electrode 212 and second electrode 213 material can be metal, indium tin oxide (indium tin oxide, ITO), indium-zinc oxide (indium zinc oxide, IZO) or the combination of above-mentioned material.
Fig. 4 display filter substrate 204 is provided with black matrix" 205.Black matrix" 205 is for conductive material or tree refer to material, and black matrix" 205 in the present embodiment is that the conductive material of act is an example, for example is to be chromium (Cr) or chromium oxide (CrO).When but black matrix" 205 was conductive material, the subregion that can directly utilize black matrix" 205 was as the signal wire 218 that connects third electrode 214 and the 4th electrode 215.At this moment, the part black matrix" 205 of being treated as signal wire 218 is through suitable design, takes place to avoid the short circuit between adjacent two signal wires 218.Owing to be to treat as signal wire 218, so each signal line 218 all has along two line segments of vertical direction D2 and horizontal direction D1 extension, to form the shape of approximate L simultaneously with black matrix" 205.Third electrode 214 is provided with corresponding to the position of first electrode 212, preferably, is to be provided with the mode of a third electrode 214 corresponding to one first electrode 212.Likewise, each the 4th electrode 215 also is provided with corresponding to the position of one second electrode 213.Third electrode 214 and the 4th electrode 215 material can be metal, indium tin oxide (indium tin oxide, ITO), indium-zinc oxide (indium zinc oxide, IZO) or the combination of above-mentioned material.
Fig. 5 shows the diagrammatic cross-section of membrane transistor multiple substrate 202 and filter sheet base plate 204, and a liquid crystal layer 222 is arranged between membrane transistor multiple substrate 202 and the filter sheet base plate 204.Membrane transistor multiple substrate 202 comprises metal level (lead 206 and sweep trace 216), a layer insulating 203, first electrode 212 and second electrode 213 of a transparency carrier 201, a patterned.Filter sheet base plate 204 comprises a transparency carrier 203, a black matrix" 205, an insulation course 209, third electrode 214 and the 4th electrode 215.Shown in figure, a plurality of conductive gap 211 are established as between membrane transistor multiple substrate 202 and the filter sheet base plate 204, use conducting first electrode 212 and third electrode 214, and conducting second electrode 213 and the 4th electrode 215.Thus; By each of driving circuit 210 output scan signal can be in regular turn via lead 216, first electrode 212, conductive gap 211, third electrode 214, signal wire 218, the 4th electrode 215, conductive gap 211, second electrode 213, be input to corresponding scanning linear 206 at last.
In addition; Black matrix" 205 can not be a conductive material also; If for example black matrix" 205 is when adopting the resin material; Then signal wire 218 is arranged between surface and the insulation course 209 of black matrix" 205 (not illustrating), and along the surface placement of black matrix" 205 to connect third electrode 214 and the 4th electrode 215.The technical skill of this kind design and above-mentioned embodiment are similar, repeat no more.
In addition, can be provided with a frame glue (sealant) 220 between membrane transistor multiple substrate 202 and the filter sheet base plate 204 usually with as isolation layer, and be filled with a liquid crystal layer 222 as viewing area AA in the space that centered on of frame glue 220.Wherein, frame glue 220 is doped with conductive gap son 211 and covers first electrode 212, second electrode 213, third electrode 214 and the 4th electrode 215.On the practice; Can earlier conductive gap 211 be doped in the frame glue 220; Coat patterned membrane transistor multiple substrate 202 or filter sheet base plate 204 wherein on a slice, solidify after then again membrane transistor multiple substrate 202 and filter sheet base plate 204 being fitted each other.
The above embodiments are that signal wire 218, second electrode 213, the 4th electrode 215 are concentrated the right sides that are arranged on flat display panel 20.Yet second electrode 213 and the 4th electrode 215 also can disperse to be arranged at the left and right sides of flat display panel 20 in fact.Please refer to the 6th figure, Fig. 6 is the schematic top plan view according to the flat display panel of another embodiment of the present invention.At this, flat display panel 30 is no longer given unnecessary details with the something in common of the flat display panel 20 of previous embodiment, below only explains with regard to difference.
Shown in figure, a plurality of first electrodes 306 are configured in a membrane transistor multiple substrate 202 belows near near the one drive circuit 303, and wherein, that be configured in the lower left is the first electrode 306a, is the first electrode 306b and be configured in bottom-right.Likewise, a plurality of second electrodes 308 that are arranged at membrane transistor multiple substrate 202 both sides can be divided into second electrode 308a that is positioned at the left side and the second electrode 308b that is positioned at the right side again.Wherein, the second electrode 308a that is positioned at the left side connects the scanning linear 314a of odd number bar, for example is the 1st, 3, the 5......N bar, and N is a positive integer.On the contrary, the second electrode 308b that is positioned at the right side connects the scanning linear 314b of even number bar, for example is the 2nd, 4,6...... (N+1) bar.
On the other hand, a plurality of third electrodes 310 are configured in a filter sheet base plate 204 belows and corresponding first electrode 306 of difference, and wherein, that be configured in the lower left is third electrode 310a, is third electrode 310b and be configured in bottom-right.And the both sides of filter sheet base plate 204 also are provided with a plurality of the 4th electrode 312a and the 312b that correspond respectively to the second electrode 308a, 308b.Be formed at filter sheet base plate 204 lip-deep signal wires 316 and connect third electrode 310 and the 4th electrode 312 with man-to-man mode.That is the signal wire 316a in left side connects third electrode 310a and the 4th electrode 312a, and the signal wire 316b on right side connects third electrode 310b and the 4th electrode 312b.Such design has its benefit; For instance;, driving circuit 303 (do not illustrate) when being the chip for driving more than at least two; The mode that can pass through present embodiment makes things convenient for the layout of circuit with electrode 306～312 and signal wire 316 separated into two parts, is applicable to the panel of large-size.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is when being as the criterion according to the content that claim defined.In addition, arbitrary embodiment of the present invention or protection domain must not reached whole purposes or advantage or the characteristics that the present invention discloses.In addition, summary part and title only are the usefulness that is used for assisting the patent document search, are not to be used for limiting protection scope of the present invention.
Claims (8)
1. a flat display panel is characterized in that, comprises:
One membrane transistor multiple substrate has many sweep trace and many data lines of arranging along a second direction of arranging along a first direction, and this first direction and this second direction intersect;
Said sweep trace and said data line intersect and define a viewing area;
A plurality of first electrodes and second electrode; Be located on the lateral margin position, said viewing area between this membrane transistor multiple substrate and the filter sheet base plate; Those first electrodes receive a plurality of sweep signals from least one driving circuit, and those second electrodes connect those sweep traces;
Said filter sheet base plate has many signal line; And
A plurality of conductive gap are arranged between said membrane transistor multiple substrate and the filter sheet base plate;
A plurality of third electrodes and the 4th electrode; Be located on the lateral margin position of viewing area of corresponding said first electrode and said second electrode; Those third electrodes electrically connect those first electrodes and those signal wires through said conductive gap, and those the 4th electrodes electrically connect those second electrodes and those signal wires through said conductive gap;
Wherein, be provided with a frame glue between membrane transistor multiple substrate and this filter sheet base plate, and this frame glue is doped with said conductive gap and covers first electrode, second electrode, third electrode and the 4th electrode.
2. flat display panel according to claim 1 is characterized in that this filter sheet base plate has a black matrix", and this black matrix" is made up of this black matrix" of part by conductive material and those signal wires.
3. flat display panel according to claim 1 is characterized in that this filter sheet base plate has a black matrix", and this black matrix" is the resin material, and those signal wires are arranged on this black matrix".
4. flat display panel according to claim 1; It is characterized in that the material of those first electrodes, those second electrodes, those third electrodes and those the 4th electrodes is the combinations for indium tin oxide, indium-zinc oxide, metal or above-mentioned material.
5. flat display panel according to claim 1 is characterized in that, those signal wires have along two line segments of this first direction and the configuration of this second direction simultaneously.
6. flat display panel according to claim 1; It is characterized in that; Those second electrode neighbor configuration of part are in an end of those sweep traces; And connect odd number bar sweep trace, remaining those second electrode neighbor configuration is in an other end of those sweep traces, and connection even number bar sweep trace.
7. flat display panel according to claim 1 is characterized in that, this flat display panel be panel of LCD, electrophoresis display panel, electric wet-type display panel and organic LED panel one of them.
8. flat display panel according to claim 1 is characterized in that this driving circuit is a circuit system on glass, comprises with wherein a kind of technology of low temperature polycrystalline silicon, microcrystal silicon, amorphous silicon to be formed directly into driving circuit on glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101588043A CN101943811B (en) | 2009-07-06 | 2009-07-06 | Flat panel display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101588043A CN101943811B (en) | 2009-07-06 | 2009-07-06 | Flat panel display panel |
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| Publication Number | Publication Date |
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| CN101943811A CN101943811A (en) | 2011-01-12 |
| CN101943811B true CN101943811B (en) | 2012-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009101588043A Expired - Fee Related CN101943811B (en) | 2009-07-06 | 2009-07-06 | Flat panel display panel |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI444743B (en) * | 2011-08-16 | 2014-07-11 | E Ink Holdings Inc | Display device and method for manufacturing the same |
| CN103135287B (en) * | 2011-11-22 | 2016-08-17 | 上海天马微电子有限公司 | Spacer and display panels |
| CN103700669A (en) * | 2013-12-19 | 2014-04-02 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof as well as display device |
| CN105068294B (en) * | 2015-08-25 | 2018-01-12 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel and device |
| CN105068300A (en) * | 2015-08-25 | 2015-11-18 | 深圳市华星光电技术有限公司 | Display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412739A (en) * | 2001-09-27 | 2003-04-23 | 三星电子株式会社 | Liquid crystal display |
| CN1164969C (en) * | 2000-06-19 | 2004-09-01 | 夏普株式会社 | Liquid crystal display including driving circuit system |
| CN101149500A (en) * | 2006-09-18 | 2008-03-26 | 三星电子株式会社 | Display apparatus |
-
2009
- 2009-07-06 CN CN2009101588043A patent/CN101943811B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1164969C (en) * | 2000-06-19 | 2004-09-01 | 夏普株式会社 | Liquid crystal display including driving circuit system |
| CN1412739A (en) * | 2001-09-27 | 2003-04-23 | 三星电子株式会社 | Liquid crystal display |
| CN101149500A (en) * | 2006-09-18 | 2008-03-26 | 三星电子株式会社 | Display apparatus |
Non-Patent Citations (3)
| Title |
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| JP特开2007-17828A 2007.01.25 |
| JP特开平10-303431A 1998.11.13 |
| JP特开平11-45072A 1999.02.16 |
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