CN101937917A - Electrostatic discharge safeguard structure in integrated circuit - Google Patents
Electrostatic discharge safeguard structure in integrated circuit Download PDFInfo
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- CN101937917A CN101937917A CN 201010268550 CN201010268550A CN101937917A CN 101937917 A CN101937917 A CN 101937917A CN 201010268550 CN201010268550 CN 201010268550 CN 201010268550 A CN201010268550 A CN 201010268550A CN 101937917 A CN101937917 A CN 101937917A
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Abstract
The invention relates to an electrostatic discharge safeguard structure in an integrated circuit, which comprises a first-class electrostatic discharge safeguard component and a second-class electrostatic discharge safeguard component, wherein the first-class electrostatic discharge safeguard component is a diode; the second-class electrostatic discharge safeguard component is a subsection doublestage transistor with a Zener diode; the subsection doublestage transistor with the Zener diode comprises a subsection doublestage transistor, an emitter series resistor, a collector series resistor, a base resistor and the Zener diode; the electrostatic discharge safeguard structure of the integrated circuit provides electrostatic discharge safeguard for an input buffer, an output buffer, a power trajectory and a ground trajectory; and the electrostatic discharge safeguard component utilizes a subsection doublestage transistor structure in a domain territory and a fictive poly gate structure in each section doublestage transistor to form a series resistor of the Zener diode with low trigger voltage, an emitter and a collector. The invention effectively enhances the electrostatic discharge safeguard capability of the integrated circuit, reduces the trigger voltage of an electrostatic discharge safeguard circuit, enhances the uniform continuity of the electrostatic discharge safeguard component and effectively saves the domain territory area of the electrostatic discharge safeguard component.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protection structure, particularly relate to the structure that a kind of design by circuit and domain improves static discahrge protection effect, belong to integrated circuit electrostatic defending technical field.
Background technology
Static discharge is one of most important integrity problem in the current CMOS integrated circuit.Along with the high speed development of very lagre scale integrated circuit (VLSIC) technology, characteristic size has entered the deep-submicron stage, has improved the performance and the arithmetic speed of integrated circuit greatly.But reducing of device size caused the device also raising greatly of sensitivity of electromagnetic interference to external world, makes static discharge become more and more significant to the harm of device reliability.
On the other hand, along with the raising of integrated circuit signal transmission speed, the time-delay that the electrostatic storage deflection (ESD) protection circuit at input/output interface place causes has brought very big influence to high speed circuit.Must improve electrostatic discharge protection structure, make it to match, thereby make chip have better interface capability with the input/output interface circuit.Along with the raising and the mixed-voltage The Application of Technology of chip integration, make the complexity of electrostatic storage deflection (ESD) protection circuit also promote greatly.
In the former research, in deep submicron integrated circuit, mainly be to use cmos device and silicon-controlled device to realize electrostatic discharge protection component.Along with reducing of integrated circuit characteristic size, cmos device need take bigger chip area as electrostatic discharge protection component, and has the shortcoming of non-homogeneous conducting.And silicon-controlled device has higher trigger voltage as electrostatic discharge protection component, and may cause latch phenomenon, has certain difficulty on design realizes.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, electrostatic discharge protective problem at deep submicron integrated circuit, a kind of novel electrostatic discharge protection structure is provided, this structure is used a kind of novel segmentation bipolar transistor with zener diode structure, has realized the electrostatic discharge protective network of integrated circuit.The present invention has overcome the non-homogeneous conducting of cmos device, and shortcomings such as higher trigger voltage of SCR structure and easy initiation breech lock, has reduced the shared chip area of electrostatic discharge protection component simultaneously.
Technical solution of the present invention is: electrostatic discharge protection structure in a kind of integrated circuit, comprise the first kind electrostatic discharge protection component and the second class electrostatic discharge protection component, use at least one to be connected the first kind electrostatic discharge protection component of importing between pressure welding point and power track, at least one is connected input pressure welding point and the ground second class electrostatic discharge protection component and at least one steady resistance input buffer of protecting integrated circuit between path, use at least one be connected first kind electrostatic discharge protection component between output pressure welding point and power track and at least one be connected the output pressure welding point and the second class electrostatic discharge protection component between path protect the output buffer of integrated circuit; Use at least one to be connected power track and the ground second class electrostatic discharge protection component between path and protect device between power track and the ground path; wherein first kind electrostatic discharge protection component is a diode; the second class electrostatic discharge protection component is to bring all to receive the segmentation two-stage transistor of diode, brings all to receive segmentation two-stage transistor being made up of with Zener diode segmentation two-stage transistor, emitter series resistance, collector series resistance, base resistance of diode.
Described bringing all received the segmentation two-stage transistor course of processing of diode and realized by following steps,
The first step is to carry out oxidate on the base stage at the P-substrate, forms first shallow trench isolation region and second shallow trench isolation region, and the resistance of base stage is base resistance;
Second step, below second shallow trench isolation region, carry out the N type and inject, form the N-trap, base stage and N-trap constitute parasitic diode;
The 3rd step, on first shallow trench isolation region, carry out oxidation, form gate oxide;
The 4th step, on gate oxide, carry out polysilicon deposition, form polysilicon layer;
The 5th step, carry out the silicon nitride deposition in the polysilicon layer both sides, form first and second silicon nitride side wall;
The 6th step, carry out the injection of N type in the first silicon nitride side wall left side and the first shallow trench isolation region right side, form first and second N++ active area, first and second N++ active area and base stage constitute a section in the segmentation two-stage transistor, wherein a N++ active area is a collector electrode, and the 2nd N++ active area is an emitter;
The 7th step, below first and second N++ active area, carry out the N type and inject, form first and second N+ district;
The 8th step, below a N+ district, carry out the P type and inject, form the P active area, a N+ district and P active area constitute Zener diode;
The 9th step, carry out the P type in second shallow trench isolation region left side and inject, form the P+ active area;
The tenth step, high annealing;
The 11 step, on the close first silicon nitride side wall part of a N++ active area, carry out oxidate, forming first blocking layer of metal silicide is collector series resistance, carry out oxidate on close first shallow trench isolation region part of the 2nd N++ active area, forming second blocking layer of metal silicide is the emitter series resistance;
In the 12 step,, form the 3rd metal silicide region in the enterprising row metal silicide deposition of P+ active area, in the enterprising row metal silicide deposition of a N++ active area, form first metal silicide region,, form second metal silicide region in the enterprising row metal silicide deposition of the 2nd N++ active area;
In the 13 step, in the enterprising row metal deposition of first, second and third metal silicide region, the contact of formation collector electrode metal, emitter metal contact contact with base metal, finish a section in the segmentation two-stage transistor;
The 14 step, repeated for first～the 13 step, obtain each section in the segmentation two-stage transistor simultaneously, transistorized each segment base of segmentation twin-stage is extremely continuous, each section emitter links to each other, and first blocking layer of metal silicide on each section collector electrode links to each other by the isolation of the 3rd shallow trench isolation region, first metal silicide region.
First shallow trench isolation region is that the width of the shallow trench isolation areas between collector electrode and the emitter is not less than 0.8 micron in the described first step.
The 3rd shallow-trench isolation sector width is not less than 0.4 micron in described the 14 step.
First and second N++ active area that described the 6th step forms is than the high order of magnitude of doping content in first and second N+ district of described the 7th step formation.
Described bringing all received the segmentation two-stage transistor of diode and is at least 3 sections.
Described diode comprises anode injection zone, negative electrode injection zone, N-well area and substrate contact region territory, and each area level figure all adopts 45 degree turnings in domain.
First and second N++ active area that described the 6th step forms uses arsenic element to mix, and first and second N+ district that described the 7th step forms uses P elements to mix, and the P active area that described the 8th step forms uses boron element to mix.
The present invention compared with prior art beneficial effect is:
(1) the present invention has been owing to used the layout design structure of segmentation, and adds series resistance respectively, the even conduction of electrostatic discharge protection component when having improved static discharge at the emitter and collector of bipolar transistor;
(2) the present invention has added zener diode structure in the segment of double gated transistors, has reduced the trigger point of electrostatic discharge protection component and has pressed, thereby can do sth. in advance the bleed off static discharge current, avoids other device of circuit to damage because of static discharge;
(3) the present invention has used twice N type active area to inject in the segment of double gated transistors, has strengthened the junction depth of bipolar transistor emitter and collector; Simultaneously, used illusory polysilicon grating structure, limited the position that P type Zener injects, made its edge away from the device shallow-trench isolation; This two aspect has promoted electrostatic discharge protection component self and has born the ability of static discharge current, thereby has saved the shared chip area of electro-static discharging device.
Description of drawings
Fig. 1 is electrostatic discharge protection structure circuit diagram among the present invention;
Fig. 2 receives the segment of double gated transistors single hop profile of diode for the present invention brings all;
Fig. 3 receives the structure chart of segment of double gated transistors of diode for the present invention brings all;
Fig. 4 is the domain example of diode of the present invention;
Fig. 5 receives the domain example of segment of double gated transistors of diode for the present invention brings all.
Embodiment
The present invention is described in detail below in conjunction with specific embodiment.
As shown in Figure 1, input buffer is made up of PMOS transistor 105 and nmos pass transistor 106.The source electrode of PMOS transistor 105 links to each other with power track 101, and the source electrode of nmos pass transistor 106 links to each other with ground path 102.PMOS transistor 105 links to each other with the drain electrode of nmos pass transistor 106, imports signal into chip internal.PMOS transistor 105 links to each other with the grid of nmos pass transistor 106, and links to each other with input pressure welding point 103 by resistance 114.Output buffer is made up of PMOS transistor 107 and nmos pass transistor 108.The source electrode of PMOS transistor 107 links to each other with power track 101, and the source electrode of nmos pass transistor 108 links to each other with ground path 102.PMOS transistor 107 links to each other with the grid of nmos pass transistor 108, accepts the signal of internal circuit output.PMOS transistor 107 links to each other with the drain electrode of nmos pass transistor 108, and links to each other with output pressure welding point 104.
Electrostatic storage deflection (ESD) protection circuit is made up of first kind electrostatic discharge protection component 109,111 and the second class electrostatic discharge protection component 110,112,113 and resistance 114.
Electrostatic discharge protection component 109 is made up of diode 201, and an end of electrostatic discharge protection component 109 links to each other with power track 101, and the other end links to each other with input pressure welding point 103.Electrostatic discharge protection component 111 is made up of diode 202, and an end of electrostatic discharge protection component 111 links to each other with power track 101, and the other end links to each other with output pressure welding point 104.
Electrostatic discharge protection component 110 is made up of segment of double gated transistors 203, its emitting stage series resistance 205, collector series resistance 204, base resistance 207 and Zener diode 206, one end of electrostatic discharge protection component 110 links to each other with ground path 102, and the other end links to each other with input pressure welding point 103.Electrostatic discharge protection component 112 is made up of segment of double gated transistors 208, its emitting stage series resistance 210, collector series resistance 209, base resistance 212 and Zener diode 211, one end of electrostatic protection device 112 links to each other with ground path 102, and the other end links to each other with output pressure welding point 104.Electrostatic discharge protection component 113 is made up of segment of double gated transistors 213, its emitting stage series resistance 215, collector series resistance 214, base resistance 217 and Zener diode 216, one end of electrostatic discharge protection component 113 links to each other with power track 101, and the other end links to each other with ground path 102.One end of resistance 114 links to each other with input pressure welding point 103, and the other end links to each other with the grid of PMOS transistor 105 with nmos pass transistor 106.
In this electrostatic discharge protection structure, electrostatic discharge protection component 109 provides the static discharge path of input pressure welding point 103 to power track 101, electrostatic discharge protection component 110 provides the input pressure welding point the 103 static discharge paths to ground path 102, and electrostatic discharge protection component 109,110 and steady resistance 114 are realized the electrostatic discharge protective to the input buffer of being made up of PMOS transistor 105 and nmos pass transistor 106 together.Electrostatic discharge protection component 111 provides the static discharge path of output pressure welding point 104 to power track 101, electrostatic protection device 112 provides the output pressure welding point the 104 static discharge paths to ground path 102, the electrostatic discharge protective that electrostatic discharge protection component 111,113 is realized the output buffer of being made up of PMOS transistor 107 and nmos pass transistor 108.Electrostatic discharge protection component 113 provides the static discharge path of power track 101 to ground path 102, realizes the electrostatic discharge protective of power track 101 and 102 devices of ground path.
In the example that the present invention uses, the supply power voltage of power track 101 is 3.3V, and the forward conduction voltage of diode 201,202 is about 0.6V, and reverse breakdown voltage is about 9～10V, and the reverse breakdown voltage of Zener diode 206,211,216 is about 6.5～7V.Use this electrostatic discharge protection structure, the static discharge path of all patterns can be provided, because Zener diode has lower trigger voltage, can provide more effective static discahrge protection effect simultaneously.Appear at input pressure welding point 103 in positive electrostatic pulse, under the circumstances of ground path 102 ground connection, Zener diode 206 reverse breakdowns, the reverse current of Zener diode 206 produces pressure drop on the base resistance 207 of bipolar transistor 203, pressure drop is greater than the cut-in voltage (about 0.7V) of bipolar transistor 203 on base resistance 207, and static discharge current is conducted in bipolar transistor 203 conductings.Appear at input pressure welding point 103 in negative electrostatic pulse, under the situation of ground path 102 ground connection, the diode forward conducting of bipolar transistor 203 parasitisms, conduction static discharge current.Appear at input pressure welding point 103 in positive electrostatic pulse, under the situation of power track 101 ground connection, diode 201 forward conductions, conduction static discharge current.Appear at input pressure welding point 103 in negative electrostatic pulse, under the situation of power track 101 ground connection, Zener diode 216 reverse breakdowns, thereby make bipolar transistor 213 conductings, static discharge current is transmitted to ground path 102 from power track 101, arrives input pressure welding point 103 in diodes conduct via bipolar transistor 203 parasitisms.Appear at input pressure welding point 103 in positive electrostatic pulse, under the situation of another input pressure welding point 103 or output pressure welding point 104 ground connection, diode 201 forward conductions, static discharge current is transmitted on the power track 101 from input pressure welding point 103, reverse breakdown takes place in Zener diode 216 then, open bipolar transistor 213, static discharge current is transmitted to ground path 102 from 101, again via the diodes conduct of another bipolar transistor 203 or 208 parasitisms to another input pressure welding point 103 or output pressure welding point 104.Appear at input pressure welding point 103 for negative electrostatic pulse, the situation of another input pressure welding point 103 or output pressure welding point 104 ground connection, the static discharge path is identical.Also there are these identical six kinds of static discharge conduction paths for output pressure welding point 104.Appear on the power track 101 in positive electrostatic pulse, under the situation of ground path 102 ground connection, Zener diode 216 reverse breakdowns open bipolar transistor 213, the conduction static discharge current.Appear on the power track 101 in negative electrostatic pulse, under the situation of ground path 102 ground connection, the diode of bipolar transistor 213 parasitisms is opened, the conduction static discharge current.
Generalized section with Fig. 2 electrostatic discharge protection component 110 is an example, and the structure of the segment of double gated transistors that has Zener diode is described.Bipolar transistor pipe 203 is made up of N++ active area 304,305 and P-substrate 301 in the electrostatic discharge protection component 110.N++ active area 304 is collector electrodes of bipolar transistor, and N++ active area 305 is emitters of bipolar transistor, and P-substrate 301 is base stages of bipolar transistor.Below N++ active area 304,305, carry out the lightly doped N+ injection second time, formed N+ active area 306,307.The use secondary doping injects, and can increase the junction depth of bipolar transistor emitter and collector, has overcome the shallow problem of active area injection junction depth in the deep submicron process, thereby has improved the ability that the device unit are is born static discharge current.Below bipolar transistor pipe collector 304, carried out P type Zener and injected, formed P active area 308 than P-substrate 301 high-dopant concentrations.P active area 308 and N+ active area 306 have formed the Zener diode 206 in the electrostatic discharge protection component 110.The adding zener diode structure can effectively reduce the trigger point of electrostatic discharge protection component 110 presses, and improves static discahrge protection effect.Forming the technology that Zener diode injects, introduced illusory polysilicon grating structure 302, limited the position of P active area 308 by polysilicon gate 302, make it away from shallow-trench isolation 303 zones, thereby produce focus in shallow-trench isolation 303 edges of regions when avoiding the Zener diode reverse breakdown, the situation that causes bipolar transistor to damage.N++ active area 304,305 uses arsenic element to mix in the example that the present invention uses, and peak concentration is about 2e20/cm
-3, about 0.2 micron of its vertical degree of depth, N+ active area 306,307 uses P elements to mix, and peak concentration is about 2e19/cm
-3, about 0.4 micron of its vertical degree of depth, P active area 308 uses boron element to mix, and peak concentration is about 2e18/cm
-3, about 0.6 micron of its vertical degree of depth.
Because the collector electrode of bipolar transistor 203 links to each other with input pressure welding point 103, for avoiding collector electrode and substrate 301 short circuits of metal spike that static discharge current produced collector electrode metal contact 314 fusings with bipolar transistor 203, below collector electrode metal contact 314, N-trap 310 structures have been added.In the zone that the metal silicide deposition is not carried out in the emitter 305 and collector electrode 304 zones of bipolar transistor 203, form the emitter resistance 205 and the collector resistance 204 of bipolar transistor 203.Adding emitter resistance 205 and collector resistance 204 can improve the secondary breakdown voltage of bipolar transistor 203, make the secondary breakdown voltage of bipolar transistor 203 be higher than its puncture voltage, thereby have improved the even conduction of bipolar transistor 203.Contact the deposition 311,312 of having carried out metal silicide below 314 with collector electrode metal in bipolar transistor 203 emitter metal contact 315.Metal silicide 311,312 has reduced the heat of contact resistance and generation, avoids the big electric current of static discharge to cause Metal Contact 314 and 315 fusings or inefficacy.Equally, electrostatic discharge protection component 112,113 adopts identical device architecture.
Bring all and receive that the segmentation two-stage transistor single hop course of processing of diode is following (to be brought all and receive the segmentation two-stage transistor of diode according to the hop count of designing requirement, each section one-shot forming, because each section processing method is the same, in this processing with one section the course of processing is described):
(1) be to carry out oxidate on the base stage 301 at the P-substrate, form first shallow trench isolation region 303 and second shallow trench isolation region 317, the resistance of base stage 301 is base resistance;
(2) carry out the N type below second shallow trench isolation region 317 and inject, form N-trap 310, base stage 301 and N-trap 310 constitute parasitic diode;
(3) on first shallow trench isolation region 303, carry out oxidation, form gate oxide 318;
(4) on gate oxide 318, carry out polysilicon deposition, form polysilicon layer 302;
(5) carry out the silicon nitride deposition in polysilicon layer 302 both sides, form first and second silicon nitride side wall 319,320;
(6) carry out the injection of N type in the first silicon nitride side wall, 319 left sides and first shallow trench isolation region, 303 right sides, form first and second N++ active area 304,305, one section of constituting in the segmentation two-stage transistors of first and second N++ active area 304,305 and base stage 301, wherein a N++ active area 304 is a collector electrode, and the 2nd N++ active area 305 is an emitter;
(7) below first and second N++ active area 304,305, carry out the N type and inject, form first and second N+ district 306,307;
(8) carry out the P type below a N+ district 306 and inject, form P active area 308, the one N+ districts 306 and P district 308 formation Zener diodes, first and second N++ active area 304,305 is than the high order of magnitude of doping content in first and second N+ district 306,307;
(9) second shallow trench isolation regions 317 left sides are carried out the P type and are injected formation P+ active area 309;
(10) high annealing;
(11) carry out oxidate at a N++ active area 304 near on the first silicon nitride side wall, 319 parts, forming first blocking layer of metal silicide 321 is collector series resistance, carry out oxidate at the 2nd N++ active area 305 near on first shallow trench isolation region, 303 parts, forming second blocking layer of metal silicide 322 is the emitter series resistance;
(12) in P+ active area 309 enterprising row metal silicide depositions, form the 3rd metal silicide region 313, in a N++ active area 304 enterprising row metal silicide depositions, form first metal silicide region 311, in the 2nd N++ active area 305 enterprising row metal silicide depositions, form second metal silicide region 312;
(13) in first, second and third metal silicide region 311,312,313 enterprising row metals depositions, form collector electrode metal contact 314, emitter metal contact 315 and contact 316 with base metal, finish a section in the segmentation two-stage transistor.
Fig. 3 is the structure chart of segment of double gated transistors 203 in the electrostatic discharge protection component 110.Bipolar transistor 203 in the electrostatic discharge protection component 110 adopts the laying out pattern of segmentation.Bipolar transistor 203 has been divided into plurality of sections 401,402,403 etc. on layout design, use shallow-trench isolation 320 to isolate between each section.The hop count according to designing requirement of bipolar transistor 203, each section one-shot forming.The base stage of segment of double gated transistors under shallow trench isolation region 408 links to each other in domain structure.Segment of double gated transistors 203 is at least 3 sections, each segment base utmost point 301 links to each other, each section emitter 305 is 407 to link to each other among Fig. 3, each section collector electrode 304 be on 404 among Fig. 3,405,406 first blocking layer of metal silicide 318 by the 3rd shallow trench isolation region 323 isolate, first metal silicide region 311 links to each other.First shallow trench isolation region 303 is that the width of the shallow trench isolation areas (408 among Fig. 3) between collector electrode 304 and the emitter 305 is not less than 0.8 micron.The 3rd shallow trench isolation region 323 width are not less than 0.4 micron.
Use the domain structure of this segmentation, limit static discharging current lateral flow in bipolar transistor 203 avoids taking place the current concentration effect effectively, causes bipolar transistor 203 to cause inefficacy because of local current is excessive.Simultaneously, this laying out pattern can improve the even conduction of device effectively.For example, begin to conduct static discharge current when one section bipolar transistor 402 takes place to puncture, static discharge current can flow according to power line 409 directions.Like this, the electric current that is conducted by one section bipolar transistor 402 conducting can flow through two sections bipolar transistors 401 contiguous and 403 base stage, impels their to open, thereby conducts static discharge current together.
The domain of electrostatic discharge protection component 109 as shown in Figure 4 among the present invention.Wherein figure 501 is the anode injection zone of electrostatic discharge protection component 109, figure 502 is the negative electrode injection zone of electrostatic discharge protection component 109, figure 503 is the N-well area of electrostatic discharge protection component 109, and figure 504 is the substrate contact region territory of electrostatic discharge protection component 109.Each layer pattern all adopts 45 degree turnings in the domain, avoids causing component failure because of the turning effect in the static discharge process.
The domain example of electrostatic discharge protection component 110 as shown in Figure 5 among the present invention.Wherein figure 601 is the collector electrode injection zone of electrostatic discharge protection component 110, figure 602 is the emitter injection zone of electrostatic discharge protection component 110, figure 603 is the base stage contact area of electrostatic discharge protection component 110, figure 604 is the polysilicon region of electrostatic discharge protection component 110, and figure 605 is the Zener injection zone of electrostatic discharge protection component 110.Segment of double gated transistors 401,402,403 is near the collector electrode the 404,405, the 406th of emitter part in this example, separated by shallow trench isolation areas, then links to each other in the part near Metal Contact.The emitter 407 of segment of double gated transistors links to each other in domain structure.The base stage of segment of double gated transistors under shallow trench isolation region 408 links to each other in domain structure.In example of the present invention, the shallow trench isolation areas width between the active area 404,405,406 is 0.4 micron, and active area 404 (405,406) and the shallow trench isolation areas width between 407 are 0.8 micron.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (8)
1. electrostatic discharge protection structure in the integrated circuit, it is characterized in that: comprise the first kind electrostatic discharge protection component and the second class electrostatic discharge protection component, use at least one to be connected the first kind electrostatic discharge protection component of importing between pressure welding point and power track, at least one is connected input pressure welding point and the ground second class electrostatic discharge protection component and at least one steady resistance input buffer of protecting integrated circuit between path, use at least one be connected first kind electrostatic discharge protection component between output pressure welding point and power track and at least one be connected the output pressure welding point and the second class electrostatic discharge protection component between path protect the output buffer of integrated circuit; Use at least one to be connected power track and the ground second class electrostatic discharge protection component between path and protect device between power track and the ground path; wherein first kind electrostatic discharge protection component is a diode; the second class electrostatic discharge protection component is to bring all to receive the segmentation two-stage transistor of diode, brings all to receive segmentation two-stage transistor being made up of with Zener diode segmentation two-stage transistor, emitter series resistance, collector series resistance, base resistance of diode.
2. electrostatic discharge protection structure in a kind of integrated circuit according to claim 1 is characterized in that: described bringing all received the segmentation two-stage transistor course of processing of diode and realized by following steps,
The first step is to carry out oxidate on the base stage (301) at the P-substrate, forms first shallow trench isolation region (303) and second shallow trench isolation region (317), and the resistance of base stage (301) is base resistance;
Second step, carry out the N type in second shallow trench isolation region (317) below and inject, form N-trap (310), base stage (301) and N-trap (310) constitute parasitic diode;
The 3rd step, on first shallow trench isolation region (303), carry out oxidation, form gate oxide (318);
The 4th step, on gate oxide (318), carry out polysilicon deposition, form polysilicon layer (302);
The 5th step, carry out the silicon nitride deposition in polysilicon layer (302) both sides, form first and second silicon nitride side wall (319,320);
The 6th step, carry out the injection of N type in the first silicon nitride side wall (319) left side and first shallow trench isolation region (303) right side, form first and second N++ active area (304,305), first and second N++ active area (304,305) and base stage (301) constitute a section in the segmentation two-stage transistor, wherein a N++ active area (304) is a collector electrode, and the 2nd N++ active area (305) is an emitter;
The 7th step, carry out the N type in first and second N++ active area (304,305) below and inject, form first and second N+ district (306,307);
The 8th step, carry out the P type in below, a N+ district (306) and inject, form P active area (308), a N+ district (306) and P active area (308) constitute Zener diode;
The 9th step, carry out the P type in second shallow trench isolation region (317) left side and inject, form the P+ active area
(309)；
The tenth step, high annealing;
The 11 step, on the close first silicon nitride side wall (319) part of a N++ active area (304), carry out oxidate, forming first blocking layer of metal silicide (321) is collector series resistance, carry out oxidate on close first shallow trench isolation region (303) part of the 2nd N++ active area (305), forming second blocking layer of metal silicide (322) is the emitter series resistance;
The 12 step, in the enterprising row metal silicide deposition of P+ active area (309), form the 3rd metal silicide region (313), in the enterprising row metal silicide deposition of a N++ active area (304), form first metal silicide region (311), in the enterprising row metal silicide deposition of the 2nd N++ active area (305), form second metal silicide region (312);
The 13 step, in the enterprising row metal deposition of first, second and third metal silicide region (311,312,313), formation collector electrode metal contact (314), emitter metal contact (315) contact (316) with base metal, finish a section in the segmentation two-stage transistor;
The 14 step, repeated for first～the 13 step, obtain each section in the segmentation two-stage transistor simultaneously, transistorized each the segment base utmost point (301) of segmentation twin-stage links to each other, each section emitter (305) links to each other, and first blocking layer of metal silicide (318) on each section collector electrode (304) links to each other by the 3rd shallow trench isolation region (323) isolation, first metal silicide region (311).
3. electrostatic discharge protection structure in a kind of integrated circuit according to claim 2 is characterized in that: first shallow trench isolation region (303) is that the width of the shallow trench isolation areas between collector electrode (304) and the emitter (305) is not less than 0.8 micron in the described first step.
4. electrostatic discharge protection structure in a kind of integrated circuit according to claim 2 is characterized in that: the 3rd shallow trench isolation region (323) width is not less than 0.4 micron in described the 14 step.
5. electrostatic discharge protection structure in a kind of integrated circuit according to claim 2 is characterized in that: first and second N++ active area (304,305) that described the 6th step forms is than the high order of magnitude of doping content in first and second N+ district (306,307) of described the 7th step formation.
6. electrostatic discharge protection structure in a kind of integrated circuit according to claim 2 is characterized in that: described bringing all received the segmentation two-stage transistor of diode and is at least 3 sections.
7. electrostatic discharge protection structure in a kind of integrated circuit according to claim 1, it is characterized in that: described diode comprises anode injection zone, negative electrode injection zone, N-well area and substrate contact region territory, and each area level figure all adopts 45 degree turnings in domain.
8. electrostatic discharge protection structure in a kind of integrated circuit according to claim 2, it is characterized in that: first and second N++ active area (304,305) that described the 6th step forms uses arsenic element to mix, first and second N+ district (306,307) that described the 7th step forms uses P elements to mix, and the P active area (308) that described the 8th step forms uses boron element to mix.
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| CN103050442A (en) * | 2012-12-20 | 2013-04-17 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN104253410A (en) * | 2014-09-11 | 2014-12-31 | 北京大学 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
| CN105932022A (en) * | 2015-02-27 | 2016-09-07 | 万国半导体股份有限公司 | Field effect transistor with integrated zener diode |
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| CN103050442A (en) * | 2012-12-20 | 2013-04-17 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN103050442B (en) * | 2012-12-20 | 2015-01-07 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN104157645B (en) * | 2012-12-20 | 2017-02-22 | 杭州士兰微电子股份有限公司 | Power semiconductor device with electro-static discharging capability and manufacturing method |
| CN104253410A (en) * | 2014-09-11 | 2014-12-31 | 北京大学 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
| CN105932022A (en) * | 2015-02-27 | 2016-09-07 | 万国半导体股份有限公司 | Field effect transistor with integrated zener diode |
| CN105932022B (en) * | 2015-02-27 | 2019-02-05 | 万国半导体股份有限公司 | The field effect transistor of integrated Zener diode |
| CN106033722A (en) * | 2015-03-10 | 2016-10-19 | 无锡华润上华半导体有限公司 | Zener diode manufacturing method based on CMOS manufacturing process |
| CN106033722B (en) * | 2015-03-10 | 2020-02-18 | 无锡华润上华科技有限公司 | Manufacturing method of Zener tube based on CMOS manufacturing process |
| CN108346652A (en) * | 2017-01-22 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of electrostatic discharge protection component |
| CN110534503A (en) * | 2019-08-23 | 2019-12-03 | 无锡华润矽科微电子有限公司 | IC chip and integrated circuit |
| CN113471193A (en) * | 2021-06-28 | 2021-10-01 | 深圳砺芯半导体有限责任公司 | Anti-latch-up composite device for positive and negative power supply ESD protection |
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