CN101937384A

CN101937384A - DSP (Digital Signal Processor) failure detection method

Info

Publication number: CN101937384A
Application number: CN 201010500822
Authority: CN
Inventors: 但春华
Original assignee: STATE HONGFENG MACHINERY FACTORY
Current assignee: STATE HONGFENG MACHINERY FACTORY
Priority date: 2010-10-09
Filing date: 2010-10-09
Publication date: 2011-01-05

Abstract

The invention relates to a DSP (Digital Signal Processor) failure detection method which is characterized in that a monitoring device connected with a DSP is installed and used for monitoring periodic pulse signals output from a GPIO (General Purpose Input Output) port of the DSP; a monitoring part is internally provided with a delay counter; when the periodic pulse signals output from the GPIO port are normally output, the delay counter is continuously reset; when the GPIO port can not output the periodic pulse signals, the delay counter overflows; and the monitoring device sends an output failure detection signal so as to confirm that the DSP is failed. The failure detection method can timely and effectively detect the failure of the DSP.

Description

The DSP fault detection method

Technical field

The present invention is a kind of DSP fault detection method, belongs to electronic technology field.

Background technology

Digital signal processor (DSP) is from being born development so far, though only experienced the time in 30 years, the widespread use in fields such as communication, computing machine and consumer electronics products, profound influence people's life.DSP is that the discrete numeral of a kind of usefulness is represented signal, and the technology of these discrete serieses effectively being handled with digital hardware, it utilizes computing machine or dedicated treatment facility, with digital form to signal gather, processing such as conversion, filtering, valuation, enhancing, compression and identification, obtain meeting the signal form of demand.But be suitable for the DSP fault detection method owing to lack, and can't in time find after causing DSP to damage, cause bigger infringement, can directly influence the continuity of related work again.

Summary of the invention

Technical matters to be solved by this invention provide a kind of can be in time, easily detect the detection method that hardware and software failure takes place DSP.

For solving the problems of the technologies described above, the technical scheme that the present invention takes is:

A kind of DSP fault detection method, it is characterized in that, a supervising device that is connected with DSP is installed, and monitoring is provided with a delay counter by the cyclic pulse signal of the GPIO mouth output of DSP in the monitor component, when the cyclic pulse signal of GPIO mouth output is normally exported, delay counter constantly resets, and when the GPIO mouth can not be exported cyclic pulse signal, delay counter overflowed, supervising device sends the output fault detection signal, just can assert that fault has taken place DSP.

Described supervising device is a monitoring chip.

Described monitoring chip is that monitoring chip is the microprocessor monitors chip.Advantage is need not programme, and realizes simple; Shortcoming is that timing is fixed, and is non-programmable.

Described microprocessor monitors chip is DS1832.The pulse input pin (ST) of DSP general digital quantity input and output (GPIO) mouthful control microprocessor monitoring chip DS1832.When the DSP software and hardware just often, the cyclic pulse signal of the GPIO mouth output DS1832 timer internal that constantly resets, DS1832 reseting pin (RST) keeps disarmed state (being low level state); When the DSP hardware and software failure, the GPIO mouth can not be exported cyclic pulse signal, and DS1832 reseting pin (RST) is exported one low level after delaying time.

Described supervising device is a programmable logic device (PLD).In inside counter is set, delay time can be provided with by frequency division and pulse data, outside input pin (linking to each other with the general input/output port of DSP) reset counter when the level saltus step when the DSP fault and behind delay time, is exported to external detection equipment by another IO mouth.

The invention has the beneficial effects as follows the fault that can detect DSP timely and effectively.

Description of drawings

Below in conjunction with the drawings and specific embodiments technical scheme of the present invention is further described in detail.

Accompanying drawing 1 is DSP fault detect theory diagram of the present invention.

Accompanying drawing 2 is realized DS1832 and the DSP catenation principle figure of embodiment for the present invention.

The explanation of accompanying drawing DS1832 pin:

1 pin (PBR)-----------hand-reset end;

2 pin (TD)--------select, and ground connection typical case delay time is 150ms, and unsettled typical delay time is 600ms, and connecing VCC typical case delay time is 1.2s by-----delay time;

3 pin (TOL)-----------detecting the supply voltage accuracy rating to select, the earthing power supply reference voltage detection is 10%, connecing VCC supply voltage sensing range is 20%;

4 pin (GND)-----------power supply ground;

5 pin (RST)------------output (high level is effective) that resets;

6 pin (RST)------------output (low level is effective) that resets;

--------------pulse input end links to each other with the general input/output port of DSP 7 pin (ST);

8 pin (VCC)-----------power positive end.

Embodiment

As shown in Figure 2, utilize the pulse input pin (ST) of DSP general digital quantity input and output (GPIO) mouthful control microprocessor monitoring chip DS1832.As Fig. 1, when the DSP software and hardware just often, GPIO mouth output cyclic pulse signal (cycle is not more than 300ms), then the DS1832 timer internal constantly resets, DS1832 reseting pin (RST) keeps disarmed state (being low level state), shows that the DSP function is normal; When the DSP hardware and software failure, the GPIO mouth can not be exported cyclic pulse signal, and the low level that pulsewidth of DS1832 reseting pin (RST) output is 250ms after the 150ms time-delay is the output fault detection signal, shows that fault has taken place DSP.

It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims

1. DSP fault detection method, it is characterized in that, a supervising device that is connected with DSP is installed, and monitoring is provided with a delay counter by the cyclic pulse signal of the GPIO mouth output of DSP in the monitor component, when the cyclic pulse signal of GPIO mouth output is normally exported, delay counter constantly resets, and when the GPIO mouth can not be exported cyclic pulse signal, delay counter overflowed, supervising device sends the output fault detection signal, just can assert that fault has taken place DSP.

2. DSP fault detection method according to claim 1 is characterized in that, described supervising device is a monitoring chip.

3. according to the described DSP fault detection method of claim 2, it is characterized in that described monitoring chip is the microprocessor monitors chip.

4. DSP fault detection method according to claim 3 is characterized in that, described microprocessor monitors chip is DS1832.

5. DSP fault detection method according to claim 1 is characterized in that, described supervising device is a programmable logic device (PLD).