CN101936234A - Control unit for controlling IP (Intellectual Property) core by integrating multiple engines - Google Patents
Control unit for controlling IP (Intellectual Property) core by integrating multiple engines Download PDFInfo
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Abstract
The invention discloses a control unit for controlling an IP core by integrating multiple engines, adopting an FPGA (Field Programmable Gate Array) and comprising a processor, a bus, a DCM (Digital Clock Manager), an output clock signal, an EPA (Engine Position Acquisition) module, an IPC module (Injection Process Control), an ADC (Analog-to-Digital Conversion) module and an interrupt controller, wherein the EPA module is used for outputting phase signals for representing the current positions of engines and engine rotation speed signals according to input crank signals and camshaft signals; the IPC module is used for outputting engine oil injection pulse control signals according to the input phase signals of the current positions of the engines; the ADC module is used for controlling an external analog-to-digital conversion chip to carry out the analog-to-digital conversion on the signals; the EPA module, the IPC module and the ADC module respectively support an interrupt work mode; the interrupt controller manages all interrupt signals and outputs the interrupt signals of the processor; and the processor, the DCM, the EPA module, the IPC module, the ADC module and the interrupt controller are respectively mounted to the bus in manner of the IP core. The invention utilizes FPGA hardware, thereby greatly increasing the computation speed.
Description
Technical field
The present invention relates to a kind of Electronic Fuel Injection (EFI) (electronic fuel injection of motor, EFI) system, for example be used for peculiar to vessel or vehicular engine, particularly relate to electronic control unit in a kind of electronic fuel injection system of motor (electroni c control unit, ECU).
Background technique
The EFI system of motor can be divided into three subtense angles, is respectively: fuel oil transmit subsystem (fuel delivery system), induction subsystem (air induction system) and electronic control subtense angle (electronic control system).Wherein, the electronic control subtense angle comprises ECU, various sensor, fuel injector assembly (fuel injector assembly) etc.
At present, the ECU in the motor EFI system generally selects single-chip microcomputer (microcontroller, microcontroller) for use.Along with the engine control required precision improve day by day and the control function complicated day by day, the calculation process ability of single-chip microcomputer has been difficult to the competent requirement of handling bulk information.During for example to the in-cylinder combustion process control, must be in the engine combustion process utmost point short time (microsecond level) gather and processing relevant information and pursue cylinder and control.
Simultaneously, (application specific integrated circuit, single-chip microcomputer ASIC) also has " congenital " deficiency as ASIC.For example the life cycle of the life cycle of single-chip microcomputer and motor is inconsistent, may cause single-chip microcomputer stopping production back to be made troubles to engine maintenance; When the small lot batch manufacture of electronic control subtense angle, this contradiction is particularly outstanding.
Summary of the invention
Technical problem to be solved by this invention provides a kind of ECU of electronic control subtense angle of motor, not only has arithmetic speed faster, and is convenient to maintain and replace.
For solving the problems of the technologies described above, the control unit of the integrated multiple engine control IP kernel of the present invention adopt field programmable gate array (field programmable gate array FPGA), comprising:
-processor;
-bus;
-digital dock manager (digital clock manager, DCM), clock signal;
-engine location obtains that (according to the crankshaft signal and the camshaft signal of input, output characterizes the phase signal and the engine rotational speed signal of motor current location for engine position acquisition, EPA) module;
The control of-course of injection (injection process control, IPC) module, according to the phase signal of the sign motor current location of importing, output motor fuel injection pulse control signal;
The control of-analog-to-digital conversion (analog to digital control, ADC) module is controlled the analog-to-digital conversion that outside modulus conversion chip carries out signal;
Described engine location acquisition module, course of injection control module, analog-to-digital conversion control module are all supported the interruption of work mode;
-interrupt control unit to all interrupt signal management, is realized the output to the processor interrupt signal.
Described processor, digital dock manager, engine location acquisition module, course of injection control module, analog-to-digital conversion control module, interrupt control unit are all with IP core (intellectual property core, IP core, IP kernel) form is articulated to described bus.
The ECU of motor of the present invention can utilize the hardware computation capability of FPGA, thereby improves the computational speed of ECU greatly.The ECU of motor of the present invention also is separated each function module, and each function module is cured as FPGA hardware (IP kernel), provide application with chip degree, thereby make whole system present modularization and stratification, reduced the complexity that software is realized, the stability that helps the elevator system operation helps accelerating exploitation debugging and maintenance maintenance speed.
Description of drawings
Fig. 1 is the system block diagram one of the ECU of motor of the present invention;
Fig. 2 is the system block diagram two of the ECU of motor of the present invention;
Fig. 3 is the input output schematic representation of EPA module among the ECU of motor of the present invention;
Fig. 4 is the input output schematic representation of IPC module among the ECU of motor of the present invention;
Fig. 5 is the input output schematic representation of ADC module among the ECU of motor of the present invention;
Fig. 6 is the schematic representation of DAC module among the ECU of motor of the present invention;
Fig. 7 is the schematic representation of watchdog module among the ECU of motor of the present invention;
Fig. 8 is the schematic representation of contact and toggle switch IP kernel among the ECU of motor of the present invention;
Fig. 9 is the schematic representation of the ECU high speed on-off controller IP kernel of motor of the present invention;
Figure 10 is the schematic representation of the ECU high speed on-off controller IP kernel of motor of the present invention with 4 tunnel array outputs;
Figure 11 is the schematic representation of the ECU repeat circuit contact output IP kernel of motor of the present invention.
Embodiment
See also Fig. 1, the ECU of motor of the present invention comprises:
-processor;
-bus;
-DCM is to each IP kernel clock signal;
-EPA module, according to the crankshaft signal and the camshaft signal of input, output characterizes the phase signal and the engine speed information of motor current location;
-IPC module, according to the phase signal of the sign motor current location of importing, output motor fuel injection pulse control signal;
-ADC module is controlled outside AD (analog-to-digital conversion) chip by different drainage patterns, is digital signal output with the analog signal conversion of importing; Described drainage pattern comprises: press motor angle synchronous mode, press time synchronous mode and software triggering synchronous pattern;
Described EPA module, IPC module, ADC module are all supported the interruption of work mode;
-interrupt control unit is managed the interrupt signal that all IP kernels produce, and according to different priority, sends interrupt signal to processor.
Described processor, DCM, EPA module, IPC module, ADC module, interrupt control unit all are articulated to described bus with the form of IP kernel.
Each module among Fig. 1 has constituted the fundamental system of the ECU of motor of the present invention.Wherein processor carries out calculation process, and DCM provides all relevant CLK clock for each IP kernel.The EPA module is obtained the testing result of correct phase signal, tach signal and the corresponding speed probe of motor, and it offers ADC module and IPC module with the information of correspondence.The ADC module can be carried out the collection of external analog amount data by phase lock, software triggering synchronous or timing triggering synchronous pattern, and transfers to outside AD chip and carry out returning this ECU system after the analog-to-digital conversion.The IPC module is according to application layer (i.e. software on this ECU hardware system) requirement, reads the phase signal of EPA module output, realize the sending of injection timing signal of respective cylinder, thereby the control external drive circuit realized the injection control of oil sprayer.
On this basis, the ECU of motor of the present invention can also increase some add-on modules, sees also Fig. 2.Also comprise digital-to-analog conversion control (DAC among Fig. 2, digital to analog control) module, speed-sensitive switch controller, serial peripheral interface (serial peripheral interface, SPI) modules such as module, SRAM controller, watchdog module, relay contact output module, contact and toggle switch, these newly-increased modules also are that the form with IP kernel is connected to the bus among this ECU system.In Fig. 2, the collaborative work relation between processor, DCM, EPA module, ADC module, the IPC module is introduced unanimity with Fig. 1, is used for finishing basic Electronic Fuel Injection (EFI) control.Other each modules are separate, can increase newly one or morely, are respectively applied for and realize different expanded functions.The DA conversion chip of DAC module controls periphery is realized digital-to-analog conversion.The speed-sensitive switch controller produces complicated PWM (pulsewidth modulation) waveform, external object such as control motor, solenoid valve.The SPI module is standard I P nuclear, realizes the SPI interface chip is controlled.The SRAM controller is realized the control to sram chip for standard I P nuclear.Watchdog module, realize to controller reset, the watchdog function of program detection etc.The relay contact output module, control relay adhesive, disconnection.Contact and toggle switch module realize reading of switch amount signal.
The ECU of Fig. 1 or motor of the present invention shown in Figure 2 is hardware.Can operating software on hardware foundation, described software is comprised to high level by bottom: driver (device driver), operation system, user application software etc.These softwares are also by the unified application layer that is called.
ECU in traditional motor EFI system adopts single-chip microcomputer, and this single-chip microcomputer is handled input, output, the calculating of each function module with software mode.ECU of the present invention adopts FPGA, and each function module of ECU all is cured as the IP kernel one by one of FPGA.In order to guarantee real-time, all IP kernels are all supported the interruption of work mode.Obviously the present invention has significantly promoted the arithmetic speed of ECU.
The hardware of ECU of the present invention constitutes the flat framework that adopts based on bus interconnection, and promptly processor and all IP kernels all are connected to on the one-level high-speed bus (for example PLB bus), so that improve Whole Response speed.All IP issued transaction all adopt interrupt mode, handle in conjunction with the priority ruling of interrupt control unit, compare traditional inquiry mode and have improved treatment effeciency.In addition, utilize the FPGA of FPGA can dispose direct communication interface between each IP kernel easily, make some processing can not rely on processor and carry out automatically that this has further alleviated the processor active task of processor.These improvement make processor can finish some the computing intensive task outside data capture and the control processing.
FPGA with xilinx company is an example, among the ECU of the present invention, processor can adopt MicroBlaze soft-core processor (sofe-core processor), bus can adopt the PLB bus, DCM can adopt the standard I P nuclear of the DCM in xinlinx EDK (Embedded Development Kit, the embedded development external member) development kit.
The function of DCM module is for whole system provides required clock output, avoids independently carrying out the phase deviation and the wasting of resources that clock division brings by each IP kernel.For example can directly adopt the IP kernel of the existing DCM that FPGA manufacturer provides in EDK, usually the DCM module that provides of manufacturer can provide clock synchronously, phase shift, frequency division, frequency multiplication and go function such as shake.
The function of interrupt control unit is the interrupt signal (interrupt requests) of each IP kernel of rational management, and according to the limited processor calculating resource of priority.For example can directly adopt the IP kernel of the existing interrupt control unit that FPGA manufacturer provides in EDK.
The EPA module realizes obtaining of motor current location, sees also Fig. 3, and it carries out being converted into phase signal and engine rotational speed signal and the output that characterizes the motor current location after the fault-tolerant processing according to crankshaft signal, camshaft signal and the CLK clock of input.The phase signal of the sign motor current location of EPA module output comprises: crankshaft signal, high-resolution little tooth signal after first cylinder compression top center signal, each cylinder compression top center signal, the processing.The engine rotational speed signal of EPA module output comprises: current ejection cylinder, each between cog cycle of bent axle, each between cog cycle of camshaft, trouble signal, interrupt signal.
The IPC module characterizes the phase signal of motor current location as input signal with the part of EPA module output, in conjunction with the data information in register and BRAM (ram in slice) space, calculate and the output sign motor fuel injection pulse moment, length and the motor fuel injection pulse control signal in cycle.See also Fig. 4, the input signal of IPC module comprises two-part.First portion is the phase signal that characterizes the motor current location, comprising: crankshaft signal, high-resolution little tooth signal, injection timing pattern, injection timing signal buffer area after first cylinder compression top center signal, each cylinder compression top center signal, the processing.Second portion is detection information and the scalar quantity information that processor calculates according to user application, these data storage are in the register and BRAM space of IPC module, and these information comprise: high pressure switching time, high pressure gating truth table, current ejection cylinder, cylinder gating truth table, copped wave switching time, chopping voltage threshold value.The motor fuel injection pulse control signal of IPC module output will be converted into corresponding hardware output configuration signal and gating siganl, drive and control the response of related hardware.The motor fuel injection pulse control signal of IPC module output comprises: high pressure gating siganl, cylinder gating siganl, chopping voltage comparison value.
In control normal injection process, the IPC module can also be carried out experiment of solenoid valve rattling and fault diagnosis according to program setting, and the result of detection solenoid valve is by specific register record and generate corresponding interrupt signal in order to carry out alternately with upper level applications.The extra input signal that increases of IPC module this moment comprises: click test enable signal, click test pulse width signal, click test pulse width interval signal, solenoid valve diagnosis information, solenoid valve detect feedback signal.The extra output signal that increases of IPC module this moment comprises: solenoid valve failure interrupt signal, solenoid valve diagnosis consequential signal.
The ADC module realizes the control to outside AD conversion chip, is mainly used in pressure signal, and analog amounts such as temperature signal are gathered, and will gather signal and transfer to outside AD chip and carry out sending to application layer after the analog-to-digital conversion.See also Fig. 5, the input signal of ADC module comprises: from the first cylinder compression top center signal of EPA module, the crankshaft signal after the processing; Serial data from outside AD (analog-to-digital conversion) chip; With Working mode set from application layer.The output signal of ADC module comprises: interrupt signal, sampling overload error interrupt signal are finished in sample numerical value, the sampling of exporting to application layer; Export to the chip selection signal and the CLK clock of outside AD chip.The ADC module is carried out the data capture of different synchronous modes according to the requirement of application layer to outside AD chip, and carries out corresponding signal filtering.Described synchronous mode comprises: software trigger mode, timing acquiring pattern, angle synchronous mode, determine by described " Working mode set " signal.
Except that above EPA module, IPC module and ADC module, IP kernels such as the house dog that relates among the ECU of the present invention, speed-sensitive switch controller, DAC module, relay contact output, contact and toggle switch all are the differences according to the external control chip, develop different IP kernels, if corresponding standard I P nuclear is arranged in the EDK, also can directly adopt.These IP kernels are all comparatively simple, below do simple the introduction.
The DAC module functions is control peripheral DA (digital-to-analog conversion) chip, realizes digital-to-analog conversion, output current or voltage analog signal.See also Fig. 6, the DAC module comprises DA control output module and control corresponding register.Signal on the PLB deposits among the control register DACR after changing through the PLB Interface Module.Value in the control register comprises that the output enable of DA, DA output channel are selected, the output data of DA.DA control output module reads the value in the control register, produces the signal that two-way meets outside DA chip sequential, exports peripheral circuit to.
The input signal of DAC module comprises:
-data transfer buffer area: define a data register, the passage that record will be changed, transforming numerical, transition enabled.
-transition enabled: application layer starts corresponding A D chip and carries out data transfer by sending the transition enabled order to IP kernel.
Above signal is kept in the DA register by application layer.
The output signal of DAC module comprises:
-DA_SYNC synchronizing signal: the work of DA chip enables and synchronizing signal.
-DA_SCLK CLK clock: DA chip and IP kernel communication CLK clock.
-DA_DIN data-signal: the DA chip is accepted the communication serial data from IP kernel.
The major function of watchdog module is to accept the reset signal of peripheral monitoring chip, and whole ECU system is resetted.See also Fig. 7, watchdog module comprises it being pulse generation module, Proc_sys_reset module and corresponding registers (control register, status register).
The input signal of watchdog module comprises:
-clear WDT signal: this signal is from application layer, the feeding-dog signal that provides in house dog limits constantly.
-WDT enable signal:, whether enable the timing watchdog reset function of WDT from application layer.
More than two signals all be kept in the control register.
-WDT_Rst reset signal:, be reseting request signal from the outer monitoring chip.
The output signal of watchdog module comprises:
-WDT_Impluse feeding-dog signal: after watchdog module received clearly the WDT signal, this IP kernel sent the efficient clock edge.
-WDT_Ctrl enable signal: according to default, IP kernel sends corresponding level signal, enables or close the watch dog monitoring function of outer monitoring chip.
-systematic reset signal: by the corresponding reset signal that the proc_sys_reset module is sent, comprise that nuclear (processor) resets, bus reset, peripheral hardware (being each IP kernel) reset etc., this signal is kept in the status register.The state of watchdog module by this register corresponding positions carries out corresponding resetting or homing action not to nuclear, bus, peripheral hardware.
Contact and toggle switch module functions are the collections to switching values such as contact switch, toggle switch.See also Fig. 8, contact and toggle switch module comprise frequency division module, code interception module and corresponding registers (control register, status register).
The input signal of contact and toggle switch module comprises:
-peripheral chip enable signal: whether application layer control peripheral chip works, and promptly control strip selects the CS pin.Mode bit of definition in the IP kernel, application layer be by this position of configuration, represents whether gating of control chip CS.This signal is kept in the control register.
-Reg_SO[23:0]: SPI communication pin, serial data output interface.
-Switch_INT:MC33993 exports interrupt signal.
The output signal of contact and toggle switch module comprises:
-contact and toggle switch state buffer: this IP kernel is saved in the information that receives in the status register, writes down the state of each contact, road and toggle switch.
-change of state position: when sending " change of state interrupt signal ",, write down any way switch amount of current variation by defining one 5 bit register.
Above signal is kept in the status register, makes things convenient for application layer to read.
-Switch_Ctrl: chip selection signal.
-Switch_SI[23:0]: SPI communication pin, data input signal.
-Switch_Clk:SPI communication is pin all the time.
The major function of speed-sensitive switch controller is to allow FPGA send PWM (pulsewidth modulation) signal, then by parts work such as external power driving device drives motor, oil pump, solenoid valves.See also Fig. 9, the speed-sensitive switch controller comprises speed-sensitive switch register and PWM control output module.Signal on the PLB bus deposits in the speed-sensitive switch register via the PLB interface.PWM control output module produces the output of 4 road PWM speed-sensitive switch signals according to the value in the speed-sensitive switch register.
This speed-sensitive switch controller IP kernel can be operated under two kinds of patterns: single channel control mode and four tunnel array output patterns; And can export two kinds of different waveforms.
The input signal of speed-sensitive switch controller comprises:
-pwm signal output channel is selected: according to mode of operation, IP controls the work of arbitrary passage, and each channel start is closed mutual independence.The output on each road starts closing control and is provided with in PWM square wave output control register.
-PWM module mode of operation: this signal is set by upper layer software (applications).Upper layer software (applications) can be set the output waveform of each road PWM passage in mode of operation, the startup of each passage, close mode, phase difference etc.
More than two kinds of signals set by application layer and be kept in the speed-sensitive switch register.
The output signal of speed-sensitive switch controller comprises:
-PWM_out1: according to Working mode set, the output respective waveforms, each passage is independent mutually.When the signal at stop of this road, output level is a low level.
-PWM_out2: according to Working mode set, the output respective waveforms, each passage is independent mutually.When the signal at stop of this road, output level is a low level.
-PWM_out3: according to Working mode set, the output respective waveforms, each passage is independent mutually.When the signal at stop of this road, output level is a low level.
-PWM_out4: according to Working mode set, the output respective waveforms, each passage is independent mutually.When the signal at stop of this road, output level is a low level.
The mode of operation definition of speed-sensitive switch controller:
-single channel control mode: under this pattern, the startup of each output channel, close by upper layer software (applications) and control separately, each paths is independent mutually.The output waveform of each passage is set respectively in mode of operation.
-multichannel array output control mode: under this pattern, software control multichannel road PWM passage starts simultaneously and closes simultaneously.Requirement is provided with the output waveform of each passage in mode of operation, and the relative phase difference of each passage.
See also Figure 10, this is to be the schematic representation that example describes multichannel array output control mode with 4 the tunnel.When 4 tunnel array outputs, it is poor just to have respective phase between each road, and a1, a2, a3 represent the phase difference between the the 2 tunnel, the 3 tunnel, the 4 tunnel output signal and the 1 tunnel output signal respectively
The major function of relay contact output module is the control to relay adhesive or disconnection.See also Figure 11, the relay contact output module comprises frequency division module, data processing module and corresponding registers (control register, status register).
The input signal of relay contact output module comprises:
-output enable: application layer sends order to IP kernel, in corresponding register-bit set, informs that IP kernel has the correspondence of carrying out road relay to carry out adhesive and disconnection.
-data output buffer district: define a register, write, carry out which kind of action to certain road relay by application layer.
More than two kinds of signals all be kept in the control register by application layer.
The output signal of relay contact output IP kernel comprises:
-RE_SClk: external control clock signal chip.
-RE_DIN[7:0]: the data of exporting to external chip;
-RE_STB: signal synchronization.
In sum, the ECU of motor of the present invention has broken away from traditional single-chip microcomputer and complicated software thereof, then the FPGA of employing IP kernel framework, by each function module independently being formed the IP kernel of hardware, not only improved computational speed greatly, alleviated the burden of processor among the FPGA, and be convenient to maintenance and management, helped this ECU is further debugged.
The structure of above each IP kernel that provides, input output etc. are exemplary in nature, and on thought disclosed in this invention basis, one of ordinary skill in the art can be made and be equal to replacement, and these all should belong within protection scope of the present invention.
Claims (2)
1. the control unit of an integrated multiple engine control IP kernel is characterized in that, adopts field programmable gate array, comprising:
-processor;
-bus;
-digital dock manager, clock signal;
-engine location acquisition module, according to the crankshaft signal and the camshaft signal of input, output characterizes the phase signal and the engine rotational speed signal of motor current location;
-course of injection control module, according to the phase signal of the sign motor current location of importing, output motor fuel injection pulse control signal;
-analog-to-digital conversion control module is controlled the analog-to-digital conversion that outside modulus conversion chip carries out signal;
Described engine location acquisition module, course of injection control module, analog-to-digital conversion control module are all supported the interruption of work mode;
-interrupt control unit to all interrupt signal management, is realized the output to the processor interrupt signal.
Described processor, digital dock manager, engine location acquisition module, course of injection control module, analog-to-digital conversion control module, interrupt control unit all are articulated to described bus with the form of IP core.
2. the control unit of integrated multiple engine control IP kernel according to claim 1 is characterized in that, also comprises one or more as in the lower module:
-digital-to-analog conversion control module is controlled the digital-to-analog conversion that outside analog-digital chip is realized signal;
-speed-sensitive switch controller produces pulse-width signal control external object;
-serial peripheral interface module is controlled the serial peripheral interface chip of outside;
-SRAM controller is controlled the sram chip of outside;
-watchdog module is realized described electronic control unit is resetted, detects;
-relay contact output module is controlled outside relay adhesive, disconnection;
-contact and toggle switch module realize reading of switch amount signal;
Described digital-to-analog conversion control module, speed-sensitive switch controller, serial peripheral interface module, SRAM controller, watchdog module, relay contact output module, contact and toggle switch module all are connected in the described electronic control unit with the form of IP core.
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| CN2010102336447A CN101936234A (en) | 2010-07-22 | 2010-07-22 | Control unit for controlling IP (Intellectual Property) core by integrating multiple engines |
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| CN104797802A (en) * | 2012-11-26 | 2015-07-22 | 日立汽车***株式会社 | Control device |
| CN109213027A (en) * | 2018-07-16 | 2019-01-15 | 哈尔滨工程大学 | One kind being based on the marine low-speed common rail diesel engine speed adjustment unit of μ/COS-II real time operating system |
| CN112887438A (en) * | 2021-04-29 | 2021-06-01 | 深圳市永联科技股份有限公司 | Energy controller, system image file downloading method and file downloading system |
| CN114281751A (en) * | 2020-09-28 | 2022-04-05 | 上海商汤智能科技有限公司 | Chip system |
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| CN112887438A (en) * | 2021-04-29 | 2021-06-01 | 深圳市永联科技股份有限公司 | Energy controller, system image file downloading method and file downloading system |
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Application publication date: 20110105 |