CN101930922B

CN101930922B - Production method of MOS (Metal Oxide Semiconductor) transistor

Info

Publication number: CN101930922B
Application number: CN200910054094XA
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2009-06-26
Filing date: 2009-06-26
Publication date: 2011-12-07
Anticipated expiration: 2029-06-26
Also published as: CN101930922A

Abstract

The invention relates to a production method of an MOS (Metal Oxide Semiconductor) transistor, which comprises the following steps of: carrying out etching on a first medium layer and a polysilicon layer for the first time to form an auxiliary hard mask layer; oxidizing the polysilicon layer in the auxiliary hard mask layer to form a first oxide layer; injecting for the first time to form high doping source/drain electrodes; removing the first oxide layer; etching the auxiliary hard mask layer to form a polysilicon gate electrode and a gate medium layer; oxidizing the polysilicon gate electrode for the second time to form a second oxide layer; forming first side walls on a semiconductor substrate and two sides of the polysilicon grate electrode; injecting for the second time to form low doping source/drain electrodes and then forming a second medium layer; and annealing. By adjusting the process of the MOS transistor, the high doping source/drain electrodes are formed before the low doping source/drain electrodes are formed, and the high doping source/drain electrodes and the low doping source/drain electrodes are only annealed once, and over-large diffusion area can not be caused by long-time annealing, thereby facilitating the form of ultra shallow junctions.

Description

The manufacture method of MOS transistor

Technical field

The present invention relates to technical field of semiconductors, particularly the manufacture method of MOS transistor.

Background technology

, speed faster device development littler along with semi-conductor industry court, the feature lateral dimension and the degree of depth of semiconductor device reduce gradually, require more and more higher to device performance.

A kind of manufacture method of MOS transistor in being the United States Patent (USP) of US6512273, the patent No. is disclosed, form polysilicon side wall by transistor to the N raceway groove, transistor to the p raceway groove forms the silicon nitride side wall, thereby optimizes the hot carrier life-span of the drive current of every kind of device with raising n channel device.

A kind of manufacture method of MOS transistor in being the United States Patent (USP) of US5869379, the patent No. is disclosed, by form the air side wall in the polygate electrodes both sides, reduce the lateral electric capacity between the adjacent gate electrode, reduce the coupling capacitance between gate electrode and the source/drain simultaneously.

Therefore, as can be seen, prior art has been made various effort, to obtain high performance MOS transistor.

Yet along with the size of MOS transistor continue dwindle, the thickness of gate dielectric layer and voltage source voltage are not scaled, this makes the degeneration that is difficult to suppress the caused device performance of short channel (SCE) effect.Therefore, need the super shallow junction of preparation (USJ) to suppress short-channel effect, yet, this can increase the difficulty that reduces drain junction capacitance and junction leakage, especially for the nMOS transistor, because voltage source voltage is not scaled, the interface has higher electric field between drain electrode/halo (Halo), especially when the halo that adopts higher-doped concentration injects.

The patent No. a kind of method that forms MOS transistor that has been 6624014 U.S. Patent Publication, in this method in order to form P+/N type and the super shallow junction of N+/P type, by having on the Semiconductor substrate of grid structure deposition one deck silicon nitride layer as a resilient coating, and then carry out ion in the dopant well in Semiconductor substrate and inject, can overcome the difficulty of the low energy injection of prior art.

Prior art also discloses a kind of method that forms MOS transistor, please refer to Fig. 1, comprise: step S101, Semiconductor substrate is provided, in Semiconductor substrate, form isolation structure, described isolation structure is divided into different active areas with Semiconductor substrate, forms dopant well in described active area, adjusts threshold voltage and inject in dopant well; S103 forms grid structure on Semiconductor substrate; Step S105 carries out low-doped drain (LDD) injection and halo and injects; Step S107 carries out first annealing; Step S109 forms side wall; Step S111 carries out heavy-doped source/drain electrode and injects; Carry out second annealing.

Also comprise more step in the technology of certain existing formation MOS transistor, do not enumerate one by one herein.

In the method for above-mentioned formation MOS transistor, in order to prevent to occur break-through (overrun) between source electrode and the drain electrode and suppress short-channel effect, the injection of formation source/drain electrode is divided into two steps, be that low-doped drain is injected and heavy-doped source/drain electrode is injected, yet in said method, inject formed injection region for low-doped drain and need experience at least twice annealing, and every many once annealing, with increasing the diffusion zone of the ion that injects, will be difficult to form super shallow junction and wayward horizontal proliferation.

Summary of the invention

The problem that the present invention solves provides a kind of manufacture method of MOS transistor, has the MOS transistor of super shallow junction with formation.

For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprising: Semiconductor substrate is provided, is formed with first dielectric layer and polysilicon layer on the described Semiconductor substrate; Utilize the auxiliary mask version that first dielectric layer and polysilicon layer are carried out first etching, form auxiliary hard mask layer; Polysilicon layer in the auxiliary hard mask layer is carried out oxidation, in peripheral first oxide layer that forms of polysilicon layer; Carry out first and inject, form heavy-doped source/drain electrode; Remove first oxide layer; Etching is assisted hard mask layer, forms polygate electrodes and gate dielectric layer; Polygate electrodes is carried out second oxidation, in peripheral second oxide layer that forms of polygate electrodes; On Semiconductor substrate, the polygate electrodes both sides form first side wall; Carry out second and inject, form low doping source/drain electrode; Form second dielectric layer; Anneal.

Described auxiliary hard mask layer be distance between the heavy-doped source/drain electrode of MOS transistor to be formed in the size on the orientation.

The described spike annealing that is annealed into, the temperature range of annealing are 1030 to 1090 degrees centigrade, and temperature rate-of-rise is 70 to 250 degrees centigrade of per seconds, and the temperature fall off rate is 70 to 250 degrees centigrade of per seconds.

The gas that feeds during described annealing is inert gas or nitrogen.

The flow that feeds described inert gas is 0.3 to 9 Liter Per Minute.

The flow that feeds nitrogen is 0.3 to 9 Liter Per Minute.

The flow that feeds nitrogen is 0.3 to 5 Liter Per Minute.

Also comprise and carry out the halo implantation step, described halo implantation step second inject before or carry out afterwards.

Also be included on the Semiconductor substrate after annealing, form the second side wall step on first side wall of polygate electrodes both sides.

After forming second side wall, also comprise the formation silicide step.

Compared with prior art, the technical program has the following advantages: by adjusting the technology of MOS transistor, form heavy-doped source/drain electrode earlier, form low doping source/drain electrode again, because after low doping source/drain electrode is formed on, its injection region only experiences once annealing, can not cause that diffusion area is excessive owing to passing through to anneal for a long time, helps forming super shallow junction;

By improving annealing process, heavy-doped source/drain electrode and low doping source/drain electrode are all only once annealed, reduced the heat budget of device generally, help the stable of device performance, and can enough satisfy active ions and make it spread uniform purpose.

Description of drawings

Fig. 1 is the schematic flow sheet of the formation cmos device of prior art;

Fig. 2 is the schematic flow sheet of the formation cmos device of one embodiment of the present of invention;

Fig. 3 to Figure 13 is the transistorized cross-sectional view of formation nMOS of one embodiment of the present of invention;

Figure 14 is the distribution profile (profile) of the LDD injection region of prior art and optimization of the present invention.

Embodiment

As previously mentioned, based on above-mentioned experimental study and theoretical derivation, the present inventor finds that the LDD injection region of prior art need experience twice annealing at least, is difficult to form super shallow junction and is difficult to carry out horizontal proliferation control.Based on above-mentioned discovery, the present inventor only once anneals the LDD injection region by changing technology, and annealing process is improved, to reduce the diffusion that LDD injects the depth direction of ion, under this technical scheme, do not resemble and reduce dosage or the energy that LDD injects the conventional art and form shallow junction, therefore can prevent that the ions diffusion area of LDD injection region is excessive, help forming super shallow junction; Simultaneously owing to reduce and inject energy and dosage, can keep the LDD injection region than low resistance, higher drain saturation current, thus suppress short-channel effect; And adopting this scheme can overcome the break-through (overrun) of source/drain electrode, the injection window that can increase source/drain electrode like this to be reducing active area resistance, to increase drain saturation current, and the break-through problem can not occur and cause the degeneration of device performance.

Below describe specific embodiment in detail by accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:

The present invention at first provides a kind of manufacture method of MOS transistor, specifically please refer to Fig. 2, comprising: execution in step S101, Semiconductor substrate is provided, and be formed with first dielectric layer and polysilicon layer on the described Semiconductor substrate; Execution in step S103 utilizes the auxiliary mask version that first dielectric layer and polysilicon layer are carried out first etching, forms auxiliary hard mask layer; Execution in step S105 carries out oxidation to the polysilicon layer in the auxiliary hard mask layer, forms first oxide layer; Execution in step S107 carries out first and injects, and forms heavy-doped source/drain electrode; Execution in step S109 removes first oxide layer; Execution in step S111, etching is assisted hard mask layer, forms polygate electrodes and gate dielectric layer; Execution in step S113 carries out second oxidation to polygate electrodes, forms second oxide layer; Execution in step S115, the polygate electrodes both sides on Semiconductor substrate form first side wall; Execution in step S117 carries out second and injects, and forms low doping source/drain electrode; Execution in step S119 forms second dielectric layer; Execution in step S121 anneals.

Describing formation MOS transistor technology of the present invention in detail below in conjunction with Fig. 3 to Figure 13, in the present embodiment, is that example is illustrated with the transistorized formation technology of nMOS.

At first with reference to Fig. 3, provide Semiconductor substrate 100, be formed with isolation structure 101 in the described Semiconductor substrate 100, described isolation structure 101 is divided into Semiconductor substrate 100 the different active areas (unmarked) of MOS transistor to be formed.The conduction type of described Semiconductor substrate 100 can adopt the p type usually for n type or p type.

Also be formed with pad oxide 103 on the described Semiconductor substrate 100, be used for the follow-up ion that injects in the protection of injection ion formation dopant well technology, prevent to inject ion and overflow.

In the active area of Semiconductor substrate 100, introduce first ion, form dopant well 102.The kind of the MOS transistor that described first ion and this active area are to be formed is relevant, if the channel type of MOS transistor to be formed is the n type, then first ion is the p type, such as being generally the boron ion; If the channel type of MOS transistor to be formed is the p type, then first ion is the n type, such as being generally phosphonium ion.MOS transistor in the present embodiment is the n type, so the conduction type of dopant well should be the p type.

Simultaneously, the structure of dopant well 102 can also comprise multiple, be not limited to single dopant well 102 structures of diagram in the present embodiment, can be the triple-well structure, such as: if Semiconductor substrate is the p type, then can injects n type ion and form first dopant well, can form p type MOS transistor in this first dopant well, nMOS transistor area in first dopant well is injected p type ion then, forms second dopant well, forms n type MOS transistor then in this second dopant well.

Then, with reference to Fig. 4, in the dopant well 102 of Semiconductor substrate 100, introduce second ion, to adjust the threshold voltage of MOS transistor to be formed.Usually, introducing second ion at active area forms by injecting.

Inject after second ion, form the second ion district 104 in the channel region of the MOS transistor in isolation well 102.Simultaneously, this second ion district 104 also extends in the low doping source/drain electrode of raceway groove both sides of follow-up formation.

Equally in this step, in fact can directly adopt the mask that forms isolation well, second ion that promptly works the injection of adjusting the threshold voltage effect can be not limited to only be infused in the channel region of MOS transistor to be formed, can not bring ill effect equally even be injected into the low doping source/drain region of raceway groove both sides.

Described second ion is different and different according to MOS transistor kind to be formed, if the channel type of MOS transistor to be formed is the n type, then second ion is the p type, such as being boron ion or indium ion; If the channel type of MOS transistor to be formed is the p type, then second ion is the n type, such as being phosphonium ion or arsenic ion.

Usually after the formation dopant well 102 and the second ion district 104, need anneal to the ion that injects, so that its diffusion evenly, this technology is a techniques well known, is not described in detail in this.

With reference to Fig. 5, remove pad oxide 103; On Semiconductor substrate 100, form first dielectric layer 106 and polysilicon layer 107.

Described first dielectric layer 106 can be silica, silicon nitride, silicon oxynitride or other high k materials, and the thickness range of described first dielectric layer 106 is mainly determined according to the applied voltage scope of device.

With reference to Fig. 6, utilize the auxiliary mask version that first dielectric layer 106 and polysilicon layer 107 are carried out first etching, form auxiliary hard mask layer.

To form grid structure different for the step that first dielectric layer 106 and polysilicon layer 107 are carried out first etching and the direct etching of prior art herein, but its structure is bigger a little than grid structure size, distance between the concrete heavy-doped source/drain electrode that is equivalent to MOS transistor to be formed, so the effect that comprises the auxiliary hard mask layer of the polysilicon layer 107 after the etching and first dielectric layer 106 mainly is to be used for mask.

With reference to Fig. 7, the polysilicon layer 107 in the auxiliary hard mask layer is carried out oxidation, in polysilicon layer 107 peripheral first oxide layers 108 that form.

The purpose that forms first oxide layer 108 is for to protect polysilicon layer.

In to polysilicon 107 oxidations, Semiconductor substrate 100 is also oxidized, therefore also is formed with first oxide layer 108 thereon.

With reference to Fig. 8, carry out first and inject, form heavy-doped source/drain electrode 109.

Usually carry out to anneal after first injection, so that the ions diffusion of injecting is even, promptly activate this ion, but the application has omitted this step annealing, and also can fully activate the ion of injection by improving technology.

With reference to Fig. 9, remove first oxide layer 108.Described removal first oxide layer 108 can adopt dry method or wet etching.

With reference to Figure 10, etching is assisted hard mask layer, forms gate dielectric layer 110 and polygate electrodes 111.

Gate dielectric layer 111 that forms in this step and polygate electrodes 110 are equivalent to channel length dimension along the size of the orientation of MOS transistor.

With reference to Figure 11, polygate electrodes 111 is carried out second oxidation, in polygate electrodes 111 peripheral second oxide layers 112 that form.

The purpose that forms second oxide layer 112 is for to protect polysilicon layer.In to polygate electrodes 111 oxidations, Semiconductor substrate 100 is also oxidized, therefore also is formed with second oxide layer 112 thereon.

Then, on Semiconductor substrate 100, the both sides of polygate electrodes 111 form first side wall 113, described first side wall 113 can be silica or silicon nitride, adopts silica usually.

With reference to Figure 12, in Semiconductor substrate 100, carry out second and inject, form low doping source/drain electrode 114.

Usually, before forming low doping source/drain electrode 114 or also carry out halo afterwards and inject (Halo), described halo implantation step is before second injection or carry out afterwards.Carry out halo and be injected to present technique field personnel's known technology, be not described in detail in this.

With reference to Figure 13, on second oxide layer 112 and first side wall layer 113, form second dielectric layer 115, form second dielectric layer, 115 purposes for preventing in the subsequent anneal technology that the ion that is infused in the Semiconductor substrate 100 is overflowed, and prevents from simultaneously in the subsequent anneal impurity to be introduced in the Semiconductor substrate 100.Described second dielectric layer can be materials such as silica, silicon nitride, adopts silica usually.

Then, low doping source/drain electrode 114 is annealed.The described spike annealing that is annealed into, the temperature range of annealing are 1030 to 1090 degrees centigrade, and temperature rate-of-rise is 70 to 250 degrees centigrade of per seconds, and fall off rate is 70 to 250 degrees centigrade of per seconds.The gas that feeds during described annealing is inert gas or nitrogen, the flow that feeds described inert gas is 0.3 to 9 Liter Per Minute, if feeding gas is nitrogen, the flow of nitrogen is 0.3 to 9 Liter Per Minute, but inventor's discovery, if the nitrogen that feeds is too much, the nitrogen ion may be introduced device, influence the performance of device, therefore further optimally, the flow of described nitrogen is 0.3 to 5 Liter Per Minute.

Compared with prior art, the present invention controls low doping source/drain electrode 114 zones only through once annealing, reduced the difficulty of technology controlling and process and device performance modulation, avoided must distributing again through the impurity that heavy-doped source/drain anneal caused in the prior art, thus make the device short-channel effect can be improved significantly; Simultaneously, anneal and activate the impurity of low doping source/drain electrode 114 and heavy-doped source/drain electrode injection simultaneously by utilizing low doping source/drain electrode 114 ions to inject back one suboptimization, thereby can omit heavy-doped source in the prior art/drain ion and inject post anneal, make total heat budget reduce, help the reduction of the stable and manufacturing cost of semiconductor device layer.

Usually, after annealing, also be included on the Semiconductor substrate 100, form the second side wall step and form silicide step on first side wall of polygate electrodes 111 both sides.Forming second side wall and forming silicide is present technique field personnel's known technology, is not described in detail in this.

The present invention is by adjusting the technology of MOS transistor, form heavy-doped source/drain electrode 109 earlier, form low doping source/drain electrode 114 again, and annealing process is improved, reduced the heat budget of device generally, and can enough satisfy active ions and make it spread uniform purpose; And, can not cause that diffusion area is excessive owing to passing through to anneal for a long time because after low doping source/drain electrode 114 was formed on, its injection region only experienced once annealing, help forming super shallow junction.Respectively semiconductor device of the present invention is simulated under TSUPREM4 in the TCAD simulation softward of employing U.S. Si Nuofeisi (Synopsys) company and the MEDICI environment.The process conditions of simulation are 65nm, and Semiconductor substrate is a silicon.

Figure 14 provides the close current (Ioff) of the MOS transistor that prior art (curve I), the present invention (curve II) form and the relation between the drain saturation current (Idsat).As can be seen, the close current of the MOS transistor of the present invention's formation decreases than prior art.The MOS transistor performance that the present invention's formation is described is more stable.

Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims

1. the manufacture method of a MOS transistor is characterized in that, comprising:

Semiconductor substrate is provided, is formed with first dielectric layer and polysilicon layer on the described Semiconductor substrate;

Utilize the auxiliary mask version that first dielectric layer and polysilicon layer are carried out first etching, form auxiliary hard mask layer;

Polysilicon layer in the auxiliary hard mask layer is carried out oxidation, in peripheral first oxide layer that forms of polysilicon layer;

Carry out first and inject, form heavy-doped source/drain electrode;

Remove first oxide layer;

Etching is assisted hard mask layer, forms polygate electrodes and gate dielectric layer;

Polygate electrodes is carried out second oxidation, in peripheral second oxide layer that forms of polygate electrodes;

On Semiconductor substrate, the polygate electrodes both sides form first side wall;

Carry out second and inject, form low doping source/drain electrode;

Form second dielectric layer;

Anneal, the described spike annealing that is annealed into, the temperature range of annealing is 1030 to 1090 degrees centigrade, and temperature rate-of-rise is 70 to 250 degrees centigrade of per seconds, and the temperature fall off rate is 70 to 250 degrees centigrade of per seconds.

2. the manufacture method of MOS transistor according to claim 1 is characterized in that, described auxiliary hard mask layer be distance between the heavy-doped source/drain electrode of MOS transistor to be formed in the size on the orientation.

3. the manufacture method of MOS transistor according to claim 1 and 2 is characterized in that, the gas that feeds during described annealing is inert gas or nitrogen.

4. the manufacture method of MOS transistor according to claim 3 is characterized in that, the flow that feeds described inert gas is 0.3 to 9 Liter Per Minute.

5. the manufacture method of MOS transistor according to claim 3 is characterized in that, the flow that feeds nitrogen is 0.3 to 9 Liter Per Minute.

6. the manufacture method of MOS transistor according to claim 5 is characterized in that, the flow that feeds nitrogen is 0.3 to 5 Liter Per Minute.

7. the manufacture method of MOS transistor according to claim 1 and 2 is characterized in that, also comprise carrying out the halo implantation step, described halo implantation step second inject before or carry out afterwards.

8. the manufacture method of MOS transistor according to claim 1 is characterized in that, also is included on the Semiconductor substrate after annealing, forms the second side wall step on first side wall of polygate electrodes both sides.

9. the manufacture method of MOS transistor according to claim 8 is characterized in that, also comprises the formation silicide step after forming second side wall.