CN101924553A - Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure - Google Patents
Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure Download PDFInfo
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- CN101924553A CN101924553A CN 201010281878 CN201010281878A CN101924553A CN 101924553 A CN101924553 A CN 101924553A CN 201010281878 CN201010281878 CN 201010281878 CN 201010281878 A CN201010281878 A CN 201010281878A CN 101924553 A CN101924553 A CN 101924553A
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Abstract
The invention belongs to the technical field of clock frequency division, in particular relates to a divide-by-2 frequency divider structure based on a standard complementary metal oxide semiconductor (CMOS) process and suitable for an ultra-wide band. The divide-by-2 frequency divider consists of two primary and secondary differential analog D latches, wherein each D latch is a dynamic bias taking a pair of differential N-channel metal oxide semiconductor (NMOS) tubes as an amplifying part, a pair of crossly coupled positive feedback NMOS tubes as a latching part, a pair of p-channel metal oxide semiconductor (PMOS) tubes as a load and a pair of clocked NMOS tubes as the amplifying part and the latching part respectively; the magnitude of the bias voltage of the PMOS tubes changes along with frequencies; and a frequency-voltage converting circuit provides a bias for the PMOS tube load. The divide-by-2 frequency divider structure can effectively increase the working frequency range of a frequency divider; and the ratio of an upper limit frequency to a lower limit frequency of the divide-by-2 frequency divider structure can reach about 250. The circuit of the invention has the characteristics of low power consumption and noise, high speed and the like.
Description
Technical field
The invention belongs to technical field of clock frequency division, be specifically related to a kind of two-divider structure that is applicable to ultra broadband based on standard CMOS process.
Background technology
Along with the development of broadband wireless communication technique, the high-performance clock circuit more and more becomes the bottleneck that this technology deeply develops.High frequency divider is as one of key modules of high frequency frequency synthesizer, and major function is exactly with system's maximum clock two divided-frequency, and output orthogonal I, Q signal as required.In addition, it can be 50% duty cycle signals with the non-50% duty cycle signals two divided-frequency of high speed.It has not only determined the maximum operating frequency of system, and its performance will directly influence the phase noise of phase-locked loop circuit and power consumption or the like.
At present, the frequency divider of main flow comprises following three types: 1) current-mode latchs type (CML) (or being referred to as source-coupled logic (SCL)); 2) injection locking type; 3) regeneration type.Compared to other two kinds of structures, the CML structure has the working band of relative broad, and moreover, it has the good restraining effect to in-band noise.Therefore the CML structure applications is the most extensive.
The load of traditional C ML structure mainly is to constitute by two kinds: 1) dead load (resistance, be in the metal-oxide-semiconductor of linear work); 2) dynamic load.Use just because of this load makes that the band operation bandwidth of CML is wide relatively inadequately, and shortcoming such as power consumption height.
Summary of the invention
The object of the present invention is to provide a kind ofly based on CMOS technology, be applicable to the two-divider of ultra broadband.
The two-divider that is applicable to ultra broadband that the present invention proposes, its circuit structure comprises two host-guest architecture difference analogue D-latchs, two D-latchs are connected into negative feedback type, as shown in Figure 2.It is input as differential signal, sees among the figure
With
, can be sine wave signal, also can be square-wave signal.
Among the present invention, two D-latchs are formed by 8 metal-oxide-semiconductor M1-M8, and wherein, the 7th, the 8th metal-oxide-semiconductor M7, M8 constitute amplifier tube, are operated in the phase of following of clock, i.e. the positive half period of signal CK, and its grid connects input signal; Five, the 6th metal-oxide-semiconductor M5, M6 formation latchs pipe, is operated in the phase that latchs of clock, i.e. the negative half-cycle of signal CK; First, second metal-oxide-semiconductor M1, M2 constitute a pair of dynamic load with frequency change, constitute a kind of common source differential amplifier circuit with amplifier tube, and certain gain is provided; The 3rd metal-oxide-semiconductor M3 constitutes the dynamic bias of logical gate, is operated in the phase of following of clock; The 4th metal-oxide-semiconductor M4 constitutes the dynamic bias that latchs part, is operated in the phase that latchs of clock.The 4th metal-oxide-semiconductor M4 has reduced the dynamic range of output node, helps reducing power consumption.
Among the present invention, also provide the change-over circuit of a frequency to voltage.During work, frequency can be exported a voltage according to the frequency of input signal to the change-over circuit of voltage and biasing is provided for first, second M1, M2 pipe, and the size of output voltage is with frequency change.
Described frequency arrives the change-over circuit of voltage by resistance R 1, capacitor C 1, diode D1, resistance R 2 and capacitor C 2, and capacitor C 3, resistance R 3 are formed; Wherein, resistance R 1 constitutes low pass filter with capacitor C 1, and amplitude of output voltage is relevant with the frequency of input signal; Diode D1, resistance R 2 and capacitor C 2 are finished the AC-DC translation function; Capacitor C 3 is a partiting dc capacitor, and resistance R 3 is every AC signal resistance, and direct voltage is provided.
Thereby the present invention by reducing the RC constant that load reduces output node, improves the maximum operating frequency of circuit when high frequency; Thereby when low frequency,, reduce the circuit lowest operating frequency by increasing the RC constant that load increases output node.Effectively increased the operating frequency range of frequency divider by this technology, its bound frequency ratio can reach about 250.Circuit of the present invention possesses performances such as low-power consumption, low noise, high speed simultaneously.
The present invention has following beneficial effect:
1, can effectively widen the operating frequency range of two-divider;
2, can make two-divider be operated in hundred megahertzes to tens gigahertz band;
3, can between performances such as power consumption, noise, broadband, speed, well be compromised;
4, can be that the design of system of broadband wireless communication, particularly radio ultra wide band system brings convenience.
Description of drawings
Fig. 1 is the two-divider block diagram of CML structure.
Fig. 2 is the two-divider sequential chart of CML structure.
Fig. 3 is the physical circuit figure of two-divider of the present invention.
Fig. 4 follows the circuit diagram of phase for two-divider of the present invention.
Fig. 5 latchs the circuit diagram of phase for two-divider of the present invention.
Fig. 6 is the circuit diagram of two-divider frequency of the present invention to voltage transitions.
Embodiment
The present invention is described in more detail below in conjunction with accompanying drawing.
Fig. 1 is the structured flowchart of CML structure two-divider.This structure comprises two host-guest architecture difference D-latchs, and these two latchs are connected into negative feedback type, and input clock is a differential signal
With
, can be sinusoidal signal, also can be square-wave signal.Export two pairs of difference in orthogonality sub-signals:
With
,
With
At the positive half period of clock, main latch is operated in following state, its output
,
Follow input
,
Be operated in latch mode from latch, its output remains unchanged, and is the output of previous clock phase
,
At the negative half-cycle of clock, main latch is operated in latch mode, and its output remains unchanged, and is the output of previous clock phase
,
Be operated in following state from latch, its output
,
Follow input
,
Fig. 2 is the sequential chart of Fig. 1, output signal
,
With
,
Mutually orthogonal, and its frequency is input signal
,
Half.
Fig. 3 is the physical circuit figure of novel two-divider provided by the invention.Metal-oxide-semiconductor M7, M8 constitute logical gate, are operated in the phase of following of clock, i.e. the positive half period of CK signal, and its grid connects input signal; Metal-oxide-semiconductor M5, M6 formation latchs part, is operated in the phase that latchs of clock, i.e. the negative half-cycle of CK signal; Metal-oxide-semiconductor M1, M2 constitute a pair of dynamic load with frequency change, constitute a kind of common source differential amplifier circuit with logical gate, and certain gain is provided; Metal-oxide-semiconductor M3 constitutes the dynamic bias of logical gate, is operated in the phase of following of clock; Metal-oxide-semiconductor M4 constitutes the dynamic bias that latchs part, is operated in the phase that latchs of clock.Metal-oxide-semiconductor M4 has reduced the dynamic range of output node, helps reducing power consumption, improves operating frequency.
Fig. 4 follows the circuit diagram of phase for novel two-divider provided by the invention.Metal-oxide-semiconductor M7 or M8 work this moment, metal-oxide-semiconductor M1, M2 work, remaining tubing is not all worked.This circuit constitutes amplifier, makes output follow input.
Fig. 5 latchs the circuit diagram of phase for novel two-divider provided by the invention.Metal-oxide-semiconductor M5 or M6 work this moment, metal-oxide-semiconductor M1, M2 work, remaining tubing is not all worked.This circuit constitutes positive feedback structure, and latch output signal remains unchanged it.Metal-oxide-semiconductor M4 is used to regulate the output node amplitude of oscillation, saves power consumption, improves operating frequency.
Fig. 6 is the circuit diagram of novel two-divider frequency provided by the invention to voltage transitions.Resistance R 1 constitutes low pass filter with capacitor C 1, and amplitude of output voltage is relevant with the frequency of input signal; Diode D1, resistance R 2 and capacitor C 2 are finished the AC-DC translation function; Capacitor C 3 is a partiting dc capacitor, and resistance R 3 is every AC signal resistance, and direct voltage is provided.
Claims (4)
1. a CMOS ultra broadband two-divider structure is characterized in that, this structure comprises two host-guest architecture difference analogue D-latchs, and two D-latchs are connected into negative feedback type; It is input as differential signal:
With
, be sine wave signal, perhaps think square-wave signal.
2. CMOS ultra broadband two-divider structure according to claim 1 is characterized in that described D-latch is by by 8 metal-oxide-semiconductor (M1-M8) form; Wherein, the 7th, the 8th metal-oxide-semiconductor (M7, M8) constitutes amplifier tube, is operated in the phase of following of clock, i.e. the positive half period of signal CK, and its grid connects input signal; Five, the 6th metal-oxide-semiconductor (M5, M6) formation latchs pipe, is operated in the phase that latchs of clock, i.e. the negative half-cycle of signal CK; First, second metal-oxide-semiconductor (M1, M2) constitutes a pair of dynamic load with frequency change, constitutes a kind of common source differential amplifier circuit with amplifier tube, and certain gain is provided; The 3rd metal-oxide-semiconductor (M3) constitutes the dynamic bias of logical gate, is operated in the phase of following of clock; The 4th metal-oxide-semiconductor (M4) constitutes the dynamic bias that latchs part, is operated in the phase that latchs of clock.
3. CMOS ultra broadband two-divider structure according to claim 1 and 2 is characterized in that also comprising the change-over circuit of a frequency to voltage; During work, frequency provides biasing for first, second metal-oxide-semiconductor (M1, M2) to the change-over circuit of voltage according to the frequency output voltage of input signal, and the size of output voltage is with frequency change.
4. CMOS ultra broadband two-divider structure according to claim 3, it is characterized in that described frequency to the change-over circuit of voltage by resistance R 1, capacitor C 1, diode D1, resistance R 2 and capacitor C 2, capacitor C 3, resistance R 3 are formed; Wherein, resistance R 1 constitutes low pass filter with capacitor C 1; Diode D1, resistance R 2 and capacitor C 2 are finished the AC-DC translation function; Capacitor C 3 is a partiting dc capacitor, and resistance R 3 is every AC signal resistance, and direct voltage is provided.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012129553A1 (en) * | 2011-03-23 | 2012-09-27 | Qualcomm Incorporated | A frequency divider circuit |
| CN102916695A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN103532544A (en) * | 2013-09-24 | 2014-01-22 | 南京中科微电子有限公司 | Low-power-consumption divide-by-two frequency divider with gating function |
| CN106452435A (en) * | 2016-09-23 | 2017-02-22 | 无锡中科微电子工业技术研究院有限责任公司 | Signal enhancement prescaler |
| CN111726139A (en) * | 2020-06-17 | 2020-09-29 | 广州昂瑞微电子技术有限公司 | Divide by two frequency division circuit and bluetooth transceiver |
| CN111879999A (en) * | 2020-07-31 | 2020-11-03 | 东南大学 | Low-temperature coefficient rapid voltage detection circuit |
| CN113346894A (en) * | 2021-06-08 | 2021-09-03 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| CN114553218A (en) * | 2022-01-12 | 2022-05-27 | 中国电子科技集团公司第十研究所 | Silicon-based broadband high-speed reconfigurable orthogonal frequency divider |
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| CN1129369A (en) * | 1994-11-03 | 1996-08-21 | 摩托罗拉公司 | Circuit and method for reducing a gate voltage of a transmission gate within a charge pump circuit |
| US20030052720A1 (en) * | 2001-09-05 | 2003-03-20 | Tung John C. | D-type latch with asymmetrical high-side MOS transistors for optical communication |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
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2010
- 2010-09-15 CN CN2010102818789A patent/CN101924553B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129369A (en) * | 1994-11-03 | 1996-08-21 | 摩托罗拉公司 | Circuit and method for reducing a gate voltage of a transmission gate within a charge pump circuit |
| US20030052720A1 (en) * | 2001-09-05 | 2003-03-20 | Tung John C. | D-type latch with asymmetrical high-side MOS transistors for optical communication |
| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012129553A1 (en) * | 2011-03-23 | 2012-09-27 | Qualcomm Incorporated | A frequency divider circuit |
| US8829954B2 (en) | 2011-03-23 | 2014-09-09 | Qualcomm Incorporated | Frequency divider circuit |
| CN102916695A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN102916695B (en) * | 2012-11-02 | 2014-03-12 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN103281071B (en) * | 2013-06-21 | 2016-04-13 | 中国科学院上海高等研究院 | Latch and comprise the divider circuit of this latch |
| CN103532544A (en) * | 2013-09-24 | 2014-01-22 | 南京中科微电子有限公司 | Low-power-consumption divide-by-two frequency divider with gating function |
| CN103532544B (en) * | 2013-09-24 | 2016-06-01 | 南京中科微电子有限公司 | The low-power consumption of a kind of band gating function is except two-divider |
| CN106452435A (en) * | 2016-09-23 | 2017-02-22 | 无锡中科微电子工业技术研究院有限责任公司 | Signal enhancement prescaler |
| CN106452435B (en) * | 2016-09-23 | 2019-05-21 | 无锡中科微电子工业技术研究院有限责任公司 | Signal enhancing pre-divider |
| CN111726139A (en) * | 2020-06-17 | 2020-09-29 | 广州昂瑞微电子技术有限公司 | Divide by two frequency division circuit and bluetooth transceiver |
| CN111879999A (en) * | 2020-07-31 | 2020-11-03 | 东南大学 | Low-temperature coefficient rapid voltage detection circuit |
| CN111879999B (en) * | 2020-07-31 | 2023-03-14 | 东南大学 | Low-temperature coefficient rapid voltage detection circuit |
| CN113346894A (en) * | 2021-06-08 | 2021-09-03 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| WO2022257246A1 (en) * | 2021-06-08 | 2022-12-15 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| CN113346894B (en) * | 2021-06-08 | 2024-05-31 | 李世杰 | Logic operation circuit and electronic device |
| CN114553218A (en) * | 2022-01-12 | 2022-05-27 | 中国电子科技集团公司第十研究所 | Silicon-based broadband high-speed reconfigurable orthogonal frequency divider |
| CN114553218B (en) * | 2022-01-12 | 2023-12-01 | 中国电子科技集团公司第十研究所 | Silicon-based broadband high-speed reconfigurable orthogonal frequency divider |
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