CN101916306A - System and method for positioning FPGA chip sensitive area - Google Patents
System and method for positioning FPGA chip sensitive area Download PDFInfo
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- CN101916306A CN101916306A CN 201010232855 CN201010232855A CN101916306A CN 101916306 A CN101916306 A CN 101916306A CN 201010232855 CN201010232855 CN 201010232855 CN 201010232855 A CN201010232855 A CN 201010232855A CN 101916306 A CN101916306 A CN 101916306A
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Abstract
The invention relates to a system for positioning an FPGA chip sensitive area, which comprises a manufacture fault control module, a fault injection module and a sensitive area detection module. In the system, the position connection relation comprises that: the fault control module outputs generated required configuration information containing fault information to the fault injection module; the fault injection module injects the configuration information into a target FPGA; and the sensitive area detection module detects and compares a signal outputted by the target FPGA in real time. A method for positioning the FPGA chip sensitive area comprises the three steps of: 1, according to the logic of the target FPGA, finding an area in which a target FPGA chip is positioned in logic design through the compiling of Xilinx ISE 9.li; 2, mapping to the position of the configuration information stored in a FLASH chip according to the determined area, after negating one bit of the configuration information, performing fault injection on the target FPGA, and reversing configuration information bits of the target FPGA bit by bit; and 3, detecting whether the output of the target FPGA generates error or not so as to judge whether the area is the sensitive area or not.
Description
(1) technical field
The present invention relates to a kind of system and method thereof that is used for field programmable gate array (being called for short FPGA) location, sensitizing range.It can detect the sensitizing range of fpga chip under the Different Logic design of different model fast and effectively.In the environment of the outer space, cause single-particle inversion fault (being called for short SEU) by space radiation, this fault will produce mistake to the normal operation of fpga logic, and its zone that single-particle inversion fault takes place is the sensitizing range.This invention belongs to satellite and uses FPGA QAT (quality assurance technique) field.
(2) background technology
Important component part as spacecraft, the reliability of FPGA directly has influence on its place subsystem, the reliability of whole satellite system even, yet, because it is shorter that FPGA is applied to the space industry time, exposed many designs, managerial problem in its use,, had a strong impact on the normal operation of satellite system as recurrent SEU fault.How efficiently and effectively addresses these problems, and promotes the FPGA design level of spacecraft, the designed reliability of assurance FPGA rapidly, is an important and urgent problem.
Occur in the SEU fault of sensitizing range in the fpga chip, tend to make the operation of FPGA internal logic to make a mistake, and then cause the run-time error of system.Since the fpga logic difference of different user design, the FPGA model difference of selecting for use, the responsive configuring area of its FPGA is also different, and this has just caused detection fpga chip sensitizing range to realize that difficulty is very big.At present, also do not have a kind of clear and definite effective method to locate the fpga chip sensitizing range, it is protected, strengthen its capability of resistance to radiation, guarantee the designed reliability of FPGA.
At the problems referred to above, the present invention proposes the sensitizing range that a kind of clear and definite system reliably and method thereof are located fpga chip.
(3) summary of the invention
1, purpose: the purpose of this invention is to provide a kind of system and method thereof that is used for location, fpga chip sensitizing range, it has overcome the clearly deficiency of effective detection and location FPGA sensitizing range of prior art, can clear and definite sensitizing range of locating fpga chip fast and effectively.
2, technical scheme:
(1) a kind of system that is used for location, fpga chip sensitizing range of the present invention, as shown in Figure 1, it comprises making FCM fault control module, fault injection module and sensitizing range detection module.Position annexation between them is: FCM fault control module will generate the required configuration information that contains failure message and export to the fault injection module, the fault injection module is injected into configuration information among the target FPGA, the signal that the sensitizing range detection module detects in real time and comparison object FPGA exports.
Described FCM fault control module is made up of software section and hardware components, the software section process flow diagram as shown in Figure 2, at first, inject the position of configuration information according to target faults, be mapped in the backup configuration information, the required configuration information that reads back will be wherein after negate, generates the required configuration information that contains failure message.Hardware components is made up of EEPROM (Electrically Erasable Programmable Read Only Memo) (being called for short EEPROM), micro-control unit (being called for short MCU), CPLD (being called for short CPLD) and flash memory (being called for short FLASH), as shown in Figure 3, position annexation therebetween is that EEPROM is that powering on of MCU code loads automatically, CPLD is responsible for MCU peripheral data bus, address bus are deciphered, and the configuration information of FLASH storage backup also provides required configuration information for the FCM fault control module software section.This EEPROM model is 24LC128; This MCU model is CY7C68013A; The EPM3512AQC208-10N that this CPLD produces for U.S. altera corp; This FLASH model is SST39VF6401.
Described fault injection module is made up of hardware MCU, CPLD and target fpga chip, as shown in Figure 4, position annexation therebetween is that instruction that has been provided with and the configuration information that contains failure message input to CPLD by MCU, through CPLD through decoding after, write to target FPGA earlier instruction is set, write the configuration information that contains failure message again, finish fault at last and inject.This target fpga chip is the XCV300 that U.S. Xilinx company produces.
Described sensitizing range detection module is made up of software, process flow diagram as shown in Figure 5, at first, output result after fault injected and the output result who does not have fault to inject, be that output result under the normal condition compares, see and whether make a mistake, if make a mistake, the positional information injected of record trouble then, this position is the sensitizing range of target fpga chip under this logical design; If there is not fault to take place, then continue to detect.
The principle of work of native system is: with original FPGA configuration information as reference information, on this basis, read one section configuration information in the reference information according to demand, negate is wherein generated the required configuration information that contains failure message, and be injected among the target FPGA.If injecting the fault zone is the sensitizing range of target FPGA, this failure message will impact the operate as normal of target FPGA, the output result of target FPGA is made a mistake, at this moment, with this output result and the output result who does not carry out the FPGA that fault injects make comparisons, can find this mistake, and the regional record that fault is injected gets off.
(2) a kind of method that is used for location, fpga chip sensitizing range of the present invention, it may further comprise the steps:
Step 1: as shown in Figure 6,, after the product XilinxISE of U.S. Xilinx company 9.1i compiling, check the placement-and-routing of FPGA inside, find out target fpga chip used zone in this logical design according to the existing target fpga logic that designs;
Step 2: according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault injects, with the configuration information position of target FPGA one by one step-by-step overturn;
Step 3: check whether target FPGA output makes a mistake, wrong as if detecting, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If do not detect mistake, the logic operation not influence of this regional configuration information to target FPGA then is described, not the sensitizing range.
Check the placement-and-routing of target FPGA inside in the described step 1 with compilation tool, the step implementation procedure of finding out the zone of using in the design of target fpga logic is as follows: the target fpga logic is after Xilinx ISE 9.1i compiling, find out the zone that the design of target fpga logic is used, write down their type and the row in this zone (being called for short Row) and row (being called for short Column), and calculate its main address (being called for short MJA) and (be called for short MNA) from the address.
In the described step 2 according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault to be injected, the step-by-step implementation procedure of overturning is as follows one by one with the configuration information position of target FPGA: according to the fixed regional location of step 1, pass through mapping algorithm, be mapped to the position that is stored in configuration information in the FLASH chip, read required configuration information, will be wherein after negate, generate the required configuration information that contains failure message, target fpga chip configuration information carried out fault inject, to configuration information one by one step-by-step overturn.
Described in the step 2 target FPGA is carried out fault and inject, step is as follows:
(1) as shown in Figure 7, behind the generation synchronization character, configuration register is set, close stance (being called for short Shutdown bit) is set, start and close (being called for short shutdown) function, prevent the circuit conflict;
(2) write the filling word, if the circuit contention takes place this moment, then (being called for short GHIGH_B) instruction is drawn high in statement; If the circuit contention does not take place, then need not state the GHIGH_B instruction, frame address register (being called for short FAR) is set again, frame address is provided by step 1, configuration data instruction (being called for short WCFG) is write in generation, write the number of words that will write data, write data to writing frame data input register (being called for short FDRI) again;
(3) write last frame instruction (being called for short LFRM), last, write infilled frame, fault is injected and is finished.
Check in the described step 3 that the output implementation procedure that whether makes a mistake is as follows: will press configuration information under the output result and normal condition behind the bit flipping, promptly configuration information is not compared by the result under the situation of bit flipping, if the result is inconsistent in output, wrong generation then is described, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If output is unanimity as a result, if explanation does not have wrong the generation, the logic operation not influence of this regional configuration information to target FPGA is described, not the sensitizing range.
3, advantage and effect: the present invention compared with prior art beneficial effect is:
(1) realize and can any of the configuration information of FPGA be overturn, the good SEU fault that in rail work, takes place of analog machine, and detect the influence of back of breaking down to equipment;
(2) this method is flexible, can detect the sensitizing range of the fpga chip (fpga chip need be supported the retaking of a year or grade function) of Different Logic design, different model fast and effectively.
(4) description of drawings
Fig. 1 the present invention locatees the system chart of fpga chip sensitizing range;
FCM fault control module software flow pattern among Fig. 2 the present invention;
FCM fault control module hardware composition diagram among Fig. 3 the present invention;
Fault injection module hardware composition diagram among Fig. 4 the present invention;
Fault detection module software flow pattern among Fig. 5 the present invention.
Fig. 6 the present invention locatees the process flow diagram of fpga chip sensitizing range;
Fig. 7 the present invention process flow diagram that the fault injection is carried out in step-by-step to the FPGA configuration information;
Symbol and code name among the figure are described as follows:
The EEPROM EEPROM (Electrically Erasable Programmable Read Only Memo); The MCU micro-control unit; The CPLD CPLD; The FLASH flash memory; The FPGA field programmable gate array; Shutdown bit close stance; GHIGH_B draws high instruction; MJA master address; MNA is from the address; FAR frame address register; WCFG writes the configuration data instruction; The word_count number of words; FDRI writes the frame data input register; The instruction of LFRM last frame.
(5) embodiment
(1) a kind of system that is used for location, fpga chip sensitizing range of the present invention, as shown in Figure 1, it comprises making FCM fault control module, fault injection module and sensitizing range detection module.Position annexation between them is: FCM fault control module will generate the required configuration information that contains failure message and export to the fault injection module, the fault injection module is injected into configuration information among the target FPGA, the signal that the sensitizing range detection module detects in real time and comparison object FPGA exports.This FCM fault control module according to the position of target configuration information, generates the required configuration information that contains failure message; This fault injection module writes the configuration information that contains failure message that generates in the configuration information of target FPGA; This sensitizing range detection module detects the output result of target FPGA in real time, and with correct output result comparison, if find mistake, then record injects the position of target configuration information, and this position is the sensitizing range of target FPGA.
Described FCM fault control module implementation procedure is: according to the position of target configuration information, from the configuration information of backup, read out correct data, will be wherein one digit number according to negate after, generate the required configuration information that contains failure message.
Described fault injection module implementation procedure is: it is reconfigurable state that the target fpga chip is set, and the configuration information that contains failure message that generates is write in the configuration information of target FPGA, in the process that writes, can not influence the operate as normal of FPGA.
Described sensitizing range detection module implementation procedure is: after writing the configuration information that contains failure message, detect the output result of target FPGA in real time, with correct output result comparison, if both are inconsistent, then find mistake, record injects the position of target configuration information.
Described FCM fault control module is made up of software section and hardware components, the software section process flow diagram as shown in Figure 2, at first, inject the position of configuration information according to target faults, be mapped in the backup configuration information, the required configuration information that reads back will be wherein after negate, generates the required configuration information that contains failure message.Hardware components is made up of EEPROM (Electrically Erasable Programmable Read Only Memo) (being called for short EEPROM), micro-control unit (being called for short MCU), CPLD (being called for short CPLD) and flash memory (being called for short FLASH), as shown in Figure 3, position annexation therebetween is that EEPROM is that powering on of MCU code loads automatically, CPLD is responsible for MCU peripheral data bus, address bus are deciphered, and the configuration information of FLASH storage backup also provides required configuration information for the FCM fault control module software section.This EEPROM model is 24LC128; This MCU model is CY7C68013A; The EPM3512AQC208-10N that this CPLD produces for U.S. altera corp; This FLASH model is SST39VF6401.
Described fault injection module is made up of hardware MCU, CPLD and target fpga chip, as shown in Figure 4, position annexation therebetween is that instruction that has been provided with and the configuration information that contains failure message input to CPLD by MCU, through CPLD through decoding after, write to target FPGA earlier instruction is set, write the configuration information that contains failure message again, finish fault at last and inject.This target fpga chip is the XCV300 that U.S. Xilinx company produces.
Described sensitizing range detection module is made up of software, process flow diagram as shown in Figure 5, at first, output result after fault injected and the output result who does not have fault to inject, be that output result under the normal condition compares, see and whether make a mistake, if make a mistake, the positional information injected of record trouble then, this position is the sensitizing range of target fpga chip under this logical design; If there is not fault to take place, then continue to detect.
The principle of work of native system is: with original FPGA configuration information as reference information, on this basis, read one section configuration information in the reference information according to demand, negate is wherein generated the required configuration information that contains failure message, and be injected among the target FPGA.If injecting the fault zone is the sensitizing range of target FPGA, this failure message will impact the operate as normal of target FPGA, the output result of target FPGA is made a mistake, at this moment, with this output result and the output result who does not carry out the FPGA that fault injects make comparisons, can find this mistake, and the regional record that fault is injected gets off.
(2) a kind of method that is used for location, fpga chip sensitizing range of the present invention may further comprise the steps:
Step 1: as shown in Figure 6,, after the product XilinxISE of U.S. Xilinx company 9.1i compiling, check the placement-and-routing of FPGA inside, find out target fpga chip used zone in this logical design according to the existing target fpga logic that designs;
Step 2: according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault injects, with the configuration information position of target FPGA one by one step-by-step overturn;
Step 3: check whether target FPGA output makes a mistake, wrong as if detecting, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If do not detect mistake, the logic operation not influence of this regional configuration information to target FPGA then is described, not the sensitizing range.
Check the placement-and-routing of target FPGA inside in the described step 1 with compilation tool, the step implementation procedure of finding out the zone of using in the design of target fpga logic is as follows: the target fpga logic is after Xilinx ISE 9.1i compiling, find out the zone that the design of target fpga logic is used, write down their type and the row in this zone (being called for short Row) and row (being called for short Column), and calculate its main address (being called for short MJA) and (be called for short MNA) from the address.
In the described step 2 according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault to be injected, the step-by-step implementation procedure of overturning is as follows one by one with the configuration information position of target FPGA: according to the fixed regional location of step 1, pass through mapping algorithm, be mapped to the position that is stored in configuration information in the FLASH chip, read required configuration information, will be wherein after negate, generate the required configuration information that contains failure message, target fpga chip configuration information carried out fault inject, to configuration information one by one step-by-step overturn.
Mapping algorithm is as follows described in the step 2:
If determine that by step 1 the position of target FPGA is logic configuration district (being called for short CLB), the start address that then is mapped to the FLASH storage is:
FlashAddr＝Configure_Byte+Center_Byte+(MJA-1)*CLB_Frame+(MNA-1)*Frame_Byte
If determine that by step 1 the position of target FPGA is input/output module (being called for short IOB), perhaps be random access memory district (being called for short RAM), the start address that then is mapped to the FLASH storage is:
FlashAddr＝Configure_Byte+Center_Byte+CLB_Byte+(MJA-CLB_N)*N_Frame
+(MNA-1)*Frame_Byte
Wherein, FlashAddr is the start address that is mapped to the FLASH store configuration information, Configure_Byte is the byte number that initialization is provided with FPGA in the configuration information, Center_Byte is the target fpga chip center byte number of (being called for short Center), MJA is main address, the byte number that CLB_Frame comprises for each CLB row, MNA is from the address, Frame_Byte is the byte number that every frame (being called for short Frame) comprises, CLB_Byte is the byte number that CLB comprises altogether, CLB_N is the columns of CLB, and N_Frame is the byte number that IOB or the every row of RAM comprise.
Fault implantation step described in the step 2 is as follows:
(1) as shown in Figure 7, behind the generation synchronization character, configuration register is set, close stance (being called for short Shutdown bit) is set, start and close (being called for short shutdown) function, prevent the circuit conflict;
(2) write the filling word, if the circuit contention takes place this moment, then (being called for short GHIGH_B) instruction is drawn high in statement; If the circuit contention does not take place, then need not state the GHIGH_B instruction, frame address register (being called for short FAR) is set again, frame address is provided by step 1, configuration data instruction (being called for short WCFG) is write in generation, write the number of words that will write data, write data to writing frame data input register (being called for short FDRI) again;
(3) write last frame instruction (being called for short LFRM), last, write infilled frame, fault is injected and is finished.
Check in the described step 3 that the output implementation procedure that whether makes a mistake is as follows: will press configuration information under the output result and normal condition behind the bit flipping, promptly configuration information is not compared by the result under the situation of bit flipping, if the result is inconsistent in output, wrong generation then is described, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If output is unanimity as a result, if explanation does not have wrong the generation, the logic operation not influence of this regional configuration information to target FPGA is described, not the sensitizing range.
Claims (8)
1. one kind is used for the system that locate the fpga chip sensitizing range, it is characterized in that: it comprises making FCM fault control module, fault injection module and sensitizing range detection module; Position annexation between them is: FCM fault control module will generate the required configuration information that contains failure message and export to the fault injection module, the fault injection module is injected into configuration information among the target FPGA, the signal that the sensitizing range detection module detects in real time and comparison object FPGA exports;
Described FCM fault control module is made up of software section and hardware components, it is mapped in the backup configuration information according to the position of target faults injection configuration information, and required configuration information reads back, will be wherein after negate, generate the required configuration information that contains failure message; Hardware components is that EEPROM, micro-control unit are that MCU, CPLD are that CPLD and flash memory are that FLASH forms by EEPROM (Electrically Erasable Programmable Read Only Memo), its position annexation is that EEPROM is that powering on of MCU code loads automatically, CPLD is responsible for MCU peripheral data bus, address bus are deciphered, and the configuration information of FLASH storage backup also provides required configuration information for the FCM fault control module software section;
Described fault injection module is made up of hardware MCU, CPLD and target fpga chip, its position annexation is that instruction that has been provided with and the configuration information that contains failure message input to CPLD by MCU, through CPLD through decoding after, write to target FPGA earlier instruction is set, write the configuration information that contains failure message again, finish fault at last and inject;
Described sensitizing range detection module is made up of software, output result after it injects fault and the output result who does not have fault to inject, be that output result under the normal condition compares, see whether make a mistake, if make a mistake, the positional information injected of record trouble then, this position is the sensitizing range of target fpga chip under this logical design; If there is not fault to take place, then continue to detect.
2. a kind of method that is used for fpga chip sensitizing range location of the present invention, it is characterized in that: these method concrete steps are as follows:
Step 1: according to the target fpga logic that now designs, after the product Xilinx of U.S. Xilinx company ISE 9.1i compiling, check the placement-and-routing of FPGA inside, find out target fpga chip used zone in this logical design;
Step 2: according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault injects, with the configuration information position of target FPGA one by one step-by-step overturn;
Step 3: check whether target FPGA output makes a mistake, wrong as if detecting, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If do not detect mistake, the logic operation not influence of this regional configuration information to target FPGA then is described, not the sensitizing range.
3. a kind of method that is used for location, fpga chip sensitizing range according to claim 2, it is characterized in that: the placement-and-routing of checking target FPGA inside in the described step 1 with compilation tool, the implementation procedure of finding out the zone of using in the design of target fpga logic is as follows: the target fpga logic is after Xilinx ISE 9.1i compiling, find out the zone that the design of target fpga logic is used, the type and the row in this zone that write down them are that Row and row are Column, and to calculate its main address be MJA and be MNA from the address.
4. a kind of method that is used for location, fpga chip sensitizing range according to claim 2, it is characterized in that: in the described step 2 according to the fixed regional location of step 1, be mapped to the position that is stored in configuration information in the FLASH chip, after configuration information negate wherein, target FPGA is carried out fault to be injected, the step-by-step implementation procedure of overturning is as follows one by one with the configuration information position of target FPGA: according to the fixed regional location of step 1, pass through mapping algorithm, be mapped to the position that is stored in configuration information in the FLASH chip, read required configuration information, will be wherein after negate, generate the required configuration information that contains failure message, target fpga chip configuration information is carried out fault injects, to configuration information one by one step-by-step overturn.
5. a kind of method that is used for location, fpga chip sensitizing range according to claim 2 is characterized in that: described in the step 2 target FPGA is carried out fault and inject, its concrete steps are as follows:
(1) behind the generation synchronization character, configuration register is set, it is Shutdown bit that close stance is set, and it is the shutdown function that startup is closed, and prevents the circuit conflict;
(2) write the filling word,, state that then drawing high is the GHIGH_B instruction if the circuit contention takes place this moment; If the circuit contention does not take place, then need not state the GHIGH_B instruction, it is FAR that the frame address register is set again, frame address is provided by step 1, it is WCFG that the configuration data instruction is write in generation, writes the number of words that will write data, is that FDRI writes data to writing the frame data input register again;
(3) writing the last frame instruction is LFRM, last, writes infilled frame, and fault is injected and finished.
6. a kind of method that is used for location, fpga chip sensitizing range according to claim 2, it is characterized in that: check in the described step 3 that the implementation procedure whether output make a mistake is as follows: will press configuration information under the output result and normal condition behind the bit flipping, promptly configuration information is not compared by the result under the situation of bit flipping, if the result is inconsistent in output, wrong generation then is described, illustrate that this regional configuration information is influential to the logic operation of target FPGA, this zone is the sensitizing range; If output is unanimity as a result, if explanation does not have wrong the generation, the logic operation not influence of this regional configuration information to target FPGA is described, not the sensitizing range.
7. a kind of system that is used for location, fpga chip sensitizing range according to claim 1, it is characterized in that: this EEPROM model is 24LC128; This MCU model is CY7C68013A; The EPM3512AQC208-10N that this CPLD produces for U.S. altera corp; This FLASH model is SST39VF6401.
8. a kind of system that is used for location, fpga chip sensitizing range according to claim 1 is characterized in that: this target fpga chip is the XCV300 that U.S. Xilinx company produces.
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| CN108600047A (en) * | 2018-04-04 | 2018-09-28 | 天津芯海创科技有限公司 | Serial transmission chip and SERDES circuit testing methods |
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| CN112286707A (en) * | 2020-10-26 | 2021-01-29 | 重庆智慧水务有限公司 | Fault positioning system and method for mcu abnormal operation |
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