CN101915891A - Failure detection method for digital products - Google Patents
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Abstract
The invention relates to a detection technology for digital products, in particular to a failure detection method for digital products. The invention discloses a high-efficiency failure detection method for digital products, which solves the problems of high maintenance cost and time consuming caused by difficult failure detection of digital products by the prior art. The key points of the technical scheme of the method can be summarized into the following steps of: respectively writing data into a main chip, an internal memory, a FLASH detection device and a three-bus device, reading data through an output end, and judging whether the write-in data and the read data are the same so as to further judge whether a device has a failure or not; for an IIC device, judging whether a respond bit has SDA low level to further judge whether the IIC device has a failure or not. The failure detection of the method can be accurate to a failure point, thereby improving maintenance efficiency and reducing maintenance cost simultaneously. The method is applicable to the failure detection of digital products.
Description
Technical field
The present invention relates to the detection technique of digital product, relate to the fault detection method of digital product specifically.
Background technology
Fault detect for present digital product all is to look for the trouble spot by the repairman with service experience basically, get rid of one by one, the method can also be dealt with some tangible breakdown maintenances, but also very time-consuming, efficient is extremely low, and some hidden failures are just seemed powerless.Even can't find these hidden failures, causing may be that some faults that can overcome fully also will be changed components and parts, has increased user's maintenance cost.Also there are not a kind of methodization, high efficiency failure detection method for digital products in the conventional art.
Summary of the invention
Technical matters to be solved by this invention is: be difficult for to detect at digital product fault in the conventional art, cause maintenance cost height, time-consuming problem, propose a kind of high efficiency failure detection method for digital products.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: failure detection method for digital products may further comprise the steps:
A. master chip detects: master chip powers on, system initialization, and by controlling phase-locked ring register, calibration phaselocked loop detection function is judged whether operate as normal of master chip clock, and outputs test result; Certain address writes data in ram register, reads corresponding data from this address again, judge whether write data identical with sense data, and output test result, if more than two test all normally then the master chip non-fault, otherwise master chip has fault;
B. internal memory detects: the data port test comprises:
B1. data port the 1st bit test: write data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X01 at address 0X000000, again from this address reading data, with data and the 0X01 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 1st non-fault of data port then, otherwise the 1st have fault;
B2. data port the 2nd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X02 at address 0X000000, again from this address reading data, with data and the 0X02 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 2nd non-fault of data port then, otherwise the 2nd have fault;
B3. data port the 3rd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X03 at address 0X000000, again from this address reading data, with data and the 0X03 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 3rd non-fault of data port then, otherwise the 3rd have fault;
B4. data port the 4th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X04 at address 0X000000, again from this address reading data, with data and the 0X04 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 4th non-fault of data port then, otherwise the 4th have fault;
B5. data port the 5th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X05 at address 0X000000, again from this address reading data, with data and the 0X05 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 5th non-fault of data port then, otherwise the 5th have fault;
B6. data port the 6th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X06 at address 0X000000, again from this address reading data, with data and the 0X06 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 6th non-fault of data port then, otherwise the 6th have fault;
B7. data port the 7th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X07 at address 0X000000, again from this address reading data, with data and the 0X07 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 7th non-fault of data port then, otherwise the 7th have fault;
B8. data port the 8th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X08 at address 0X000000, again from this address reading data, with data and the 0X08 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 8th non-fault of data port then, otherwise the 8th have fault;
Address wire test: to each root address wire level is that 1 o'clock corresponding stored unit, address writes 1 incremental data, from this address read-outing data, the incremental data of sense data and 1 is carried out XOR, judge whether operation result is 0, if be 0, this address wire non-fault then is not if be 0, and the data port non-fault of this address wire correspondence, then this address wire has fault;
C.FLASH detects: the data port test comprises: c1. distributes the temporary space in order to the SECTOR data among the storage FLASH in internal memory;
C2. with the SECTOR data read among the FLASH to temporary space;
C3. the data with preceding 16 bytes in the temporary space are revised as 0X00,0X01,0X00,0X02,0X00,0X04,0X00,0X08,0X00,0X10,0X00,0X20,0X00,0X40,0X00,0X80 respectively, and wipe the original SECTOR data among the FLASH;
C4. will write FLASH through amended SECTOR data in the temporary space;
C5. from FLASH, read the data of preceding 16 bytes, respectively assigned variable RDATA1, RDATA2, RDATA3, RDATA4, RDATA5, RDATA6, RDATA7, RDATA8, RDATA9, RDATA10, RDATA11, RDATA12, RDATA13, RDATA14, RDATA15, RDATA16.
C6. with 0X00 and RDATA1 XOR, operation result is assignment RDATA1 again, with 0X01 and RDATA2 XOR, operation result is assignment RDATA2 again, with RDATA1 and RDATA2 XOR, judge whether operation result is 0, if be 0, the 1st non-fault of data port then, otherwise the 1st have fault;
With 0X00 and RDATA3 XOR, operation result is assignment RDATA3 again, with 0X02 and RDATA4 XOR, operation result is assignment RDATA4 again, with RDATA3 and RDATA4 XOR, judge whether operation result is 0, if be 0, the 2nd non-fault of data port then, otherwise the 2nd have fault;
With 0X00 and RDATA5 XOR, operation result is assignment RDATA5 again, with 0X04 and RDATA6 XOR, operation result is assignment RDATA6 again, with RDATA5 and RDATA6 XOR, judge whether operation result is 0, if be 0, the 3rd non-fault of data port then, otherwise the 3rd have fault;
With 0X00 and RDATA7 XOR, operation result is assignment RDATA7 again, with 0X08 and RDATA8 XOR, operation result is assignment RDATA8 again, with RDATA7 and RDATA8 XOR, judge whether operation result is 0, if be 0, the 4th non-fault of data port then, otherwise the 4th have fault;
With 0X00 and RDATA9 XOR, operation result is assignment RDATA9 again, with 0X10 and RDATA10 XOR, operation result is assignment RDATA10 again, with RDATA9 and RDATA10 XOR, judge whether operation result is 0, if be 0, the 5th non-fault of data port then, otherwise the 5th have fault;
With 0X00 and RDATA11 XOR, operation result is assignment RDATA11 again, with 0X20 and RDATA12 XOR, operation result is assignment RDATA12 again, with RDATA11 and RDATA12 XOR, judge whether operation result is 0, if be 0, the 6th non-fault of data port then, otherwise the 6th have fault;
With 0X00 and RDATA13 XOR, operation result is assignment RDATA13 again, with 0X40 and RDATA14 XOR, operation result is assignment RDATA14 again, with RDATA13 and RDATA14 XOR, judge whether operation result is 0, if be 0, the 7th non-fault of data port then, otherwise the 7th have fault;
With 0X00 and RDATA15 XOR, operation result is assignment RDATA15 again, with 0X80 and RDATA16 XOR, operation result is assignment RDATA16 again, with RDATA15 and RDATA16 XOR, judge whether operation result is 0, if be 0, the 8th non-fault of data port then, otherwise the 8th have fault;
The d.IIC device detects: according to the communication control processor of IIC device,, judges to have or not the SDA low level in response bit to IIC device transmitting control commands, if having, and IIC device non-fault then, otherwise the IIC device has fault;
E. three bus devices detect: according to the communication control processor of three bus devices, three bus devices are write primary data, again from the output terminal sense data, judge whether write data identical with sense data, if identical, three bus device non-fault then, otherwise three bus devices have fault.
The invention has the beneficial effects as follows: fault detect is more accurate, maintenance efficiency is provided, reduce maintenance cost.
Embodiment
The present invention is directed in the conventional art digital product fault and be difficult for detecting, cause maintenance cost height, time-consuming problem, propose a kind of high efficiency failure detection method for digital products.The present invention is by writing data respectively to master chip, internal memory, FLASH detection, three bus devices, again by the output terminal sense data, whether judgement writes data identical with sense data, and then judge that device has or not fault, for the IIC device, then be by transmitting control commands, judge to have or not the SDA low level, and then judge IIC device quality in response bit.Therefore the present invention can be as accurate as the trouble spot to the detection of fault, has improved maintenance efficiency, reduces maintenance cost simultaneously.
On concrete enforcement, implementation of the present invention is as follows: the present invention solves the problems of the technologies described above the technical scheme that is adopted and is: failure detection method for digital products may further comprise the steps:
A. master chip detects: master chip powers on, system initialization, and by controlling phase-locked ring register, calibration phaselocked loop detection function is judged whether operate as normal of master chip clock, and outputs test result; Certain address writes data in ram register, reads corresponding data from this address again, judge whether write data identical with sense data, and output test result, if more than two test all normally then the master chip non-fault, otherwise master chip has fault;
B. internal memory detects: the data port test comprises:
B1. data port the 1st bit test: write data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X01 at address 0X000000, again from this address reading data, with data and the 0X01 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 1st non-fault of data port then, otherwise the 1st have fault;
B2. data port the 2nd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X02 at address 0X000000, again from this address reading data, with data and the 0X02 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 2nd non-fault of data port then, otherwise the 2nd have fault;
B3. data port the 3rd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X03 at address 0X000000, again from this address reading data, with data and the 0X03 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 3rd non-fault of data port then, otherwise the 3rd have fault;
B4. data port the 4th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X04 at address 0X000000, again from this address reading data, with data and the 0X04 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 4th non-fault of data port then, otherwise the 4th have fault;
B5. data port the 5th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X05 at address 0X000000, again from this address reading data, with data and the 0X05 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 5th non-fault of data port then, otherwise the 5th have fault;
B6. data port the 6th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X06 at address 0X000000, again from this address reading data, with data and the 0X06 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 6th non-fault of data port then, otherwise the 6th have fault;
B7. data port the 7th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X07 at address 0X000000, again from this address reading data, with data and the 0X07 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 7th non-fault of data port then, otherwise the 7th have fault;
B8. data port the 8th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X08 at address 0X000000, again from this address reading data, with data and the 0X08 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 8th non-fault of data port then, otherwise the 8th have fault;
Address wire test: to each root address wire level is that 1 o'clock corresponding stored unit, address writes 1 incremental data, from this address read-outing data, the incremental data of sense data and 1 is carried out XOR, judge whether operation result is 0, if be 0, this address wire non-fault then is not if be 0, and the data port non-fault of this address wire correspondence, then this address wire has fault;
C.FLASH detects: the data port test comprises: c1. distributes the temporary space in order to the SECTOR data among the storage FLASH in internal memory;
C2. with the SECTOR data read among the FLASH to temporary space;
C3. the data with preceding 16 bytes in the temporary space are revised as 0X00,0X01,0X00,0X02,0X00,0X04,0X00,0X08,0X00,0X10,0X00,0X20,0X00,0X40,0X00,0X80 respectively, and wipe the original SECTOR data among the FLASH;
C4. will write FLASH through amended SECTOR data in the temporary space;
C5. from FLASH, read the data of preceding 16 bytes, respectively assigned variable RDATA1, RDATA2, RDATA3, RDATA4, RDATA5, RDATA6, RDATA7, RDATA8, RDATA9, RDATA10, RDATA11, RDATA12, RDATA13, RDATA14, RDATA15, RDATA16.
C6. with 0X00 and RDATA1 XOR, operation result is assignment RDATA1 again, with 0X01 and RDATA2 XOR, operation result is assignment RDATA2 again, with RDATA1 and RDATA2 XOR, judge whether operation result is 0, if be 0, the 1st non-fault of data port then, otherwise the 1st have fault;
With 0X00 and RDATA3 XOR, operation result is assignment RDATA3 again, with 0X02 and RDATA4 XOR, operation result is assignment RDATA4 again, with RDATA3 and RDATA4 XOR, judge whether operation result is 0, if be 0, the 2nd non-fault of data port then, otherwise the 2nd have fault;
With 0X00 and RDATA5 XOR, operation result is assignment RDATA5 again, with 0X04 and RDATA6 XOR, operation result is assignment RDATA6 again, with RDATA5 and RDATA6 XOR, judge whether operation result is 0, if be 0, the 3rd non-fault of data port then, otherwise the 3rd have fault;
With 0X00 and RDATA7 XOR, operation result is assignment RDATA7 again, with 0X08 and RDATA8 XOR, operation result is assignment RDATA8 again, with RDATA7 and RDATA8 XOR, judge whether operation result is 0, if be 0, the 4th non-fault of data port then, otherwise the 4th have fault;
With 0X00 and RDATA9 XOR, operation result is assignment RDATA9 again, with 0X10 and RDATA10 XOR, operation result is assignment RDATA10 again, with RDATA9 and RDATA10 XOR, judge whether operation result is 0, if be 0, the 5th non-fault of data port then, otherwise the 5th have fault;
With 0X00 and RDATA11 XOR, operation result is assignment RDATA11 again, with 0X20 and RDATA12 XOR, operation result is assignment RDATA12 again, with RDATA11 and RDATA12 XOR, judge whether operation result is 0, if be 0, the 6th non-fault of data port then, otherwise the 6th have fault;
With 0X00 and RDATA13 XOR, operation result is assignment RDATA13 again, with 0X40 and RDATA14 XOR, operation result is assignment RDATA14 again, with RDATA13 and RDATA14 XOR, judge whether operation result is 0, if be 0, the 7th non-fault of data port then, otherwise the 7th have fault;
With 0X00 and RDATA15 XOR, operation result is assignment RDATA15 again, with 0X80 and RDATA16 XOR, operation result is assignment RDATA16 again, with RDATA15 and RDATA16 XOR, judge whether operation result is 0, if be 0, the 8th non-fault of data port then, otherwise the 8th have fault;
The d.IIC device detects: according to the communication control processor of IIC device,, judges to have or not the SDA low level in response bit to IIC device transmitting control commands, if having, and IIC device non-fault then, otherwise the IIC device has fault;
E. three bus devices detect: according to the communication control processor of three bus devices, three bus devices are write primary data, again from the output terminal sense data, judge whether write data identical with sense data, if identical, three bus device non-fault then, otherwise three bus devices have fault.
Claims (1)
1. failure detection method for digital products is characterized in that: may further comprise the steps:
A. master chip detects: master chip powers on, system initialization, and by controlling phase-locked ring register, calibration phaselocked loop detection function is judged whether operate as normal of master chip clock, and outputs test result; Certain address writes data in ram register, reads corresponding data from this address again, judge whether write data identical with sense data, and output test result, if more than two test all normally then the master chip non-fault, otherwise master chip has fault;
B. internal memory detects: the data port test comprises:
B1. data port the 1st bit test: write data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X01 at address 0X000000, again from this address reading data, with data and the 0X01 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 1st non-fault of data port then, otherwise the 1st have fault;
B2. data port the 2nd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X02 at address 0X000000, again from this address reading data, with data and the 0X02 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 2nd non-fault of data port then, otherwise the 2nd have fault;
B3. data port the 3rd bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X03 at address 0X000000, again from this address reading data, with data and the 0X03 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 3rd non-fault of data port then, otherwise the 3rd have fault;
B4. data port the 4th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X04 at address 0X000000, again from this address reading data, with data and the 0X04 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 4th non-fault of data port then, otherwise the 4th have fault;
B5. data port the 5th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X05 at address 0X000000, again from this address reading data, with data and the 0X05 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 5th non-fault of data port then, otherwise the 5th have fault;
B6. data port the 6th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X06 at address 0X000000, again from this address reading data, with data and the 0X06 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 6th non-fault of data port then, otherwise the 6th have fault;
B7. data port the 7th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X07 at address 0X000000, again from this address reading data, with data and the 0X07 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 7th non-fault of data port then, otherwise the 7th have fault;
B8. data port the 8th bit test writes data 0X00 at address 0X000000, again from this address reading data, with data and the 0X00 XOR that reads, operation result assigned variable RDATA0; Write data 0X08 at address 0X000000, again from this address reading data, with data and the 0X08 XOR that reads, among the operation result assigned variable RDATA1; With RDATA0 and RDATA1 XOR, judge whether operation result is 0, if, the 8th non-fault of data port then, otherwise the 8th have fault;
Address wire test: to each root address wire level is that 1 o'clock corresponding stored unit, address writes 1 incremental data, from this address read-outing data, the incremental data of sense data and 1 is carried out XOR, judge whether operation result is 0, if be 0, this address wire non-fault then is not if be 0, and the data port non-fault of this address wire correspondence, then this address wire has fault;
C.FLASH detects: the data port test comprises: c1. distributes the temporary space in order to the SECTOR data among the storage FLASH in internal memory;
C2. with the SECTOR data read among the FLASH to temporary space;
C3. the data with preceding 16 bytes in the temporary space are revised as 0X00,0X01,0X00,0X02,0X00,0X04,0X00,0X08,0X00,0X10,0X00,0X20,0X00,0X40,0X00,0X80 respectively, and wipe the original SECTOR data among the FLASH;
C4. will write FLASH through amended SECTOR data in the temporary space;
C5. from FLASH, read the data of preceding 16 bytes, respectively assigned variable RDATA1, RDATA2, RDATA3, RDATA4, RDATA5, RDATA6, RDATA7, RDATA8, RDATA9, RDATA10, RDATA11, RDATA12, RDATA13, RDATA14, RDATA15, RDATA16.
C6. with 0X00 and RDATA1 XOR, operation result is assignment RDATA1 again, with 0X01 and RDATA2 XOR, operation result is assignment RDATA2 again, with RDATA1 and RDATA2 XOR, judge whether operation result is 0, if be 0, the 1st non-fault of data port then, otherwise the 1st have fault;
With 0X00 and RDATA3 XOR, operation result is assignment RDATA3 again, with 0X02 and RDATA4 XOR, operation result is assignment RDATA4 again, with RDATA3 and RDATA4 XOR, judge whether operation result is 0, if be 0, the 2nd non-fault of data port then, otherwise the 2nd have fault;
With 0X00 and RDATA5 XOR, operation result is assignment RDATA5 again, with 0X04 and RDATA6 XOR, operation result is assignment RDATA6 again, with RDATA5 and RDATA6 XOR, judge whether operation result is 0, if be 0, the 3rd non-fault of data port then, otherwise the 3rd have fault;
With 0X00 and RDATA7 XOR, operation result is assignment RDATA7 again, with 0X08 and RDATA8 XOR, operation result is assignment RDATA8 again, with RDATA7 and RDATA8 XOR, judge whether operation result is 0, if be 0, the 4th non-fault of data port then, otherwise the 4th have fault;
With 0X00 and RDATA9 XOR, operation result is assignment RDATA9 again, with 0X10 and RDATA10 XOR, operation result is assignment RDATA10 again, with RDATA9 and RDATA10 XOR, judge whether operation result is 0, if be 0, the 5th non-fault of data port then, otherwise the 5th have fault;
With 0X00 and RDATA11 XOR, operation result is assignment RDATA11 again, with 0X20 and RDATA12 XOR, operation result is assignment RDATA12 again, with RDATA11 and RDATA12 XOR, judge whether operation result is 0, if be 0, the 6th non-fault of data port then, otherwise the 6th have fault;
With 0X00 and RDATA13 XOR, operation result is assignment RDATA13 again, with 0X40 and RDATA14 XOR, operation result is assignment RDATA14 again, with RDATA13 and RDATA14 XOR, judge whether operation result is 0, if be 0, the 7th non-fault of data port then, otherwise the 7th have fault;
With 0X00 and RDATA15 XOR, operation result is assignment RDATA15 again, with 0X80 and RDATA16 XOR, operation result is assignment RDATA16 again, with RDATA15 and RDATA16 XOR, judge whether operation result is 0, if be 0, the 8th non-fault of data port then, otherwise the 8th have fault;
The d.IIC device detects: according to the communication control processor of IIC device,, judges to have or not the SDA low level in response bit to IIC device transmitting control commands, if having, and IIC device non-fault then, otherwise the IIC device has fault;
E. three bus devices detect: according to the communication control processor of three bus devices, three bus devices are write primary data, again from the output terminal sense data, judge whether write data identical with sense data, if identical, three bus device non-fault then, otherwise three bus devices have fault.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967822A (en) * | 2012-12-21 | 2013-03-13 | 南京科远自动化集团股份有限公司 | Method and system for automatically detecting fault of RS-485 chip |
| CN106817161A (en) * | 2016-12-06 | 2017-06-09 | 无锡路通视信网络股份有限公司 | A kind of hardware detection method of EPON terminals |
| CN109743631A (en) * | 2019-01-16 | 2019-05-10 | 四川长虹电器股份有限公司 | Realize that TV DDR stores the system and method diagnosed automatically |
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| US20040010728A1 (en) * | 2002-05-14 | 2004-01-15 | Stmicroelectronics S.R.L. | Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol |
| CN101282494A (en) * | 2007-04-04 | 2008-10-08 | 中兴通讯股份有限公司 | Method for testing receiving performance of digital television receiving terminal |
| CN101552879A (en) * | 2009-03-13 | 2009-10-07 | 深圳市中龙通电子科技有限公司 | Digital TV receiver module |
| CN101783969A (en) * | 2009-09-30 | 2010-07-21 | 西安交通大学 | Comprehensive monitoring device of signal quality of digital television |
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| US20040010728A1 (en) * | 2002-05-14 | 2004-01-15 | Stmicroelectronics S.R.L. | Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol |
| CN101282494A (en) * | 2007-04-04 | 2008-10-08 | 中兴通讯股份有限公司 | Method for testing receiving performance of digital television receiving terminal |
| CN101552879A (en) * | 2009-03-13 | 2009-10-07 | 深圳市中龙通电子科技有限公司 | Digital TV receiver module |
| CN101783969A (en) * | 2009-09-30 | 2010-07-21 | 西安交通大学 | Comprehensive monitoring device of signal quality of digital television |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967822A (en) * | 2012-12-21 | 2013-03-13 | 南京科远自动化集团股份有限公司 | Method and system for automatically detecting fault of RS-485 chip |
| CN102967822B (en) * | 2012-12-21 | 2014-11-12 | 南京科远自动化集团股份有限公司 | Method and system for automatically detecting fault of RS-485 chip |
| CN106817161A (en) * | 2016-12-06 | 2017-06-09 | 无锡路通视信网络股份有限公司 | A kind of hardware detection method of EPON terminals |
| CN109743631A (en) * | 2019-01-16 | 2019-05-10 | 四川长虹电器股份有限公司 | Realize that TV DDR stores the system and method diagnosed automatically |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101915891B (en) | 2012-08-15 |
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