CN101908560A - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
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- CN101908560A CN101908560A CN 200910146472 CN200910146472A CN101908560A CN 101908560 A CN101908560 A CN 101908560A CN 200910146472 CN200910146472 CN 200910146472 CN 200910146472 A CN200910146472 A CN 200910146472A CN 101908560 A CN101908560 A CN 101908560A
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Abstract
The invention relates to a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a base, a grid structure, doped zones and soft doped zones. The base has a step-shaped upper surface, wherein the step-shaped upper surface comprises a first surface, a second surface and a third surface; the second surface is lower than the first surface; the third surface is connected to the first and the second surfaces; the grid structure is arranged on the first surface; the doped zones are arranged in the base at two sides of the grid structure and located below the second surface; the soft doped zones are respectively arranged in the base between the grid structure and the doped zones, and each soft doped zone comprises a first part and a second part which are connected to each other, wherein the first part is arranged below the second surface and the second part is arranged below the third surface. The semiconductor element employs the inclined and bent soft doped zones as a source electrode and a drain electrode for extending, beneficial to lightening hot carrier effect without reducing dopant concentration of the soft doped zones, and capable of decreasing leakage current of the drain electrode caused by the grid and overlap capacitance between the grid and the drain electrode.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) electric crystal and manufacture method thereof.
Background technology
Along with the fast development of semiconductor fabrication process technology, in order to promote component speeds and usefulness, the entire circuit size of component must constantly be dwindled, and the integrated level of element also must promote continuously.The element integration is being required under the more and more higher trend, must consider as leakage current, hot carrier effect (hot carrier effect) or short-channel effect (short channel effect, the change of element characteristic such as SCE) has a strong impact on to avoid the reliability of integrated circuit and usefulness caused.
With the metal-oxide semiconductor (MOS) electric crystal is example, and Fig. 1 is the generalized section that has known a kind of metal-oxide semiconductor (MOS) electric crystal now.As shown in Figure 1, grid structure 102 is configured in the substrate 100, and clearance wall 104 is configured on the sidewall of grid structure 102.The source drain extension (sourcedrain extension, skew clearance wall SDE) (offset spacer) 106 is formed between grid structure 102 and the clearance wall 104, and between clearance wall 104 and substrate 100.Source area 108a and drain region 108b are configured in respectively in the substrate 100 in clearance wall 104 outsides.Source electrode extension area 110a and drain electrode extension area 110b are configured in respectively in the substrate 100 of clearance wall 104 belows.That is to say that source electrode extension area 110a is between source area 108a and grid structure 102, and drain electrode extension area 110b is between drain region 108b and grid structure 102.Also dispose self-aligned metal silicate (salicide) 112 on grid structure 102, source area 108a and the drain region 108b.
Consider that source electrode extension area 110a and the concentration of drain electrode extension area 110b can influence element efficiency, source electrode extension area 110a must enough weigh to guarantee element efficiency and quality with the dopant dose of drain electrode extension area 110b.Yet heavily doped source electrode extension area 110a can cause very high gate induced drain leakage stream with drain electrode extension area 110b, and (gate-induced drain leakage is GIDL) with serious hot carrier effect.Though can slow down gate induced drain leakage stream and hot carrier effect by reducing the dopant dose that source drain extends, can make overlap capacitance (gate-drain overlap capacitance) between sheet resistor (sheet resistance) and grid drain electrode rise and have a strong impact on element efficiency.Moreover, clearance wall 104 must enough thick dopant diffusion of source area 108a and drain region 108b that just can prevent arrive source electrode extension area 110a and drain electrode extension area 110b, and must keep enough spaces and make the source drain diffusion, with the generation of abundant inhibition electrical breakdown (punch through) with short-channel effect.In addition, when being formed with stressor layers in the substrate 100, thick clearance wall 104 tends to cause stressor layers away from channel region, thereby reduces the lifting effect of stressor layers to carrier transport factor.
This shows that above-mentioned conventional semiconductor element and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, how effectively to guarantee the element reliability of semiconductor element, and the element efficiency of lifting semiconductor element, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new semiconductor element and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
Main purpose of the present invention is, overcomes the defective that the conventional semiconductor element exists, and a kind of new semiconductor element is provided, and technical problem to be solved is to make its element efficiency can obtain to promote, and is very suitable for practicality.
Another object of the present invention is to, a kind of manufacture method of new semiconductor element is provided, technical problem to be solved is to form and crooked source drain extends (SDE), thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the semiconductor element that the present invention proposes, it comprises substrate, grid structure, doped region and light doping section.Substrate has a scalariform upper surface, and wherein the scalariform upper surface comprises first surface, second surface and the 3rd surface.Second surface is lower than first surface.The 3rd surface connects first surface and second surface.Grid structure is disposed on the first surface.Doped region is disposed in the grid structure substrate on two sides, and is positioned under the second surface.Light doping section is disposed at respectively in the substrate between grid structure and the doped region.Each light doping section comprises interconnective first and second portion.First is disposed under the second surface, and second portion is disposed at the 3rd surface down.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In one embodiment of this invention, the 3rd above-mentioned surface tilt is in first surface, and the bearing of trend of first surface and the 3rd surperficial formed angle are between 45 ° to 60 °.
In one embodiment of this invention, above-mentioned first surface is parallel to second surface in fact.
In one embodiment of this invention, above-mentioned first surface and the difference in height between the second surface between
Extremely
Between, and the level interval between first surface and the second surface between
Extremely
Between.
In one embodiment of this invention, the length of the first of above-mentioned each light doping section between
Extremely
Between, and the length of second portion between
Extremely
Between.
In one embodiment of this invention, semiconductor element more comprises clearance wall, is disposed on the sidewall of grid structure, and is positioned on the light doping section.The thickness of clearance wall for example be between
Extremely
Between.The material of clearance wall can be the combination of oxide, nitrogen oxide (oxynitride), nitride-oxide (nitrided oxide), nitride or above-mentioned material.
In one embodiment of this invention, semiconductor element more comprises the self-aligned metal silicate layer, is disposed on the grid structure to reach on the doped region.
In one embodiment of this invention, semiconductor element more comprises stressor layers, is disposed in the substrate.Stressor layers for example is that compression stress or the tensile stress nitride film to channel region can be provided.
In one embodiment of this invention, semiconductor element more comprises the wellblock, is disposed in the substrate, and wherein doped region and light doping section are arranged in this wellblock.
In one embodiment of this invention, semiconductor element more comprises a bag shape (ring-type) implantation region, be disposed in the substrate under the grid structure, and each bag shape (ring-type) implantation region is respectively adjacent to each doped region.Bag shape (ring-type) implantation region for example is local (localized) bag shape (ring-type) implantation region or compound (multiple) bag shape (ring-type) implantation region.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of the semiconductor element that proposes according to the present invention.At first, provide a substrate, and in substrate, form grid structure.With the grid structure is that mask removes the part substrate to form the scalariform upper surface, and wherein the scalariform upper surface comprises first surface, second surface and the 3rd surface.Second surface is lower than first surface.The 3rd surface connects first surface and second surface.In the grid structure substrate on two sides, form light doping section.Each light doping section comprises interconnective first and second portion.First is disposed under the second surface, and second portion is disposed at the 3rd surface down.Form doped region in substrate, each doped region is positioned under the second surface and respectively in abutting connection with light doping section.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In one embodiment of this invention, the 3rd above-mentioned surface tilt is in first surface, and the bearing of trend of first surface and the 3rd surperficial formed angle are between 45 ° to 60 °.
In one embodiment of this invention, above-mentioned first surface is parallel to second surface in fact.
In one embodiment of this invention, above-mentioned first surface and the difference in height between the second surface between
Extremely
Between, and the level interval between first surface and the second surface between
Extremely
Between.
In one embodiment of this invention, the length of the first of above-mentioned each light doping section between
Extremely
Between, and the length of second portion between
Extremely
Between.
In one embodiment of this invention, above-mentioned method more is included on the sidewall of grid structure with on the light doping section and forms first clearance wall.The thickness of first clearance wall for example be between
Extremely
Between.
In one embodiment of this invention, the method for above-mentioned formation first clearance wall comprises the following steps.At first, in substrate, form the spacer material layer.Then, form second clearance wall on the sidewall of grid structure, wherein second clearance wall covers the part spacer material layer that is positioned on the light doping section.With second clearance wall is that mask removes part spacer material layer, then removes second clearance wall again.
In one embodiment of this invention, after removing part spacer material layer, be that mask forms doped region with second clearance wall.After forming the spacer material layer and before forming second clearance wall, form light doping section; Perhaps, after removing second clearance wall, form light doping section.
In one embodiment of this invention, after forming first clearance wall, form light doping section and doped region.Light doping section and doped region for example are to utilize unitary system fabrication technique or two step manufacturing process and form.
In one embodiment of this invention, above-mentioned method more be included on the grid structure and doped region on form the self-aligned metal silicate layer.
In one embodiment of this invention, above-mentioned method more is included in and forms stressor layers in the substrate, and it for example is that compression stress or the tensile stress nitride film to channel region can be provided.
In one embodiment of this invention, before forming grid structure, more be included in and form the wellblock in the substrate, wherein doped region and light doping section are formed in the wellblock.
In one embodiment of this invention, above-mentioned method more is included in shape pouch (ring-type) implantation region in the substrate under the grid structure, and each bag shape (ring-type) implantation region is respectively adjacent to each doped region.Bag shape (ring-type) implantation region for example is local bag shape (ring-type) implantation region or complex pocket shape (ring-type) implantation region.Above-mentioned bag shape (ring-type) implantation region can be after forming the scalariform upper surface and form, or after forming light doping section and form, or after formation spacer material layer and before the formation light doping section and form.
By technique scheme, semiconductor element of the present invention and manufacture method thereof have following advantage and beneficial effect at least:
Based on above-mentioned, semiconductor element of the present invention has and crooked light doping section extends (SDE) as source drain, can help to alleviate hot carrier effect, and need not reduce the dopant concentration of light doping section.Moreover, because light doping section has and crooked profile, therefore can reduce the overlap capacitance between gate induced drain leakage stream (GIDL) and grid drain electrode.
In addition, the manufacture method of semiconductor element of the present invention forms and crooked light doping section, so the diffusion of light doping section can not be subjected to the doped region diffusion influence, and can form thinner clearance wall in this semiconductor component structure.Thus, utilize to form thinner clearance wall, thin clearance wall cooperates oblique just etched substrate can allow stressor layers more near channel region, and makes stressor layers strengthen electron mobility more efficiently, makes element efficiency can obtain further improvement.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the generalized section that has known a kind of metal-oxide semiconductor (MOS) electric crystal now.
Fig. 2 is the generalized section according to a kind of semiconductor element of one embodiment of the invention.
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to a kind of semiconductor element of one embodiment of the invention.
Fig. 4 A to Fig. 4 C is the manufacturing process generalized section according to a kind of semiconductor element of another embodiment of the present invention.
Fig. 5 A to Fig. 5 C is the manufacturing process generalized section according to a kind of semiconductor element of another embodiment of the present invention.
It is according to the existing known NMOS and the pairing transverse electric field distribution curve chart of NMOS diverse location in being parallel to the channel region of first surface of experimental example of the present invention that Fig. 6 illustrates.
100,200,300: substrate 102,204,310: grid structure
104,210,312a, 318,402,404,502,504: clearance wall
106: skew clearance wall 108a: source area
108b: drain region 110a: source electrode extension area
110b: drain electrode extension area 112: self-aligned metal silicate
201,301: scalariform upper surface 201a, 301a: first surface
201b, 301b: second surface 201c, 301c: the 3rd surface
202,302: wellblock 204a: grid
204b: gate dielectric layer
206,322,408,509,509a, 509b: doped region
208,316,412,508: light doping section
208a, 316a, 412a, 508a: first
208b, 316b, 412b, 508b: second portion
210a: thickness
212,324,416,510: the self-aligned metal silicate layer
214,326,418,512: stressor layers
304: dielectric layer 306: conductor layer
308: patterning hard mask layer 312: the spacer material layer
314,320,406,410,506,507: implant manufacturing process
D
1: difference in height D
2: level interval
L
1, L
2: length ψ: angle
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the semiconductor element that foundation the present invention is proposed and embodiment, structure, feature and the effect thereof of manufacture method thereof, describe in detail as after.
Fig. 2 is the generalized section according to a kind of semiconductor element of one embodiment of the invention.It is noted that following embodiment represents first conductivity type with the P type, and represents second conductivity type with the N type, but the present invention is not as limit.Have the knack of this skill person and should be appreciated that, the present invention can also be replaced as the N type with first conductivity type, and second conductivity type is replaced as the P type to form semiconductor element.
Please refer to shown in Figure 2ly, semiconductor element of the present invention comprises substrate 200, grid structure 204, doped region 206 and light doping section 208 at least.Substrate 200 with first conductivity type is provided, and it can be to cover P type semiconductor (semiconductor-on-insulator, SOI) substrate on crystal silicon (epi-silicon) substrate of heap of stone of P type silicon base, P type or the insulating barrier.Substrate 200 for example is to have scalariform upper surface 201.Scalariform upper surface 201 comprises first surface 201a, second surface 201b and the 3rd surperficial 201c, and wherein the 3rd surperficial 201c connects first surface 201a and second surface 201b.The second surface 201b that is lower than first surface 201a can be parallel to first surface 201a in fact.When first surface 201a and second surface 201b were essentially tabular surface, the 3rd surperficial 201c tiltable was in first surface 201a.That is to say that the 3rd surperficial 201c is the inclined-plane between first surface 201a and second surface 201b, wherein the upper limb on inclined-plane connects first surface 201a, and the lower edge on inclined-plane connects second surface 201b.In one embodiment, the difference in height D between first surface 201a and the second surface 201b
1Between
Extremely
Between.In one embodiment, the level interval D between first surface 201a and the second surface 201b
2Between
Extremely
Between.In one embodiment, the bearing of trend of first surface 201a and the formed angle ψ of the 3rd surperficial 201c are between 45 ° to 60 °.
In addition, 200 also dispose the wellblock 202 with first conductivity type in the substrate, and it for example is p type wells district (P-well).In one embodiment, part (localized) bag shape (ring-type) implantation region or compound (multiple) bag shape (ring-type) implantation region with first conductivity type (as the P type) more can be disposed in the wellblock 202.Local bag shape (ring-type) implantation region or complex pocket shape (ring-type) implantation region for example are the belows that is disposed at grid structure 204, and respectively adjacent to each doped region 206.Wellblock 202 for example is only to have super fall back suddenly (super steep retrograde, SSR) well.In another embodiment, wellblock 202 also can be to have combining of super fall back suddenly well and bag shape (ring-type) implantation region.
The doped region 206 of second conductivity type is disposed in grid structure 204 substrate on two sides 200.Doped region 206 is disposed under the second surface 201b.Doped region 206 can be the N+ doped region, with respectively as the source electrode and the drain electrode of semiconductor element.
The light doping section 208 of second conductivity type is disposed in the substrate 200 between grid structure 204 and the doped region 206.The light doping section 208 that has the identical conduction kenel with doped region 206 can be electrically connected to corresponding doped region 206 respectively in the both sides of grid structure 204, thereby extends (SDE) as source drain.Each light doping section 208 comprises interconnected 208a of first and second portion 208b.The 208a of first is disposed under the second surface 201b, and adjacent to the 3rd surperficial 201c.Second portion 208b is disposed under the 3rd surperficial 201c.In one embodiment, second portion 208b also can extend in the zone of first surface 201a below sometimes a little.Because the aggregate level length of each light doping section 208 can depend on the length of grid 204a, therefore when the length of grid 204a was dwindled, the distributed areas of light doping section 208 can be shortened.Being about 90nm with the length of grid 204a is example, the horizontal distribution of each light doping section 208 approximately between
Extremely
Between.In one embodiment, the length L of the 208a of first
1Between
Extremely
Between.In one embodiment, the length L of second portion 208b
2Between
Extremely
Between.It should be noted that because the 3rd surperficial 201c is the inclined plane, so the inclination angle of each light doping section 208 is controlled in 45 ° to 60 ° the scope, with the breakdown characteristics (punch through characteristic) of holding element.
Generally speaking, transverse electric field (lateral electric field) only depends on the surface doping characteristic of light doping section 208.Constituted to tilt and crooked profile because light doping section 208 has by 208a of first and second portion 208b, so the 208a of first can provide the space of reservation to doped region 206 diffusions.In the structure of this semiconductor element, the surface doping of the fraction light doping section 208 under first surface 201a is very light, therefore can not reduce light doping section 208 dopant doses and not influence under the situation of light doping section 208 resistance, and the overlap capacitance and the gate induced drain leakage that effectively alleviate between hot carrier effect, grid drain electrode flow (GIDL).In detail, because the doping content in the overlapping region between grid drain electrode can reduce significantly, therefore the overlap capacitance between hot carrier effect, gate induced drain leakage stream (GIDL) and grid drain electrode also can reduce.Moreover diffusion and the diffusion of doped region 206 of light doping section 208 below grid structure 204 is irrelevant, thereby the doping content of doped region 206 can enough weigh and deeply enough.
In addition, semiconductor element of the present invention also can comprise clearance wall 210, self-aligned metal silicate layer 212 and stressor layers 214.Clearance wall 210 is disposed on the sidewall of grid structure 204, and is positioned on the light doping section 208.Clearance wall 210 for example has crooked external form, and the corresponding profile that meets grid structure 204 sidewalls, the 3rd surperficial 201c and a part of second surface 201b.In other words, clearance wall 210 can be hedged off from the outer world the sidewall of grid structure 204, and covers the part substrate 200 that is formed with light doping section 208.The material of clearance wall 210 comprises the combination of oxide, nitrogen oxide (oxynitride), nitride-oxide (nitrided oxide), nitride or above-mentioned material.In one embodiment, the thickness 210a of clearance wall 210 approximately between
Extremely
Between.
Self-aligned metal silicate layer 212 is disposed on the grid structure 204 and on the doped region 206.The material of self-aligned metal silicate layer 212 for example is nickle silicide (NiSi
x) or cobalt silicide (CoSi
x).In one embodiment, can also form contact hole (not illustrating) on the grid structure 204 with on the doped region 206, owing to dispose self-aligned metal silicate layer 212, and make the resistance on the interface to reduce.
Stressor layers 214 be disposed on the grid structure 204 with substrate 200 on.Stressor layers 214 can be that compression stress or the tensile stress nitride film to channel region (be channel region, below all be called channel region) can be provided.In one embodiment, can cause that the nitride film of tensile stress is to be used for NMOS at channel region, and can cause that the nitride film of compression stress is to be used for PMOS at channel region.For the technology node of 90nm, the thickness of stressor layers 214 for example can drop on
Extremely
Scope in.Generally speaking, the thickness 210a of clearance wall 210 is one of main keys that influence short-channel effect.Be thinned to by the thickness 210a that makes clearance wall 210
Extremely
Scope in, shortening the distance between stressor layers 214 and the channel region, thereby can improve the element efficiency that stress layer 214 is promoted.
What specify is, because light doping section 208 diffusions below grid structure 204 are irrelevant with the diffusion of doped region 206, so the doping content of doped region 206 can enough weigh and deeply enough, and helps the formation of self-aligned metal silicate layer 212.In addition, because having the 208a of first, light doping section 208 can make clearance wall 210 attenuation.Because thin clearance wall 210 and substrate 200 with concave face, help to make the stressor layers 214 can be more near the channel region that is positioned under the grid structure 204, therefore can promote carrier transport factor and promote the improvement of element efficiency.
Next will utilize generalized section to go on to say the manufacture method of the semiconductor element of the embodiment of the invention.The flow process of the following stated only is in order to describe method of the present invention in detail in the making flow process that forms semiconductor element as shown in Figure 2, so that those who familiarize themselves with the technology can implement according to this, but is not in order to limit scope of the present invention.
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to a kind of semiconductor element of one embodiment of the invention.
Please refer to shown in Fig. 3 A, the substrate 300 with first conductivity type is provided, it can be to cover P type semiconductor (SOI) substrate on crystal silicon substrate of heap of stone of P type silicon base, P type or the insulating barrier.The wellblock 302 of first conductivity type is formed in the substrate 300, and wherein wellblock 302 for example is the p type wells district.In one embodiment, wellblock 302 can be the profile that forms super (SSR) well that falls back suddenly.
Please refer to shown in Fig. 3 B, in substrate 300, form dielectric layer 304, conductor layer 306 and patterning hard mask layer 308 in regular turn.The material of dielectric layer 304 can be oxide, nitride-oxide (nitrided oxide), nitrogen oxide (oxynitride) or high-k (high-K) material, and wherein high dielectric constant material for example is hafnium (Hf), titanium oxide (TiO
x), hafnium oxide (HfO
x), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), aluminium oxide (Al
2O
3).The material of conductor layer 306 can be metal, doped polycrystalline silicon, SiGe (silicon-germanium) or the combination of polysilicon and metal.Utilize patterning hard mask layer 308 to be mask, remove part dielectric layer 304 and segment conductor layer 306, in substrate 300, to define grid structure 310.The dielectric layer 304 of patterning is as gate dielectric layer, and the conductor layer 306 of patterning is as grid.In one embodiment, the length of grid can be 90nm or other littler sizes, and the effective oxide thickness (EOT) of gate dielectric layer can be approximately between
Extremely
Between, in case the generation of leak-stopping electric current.
Afterwards, remove the substrate 300 of a part, to form scalariform upper surface 301.The method that removes part substrate 300 for example is as mask and the silicon etching manufacturing process that tilts (sloped silicon etching process) with grid structure 310.In one embodiment, inclination silicon etching manufacturing process (be processing procedure, this paper all is called manufacturing process) can be to use the wet etching that suitable prescription carried out that comprises multiple acids.In another embodiment, inclination silicon etching manufacturing process also can be to use and comprise multiple gases (as CHF
3, CF
4, Ar, O
2) the plasma etching that carries out of appropriate combination.Formed scalariform upper surface 301 comprises first surface 301a, second surface 301b and the 3rd surperficial 301c, and wherein the 3rd surperficial 301c connects first surface 301a and second surface 301b.First surface 301a for example is the position corresponding to grid structure 310.The second surface 301b that is lower than first surface 301a can be parallel to first surface 301a in fact.When first surface 301a and second surface 301b were essentially tabular surface, the 3rd surperficial 301c tiltable was in first surface 301a.That is to say that the 3rd surperficial 301c is the inclined-plane between first surface 301a and second surface 301b, wherein the upper limb on inclined-plane connects first surface 301a, and the lower edge on inclined-plane connects second surface 301b.In one embodiment, the difference in height D between first surface 301a and the second surface 301b
1Between
Extremely
Between.In one embodiment, the level interval D between first surface 301a and the second surface 301b
2Between
Extremely
Between.In one embodiment, the bearing of trend of first surface 301a and the formed angle ψ of the 3rd surperficial 301c are between 45 ° to 60 °.
Please refer to shown in Fig. 3 C, remove patterning hard mask layer 308.Then, in substrate 300, form spacer material layer 312.Spacer material layer 312 for example is overlies gate structure 310, second surface 301b and the 3rd surperficial 301c.In one embodiment, the thickness of spacer material layer 312 approximately between
Extremely
Between.The material of spacer material layer 312 comprises the combination of oxide, nitrogen oxide (oxynitride), nitride-oxide (nitrided oxide), nitride or above-mentioned material.The method that forms spacer material layer 312 can be to utilize deposition manufacturing process or Rapid Thermal manufacturing process (rapid thermal process, RTP), the Rapid Thermal manufacturing process for example is that situ steam generates (in-situ steam generation, ISSG) oxidation manufacturing process.
Thereupon, implant manufacturing process 314, to form the light doping section 316 of second conductivity type (N type) in grid structure 310 substrate on two sides 300.Light doping section 316 for example is the knot that extends (SDE) in substrate 300 as source drain.Light doping section 316 can be to utilize vertical implantation to form, or utilizes the inclination angle implantation to form, and uses low-yield to form shallow source drain extension (SDE) junction depth (junction depth) and to use enough heavy prescription amounts to reduce sheet resistor.In one embodiment, the thickness that is about 90nm and spacer material layer 312 when grid length is about
The time, can use energy and the 5e of 10-15KeV
14-3e
15Cm
-2Dosage implant manufacturing process 314, and can utilize 5 °-10 ° inclination angle to implant admixture.In one embodiment, more reduce and the thickness of spacer material layer 312 is thinned to when component size
The time, the energy of implanting manufacturing process 314 can be reduced to 2-7KeV.
It should be noted that it also can is after forming grid structure 310 and before forming spacer material layer 312, to implant manufacturing process 314.Technology node with 90nm is an example, can use energy and the 5e of 2-5KeV
14-1e
15Cm
-2Dosage implant manufacturing process 314, and can utilize 0 ° inclination angle vertically to implant admixture.When component size is more reduced, need lower energy to implant manufacturing process 314, can use the energy of about 0.1-1KeV.
In addition, in one embodiment, after forming scalariform upper surface 301 or after forming light doping section 316, can also in wellblock 302, form local bag shape (ring-type) implantation region or complex pocket shape (ring-type) implantation region of first conductivity type (as the P type).In another embodiment, also can be after forming spacer material layer 312, to reach to form before the light doping section 316 shape pouch (ring-type) implantation region in wellblock 302.That is to say that wellblock 302 can be only to have super (SSR) well that falls back suddenly, or have combining of super fall back suddenly well and bag shape (ring-type) implantation region.Local bag shape (ring-type) implantation region or complex pocket shape (ring-type) implantation region for example are the belows that is formed at grid structure 310 respectively, and preformed each doped region after being adjacent to respectively.Above-mentioned bag shape (ring-type) district can utilize vertical implantation to form, or with 7 °-45 ° inclination angle implant formed.
Please refer to shown in Fig. 3 D, on the sidewall of grid structure 310, form clearance wall 318.Clearance wall 318 covers the spacer material layer 312 of a part, to define follow-up preformed source area and drain region.Remove the spacer material layer 312 of part as mask with clearance wall 318.Remaining spacer material layer 312 can form clearance wall 312a, and each clearance wall 312a is disposed at respectively between the sidewall of clearance wall 318 and grid structure 310.Implant manufacturing process 320, in the outside of clearance wall 318 substrate 300, to form the doped region 322 of second conductivity type respectively.Doped region 322 is formed under the second surface 301b, and electrically connects light doping section 316.Doped region 322 for example is the N+ doped region, with respectively as source area and drain region.After forming clearance wall 318, can use to be higher than the energy of implanting manufacturing process 314 and to implant manufacturing process 320 in the mode of vertical implantation.Dark and heavy doped region 322 can help to reduce sheet resistor and make that follow-up metal silication manufacturing process is easier carries out.In one embodiment, for the technology node of 90nm, can use energy and the 1e of 10-20KeV
15-3e
15Cm
-2Dosage implant manufacturing process 320.
Please refer to shown in Fig. 3 E, can also carry out the tempering manufacturing process with the activation admixture.In the technology node of 90nm, the tempering manufacturing process can be general immersion (soak) tempering manufacturing process or spike (spike) tempering manufacturing process.At the littler element of size, can also use other advanced tempering technology, as quick (flash) or laser (laser) tempering manufacturing process.
Afterwards, remove clearance wall 318, and forming self-aligned metal silicate layer 324 on the grid structure 310 with on the doped region 322.The material of self-aligned metal silicate layer 324 can be nickle silicide (NiSi
x) or cobalt silicide (CoSi
x).In one embodiment, can before or after removing clearance wall 318, form self-aligned metal silicate layer 324.Then, in substrate 300, form stressor layers 326, to finish semiconductor element of the present invention.Stressor layers 326 can be that compression stress or the tensile stress nitride film to channel region can be provided.In this embodiment, stressor layers 326 can cause tensile stress at the channel region of NMOS.In another embodiment, can cause that the nitride film of compression stress can be used as the stressor layers of PMOS at channel region.At the technology node of 90nm, the thickness of stressor layers 326 is for example between about
Extremely
Between.It is noted that the formation method of members such as above-mentioned self-aligned metal silicate layer 324, stressor layers 326 and the formation personnel of technical field are in proper order for this reason known, so do not give unnecessary details its details in this.
Please referring again to shown in Fig. 3 E, each light doping section 316 that is disposed at respectively in the substrate 300 between grid structure 310 and the doped region 322 comprises 316a of first and the second portion 316b that links to each other, and tilts and crooked profile to form.The 316a of first is disposed under the second surface 301b, and adjacent to the 3rd surperficial 301c.Second portion 316b is disposed under the 3rd surperficial 301c, and second portion 316b can also have a fraction of zone to extend under the first surface 301a.When grid length was about 90nm, the horizontal distribution of each light doping section 316 for example was between about
Extremely
Between.In one embodiment, the length L of the 316a of first
1Between
Extremely
Between.In one embodiment, the length L of second portion 316b
2Between
Extremely
Between.It should be noted that because the 3rd surperficial 301c is the inclined plane, so the inclination angle of each light doping section 316 is controlled in 45 ° to 60 ° the scope, with the breakdown characteristics of holding element.Inclination and crooked light doping section 316 have lighter doping content on the surface, therefore can alleviate hot carrier effect, and under the situation that does not increase source drain extension (SDE) resistance, reduce the overlap capacitance between gate induced drain leakage stream (GIDL) and grid drain electrode.In the process of tempering manufacturing process, because light doping section 316 has and crooked profile, therefore the diffusion of light doping section 316 below grid structure 310 is irrelevant with the diffusion of doped region 322, and the doping content of doped region 322 can enough weigh and reach deeply in order to carrying out the metal silication manufacturing process.And because clearance wall 312a is thin and comply with the external form of substrate 300 and bending, so stressor layers 326 understands more close channel region, and effective lift elements usefulness.
Fig. 4 A to Fig. 4 C is the manufacturing process generalized section according to a kind of semiconductor element of another embodiment of the present invention.It is noted that the manufacturing process shown in Fig. 4 A to Fig. 4 C is the step behind the hookup 3B.In Fig. 4 A to Fig. 4 C, the member identical with Fig. 3 B then uses identical label and omits its explanation.
Please refer to shown in Fig. 4 A, remove patterning hard mask layer 308.Then, in the sidewall of grid structure 310 and part substrate 300, form clearance wall 402 and clearance wall 404.Crooked clearance wall 402 can utilize disposable type (disposable) clearance wall 404 to form.Clearance wall 402 is configured in respectively between the sidewall of clearance wall 404 and grid structure 310.Clearance wall 402 covers the 3rd surperficial 301c and cover part second surface 301b with clearance wall 404, therefore can utilize clearance wall 402 and clearance wall 404 to define follow-up preformed source area and drain region.
Then, implant manufacturing process 406, in the outside of clearance wall 404 substrate 300, to form the doped region 408 of second conductivity type respectively.The doped region 408 that is formed under the second surface 301b for example is the N+ doped region, with respectively as source area and drain region.Can use the energy that is higher than formation source drain extension (SDE) to implant manufacturing process 406 in the mode of vertical implantation.In one embodiment, for the technology node of 90nm, can use energy and the 1e of 10-20KeV
15-3e
15Cm
-2Dosage implant manufacturing process 406.
Please refer to shown in Fig. 4 B, remove clearance wall 404.Implant manufacturing process 410, in grid structure 310 substrate on two sides 300, to form the light doping section 412 of second conductivity type (N type).Light doping section 412 can be to utilize the vertical institute that implants to form, or uses low-yield and utilize the inclination angle implantation to form.In one embodiment, the thickness that is about 90nm and clearance wall 402 when grid length is about
The time, can use energy and the 5e of 10-15KeV
14-3e
15Cm
-2Dosage implant manufacturing process 410, and can utilize 5 °-10 ° inclination angle to implant admixture.In one embodiment, more reduce and the thickness of clearance wall 402 is thinned to when component size
The time, the energy of implanting manufacturing process 410 can be reduced to 2-7KeV.
Please refer to shown in Fig. 4 C, can also carry out the tempering manufacturing process with the activation admixture.Afterwards, forming self-aligned metal silicate layer 416 on the grid structure 310 with on the doped region 408.Then, in substrate 300, form stressor layers 418, to finish semiconductor element of the present invention.Shown in Fig. 4 C, each light doping section 412 that is configured in respectively in the substrate 300 between grid structure 310 and the doped region 408 comprises 412a of first and second portion 412b, and wherein the 412a of first connects second portion 412b.The 412a of first is disposed under the second surface 301b, and adjacent to the 3rd surperficial 301c.Second portion 412b is disposed under the 3rd surperficial 301c, and second portion 412b can also have a fraction of zone to extend under the first surface 301a.When the length of grid was about 90nm, the horizontal distribution of each light doping section 412 can be between about
Extremely
Between.In one embodiment, the length L of the 412a of first
1Between
Extremely
Between.In one embodiment, the length L of second portion 412b
2Between
Extremely
Between.What specify is, because the 3rd surperficial 301c is the inclined plane, so the inclination angle of each light doping section 412 can be controlled in 45 ° to 60 ° the scope, with the breakdown characteristics of holding element.
Fig. 5 A to Fig. 5 C is the manufacturing process generalized section according to a kind of semiconductor element of another embodiment of the present invention.It is noted that the manufacturing process shown in Fig. 5 A to Fig. 5 C is the step behind the hookup 3B.In Fig. 5 A to Fig. 5 C, the member identical with Fig. 3 B then uses identical label and omits its explanation.
Please refer to shown in Fig. 5 A, remove patterning hard mask layer 308.Then, in the sidewall of grid structure 310 and part substrate 300, form clearance wall 502 and clearance wall 504.Clearance wall 502 with crooked external form for example is to form by disposable type (disposable) clearance wall 504.Clearance wall 502 is disposed at respectively between the sidewall of clearance wall 504 and grid structure 310.Clearance wall 502 covers the second surface 301b of the 3rd surperficial 301c and cover part with clearance wall 504, extends (SDE), source area and drain region and can be used for defining follow-up preformed source drain.
Please refer to shown in Fig. 5 B-1, remove clearance wall 504.Implant manufacturing process 506, in grid structure 310 substrate on two sides 300, to form the light doping section 508 and doped region 509a of second conductivity type (N type).Light doping section 508 for example is the below that is formed at clearance wall 502, and doped region 509a for example is the outside that is formed at clearance wall 502.
Please refer to shown in Fig. 5 B-2, in another embodiment, more can use the low-yield manufacturing process 507 of optionally implanting,, and make source drain (SD) diffusion region darker with the doped region 509b of formation second conductivity type (N type) in the both sides of grid structure 310 substrate 300.Doped region 509b for example is formed in the scope of doped region 509a.In this explanation is that the present invention does not impose any restrictions with the sequencing of implanting manufacturing process 507 implanting manufacturing process 506, that is the above-mentioned manufacturing process 506 of implanting can be exchanged with the order of implanting manufacturing process 507.
Hold that above-mentioned, shallow source drain extends (SDE) district and source drain (SD) diffusion region can be to use suitable energy to carry out single implantation manufacturing process and form simultaneously, or carry out implanting for two times manufacturing process 300 twice admixture is implanted substrate.In one embodiment, shown in Fig. 5 B-1, single implantation manufacturing process with the process that forms light doping section 508 and doped region 509a simultaneously in because clearance wall 502 covers in the substrate 300, light doping section 508 can form shallow junctions (shallow junction); Because covering of wall 502 very close to each other, doped region 509a can form darker knot.Be about with the technology node of 90nm and the thickness of clearance wall 502
Be example, can use energy and the 1e of about 15KeV
15-3e
15Cm
-2Dosage carry out single implantation manufacturing process, and use 5 °-10 ° inclination angle to implant admixture, just can form required knot profile simultaneously thus.
In one embodiment, implant in the process of manufacturing process with formation light doping section 508 and doped region 509a, 509b, can form light doping section 508 and doped region 509a (shown in Fig. 5 B-1) simultaneously by implanting manufacturing process 506 in two steps; And because the screening effect of clearance wall 502, using lower energy to implant 507 of manufacturing process in addition can increase the doping content of doped region 509b (shown in Fig. 5 B-2).Be about with the technology node of 90nm and the thickness of clearance wall 502
Be example, can use energy and the 1e of about 15KeV
15-3e
15Cm
-2Dosage implant manufacturing process 506 and form light doping section 508 and doped region 509a simultaneously, wherein use 5 °-10 ° inclination angle to implant admixture.Be same as under the above-mentioned condition, can using energy and the 1e of about 5-10KeV
15-3e
15Cm
-2Dosage implant manufacturing process 507, to increase the doping content of doped region 509b.
Please refer to shown in Fig. 5 C, after implanting manufacturing process 506 or implanting after the manufacturing process 507, can also carry out the tempering manufacturing process with the activation admixture, thereby form doped region 509.Afterwards, forming self-aligned metal silicate layer 510 on the grid structure 310 with on the doped region 509.Then, in substrate 300, form stressor layers 512, to finish semiconductor element of the present invention.Shown in Fig. 5 C, each light doping section 508 that is disposed at respectively in the substrate 300 between grid structure 310 and the doped region 509 comprises 508a of first and second portion 508b, and wherein the 508a of first connects second portion 508b.The 508a of first is disposed under the second surface 301b, and adjacent to the 3rd surperficial 301c.Second portion 508b is disposed under the 3rd surperficial 301c, and comprises that optionally a fraction of zone extends under the first surface 301a.When the length of grid was about 90nm, the horizontal distribution of each light doping section 508 for example was between about
Extremely
Between.In one embodiment, the length L of the 508a of first
1Between
Extremely
Between.In one embodiment, the length L of second portion 508b
2Between
Extremely
Between.What specify is, because the 3rd surperficial 301c is the inclined plane, so the inclination angle of each light doping section 508 can be controlled in 45 ° to 60 ° the scope, with the breakdown characteristics of holding element.
For confirming that semiconductor element of the present invention can effectively improve element efficiency, next will illustrate its characteristic with experimental example.The explanation of following experimental example only is to be used for illustrating the influence of the structural arrangements of semiconductor element of the present invention for transverse electric field (lateral electric field), but is not in order to limit scope of the present invention.
Experimental example
It is according to the existing known NMOS and the pairing transverse electric field distribution curve chart of NMOS diverse location in being parallel to the channel region of first surface of experimental example of the present invention that Fig. 6 illustrates.
As shown in Figure 6, the transverse electric field distribution of existing known NMOS of simulation and the NMOS proposed by the invention channel region at interface between near grid structure and silicon base respectively.The grid length that has the NMOS of known NMOS and experimental example of the present invention now is about 90nm.Under the situation that identical bias to two element is provided respectively, have the transverse electric field distribution of the transverse electric field distribution of known NMOS now far above the NMOS of experimental example of the present invention.Because the hot carrier effect of transverse electric field appreciable impact, the existing known NMOS that therefore has higher transverse electric field can meet with serious hot carrier effect, and causes element efficiency to reduce.Hence one can see that, and NMOS structure proposed by the invention has lower lateral electric field values, thereby can reach the effect of lift elements usefulness.
In sum, semiconductor element of the present invention comprises the light doping section with first and second portion, and inclination and crooked light doping section can not alleviate the situation decline low hot carrier effect of light doping section dopant concentration.And, by making light doping section have and crooked profile, can also alleviate as the overlap capacitance between gate induced drain leakage stream leakage currents such as (GIDL) and grid drain electrode.
In addition, the manufacture method of semiconductor element of the present invention utilizes disposable type (disposable) clearance wall to form inclination and crooked light doping section, and can be integrated into easily in the existing manufacturing process.Therefore, manufacturing process simply and not can increase manufacturing cost, and formed element also can have better usefulness.Moreover the manufacture method of semiconductor element of the present invention can be applied on all MOS component structures, even component size micro to the MOS element below the 90nm also is suitable for.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (20)
1. semiconductor element is characterized in that it comprises:
One substrate has a scalariform upper surface, wherein this scalariform upper surface comprise a first surface, be lower than this first surface a second surface, connect the 3rd surface of this first surface and this second surface;
One grid structure is disposed on this first surface;
Two doped regions are disposed in this substrate of these grid structure both sides, and are positioned under this second surface; And
Two light doping sections are disposed at respectively in this substrate between this grid structure and those doped regions, and wherein each those light doping section comprises:
One first is positioned under this second surface; And
One second portion connects this first, and is positioned at the 3rd surface down.
2. semiconductor element according to claim 1 is characterized in that wherein said the 3rd surface tilt in this first surface, and a bearing of trend of this first surface and the 3rd surperficial formed angle are between 45 ° to 60 °.
3. semiconductor element according to claim 1 is characterized in that wherein said first surface is parallel to this second surface.
4. semiconductor element according to claim 1, it is characterized in that between wherein said first surface and this second surface difference in height between
Extremely
Between, and the level interval between this first surface and this second surface between
Extremely
Between.
5. semiconductor element according to claim 1, it is characterized in that wherein said light doping section this first length between
Extremely
Between, and the length of this second portion between
Extremely
Between.
6. semiconductor element according to claim 1 is characterized in that it more comprises a clearance wall, be disposed on the sidewall of this grid structure and be positioned on those light doping sections, the thickness of this clearance wall between
Extremely
Between.
7. semiconductor element according to claim 1 is characterized in that it more comprises a stressor layers, is disposed in this substrate.
8. semiconductor element according to claim 1, it is characterized in that it more comprises two bags of shape implantation regions, be disposed in this substrate under this grid structure, each those bags shape implantation region is respectively adjacent to each those doped region, and wherein those bags shape implantation region is local bag shape implantation region or complex pocket shape implantation region.
9. the manufacture method of a semiconductor element is characterized in that it comprises:
One substrate is provided;
In this substrate, form a grid structure;
Remove this substrate of part to form a scalariform upper surface, wherein this scalariform upper surface comprise a first surface, be lower than this first surface a second surface, connect the 3rd surface of this first surface and this second surface;
Form two light doping sections in this substrate of these grid structure both sides, wherein each those light doping section comprises:
One first is formed under this second surface; And
One second portion connects this first, and is formed at the 3rd surface down; And
Form two doped regions in this substrate, those doped regions are positioned under this second surface and respectively in abutting connection with those light doping sections.
10. the manufacture method of semiconductor element according to claim 9 is characterized in that wherein said the 3rd surface tilt in this first surface, and a bearing of trend of this first surface and the 3rd surperficial formed angle are between 45 ° to 60 °.
11. the manufacture method of semiconductor element according to claim 9 is characterized in that wherein said first surface is parallel to this second surface.
12. the manufacture method of semiconductor element according to claim 9, it is characterized in that between wherein said first surface and this second surface difference in height between
Extremely
Between, and the level interval between this first surface and this second surface between
Extremely
Between.
13. the manufacture method of semiconductor element according to claim 9, it is characterized in that wherein said light doping section this first length between
Extremely
Between, and the length of this second portion between
Extremely
Between.
14. the manufacture method of semiconductor element according to claim 9, it is characterized in that on its sidewall that more is included in this grid structure with those light doping sections on form one first clearance wall, the thickness of this first clearance wall between
Extremely
Between.
15. the manufacture method of semiconductor element according to claim 14 is characterized in that the method for this first clearance wall of wherein said formation comprises:
In this substrate, form a spacer material layer;
Form one second clearance wall on the sidewall of this grid structure, wherein this second clearance wall covers this spacer material layer of part that is positioned on those light doping sections;
With this second clearance wall is that mask removes this spacer material layer of part; And
Remove this second clearance wall.
16. the manufacture method of semiconductor element according to claim 15, it is characterized in that wherein said remove the part this spacer material layer after, be that mask forms those doped regions with this second clearance wall.
17. the manufacture method of semiconductor element according to claim 15 is characterized in that wherein saidly before forming this second clearance wall or after removing this second clearance wall, forms those light doping sections.
18. the manufacture method of semiconductor element according to claim 14 is characterized in that wherein saidly after forming this first clearance wall, utilizes unitary system fabrication technique or two step manufacturing process to form those light doping sections and those doped regions.
19. the manufacture method of semiconductor element according to claim 9 is characterized in that it more is included in formation one stressor layers in this substrate.
20. the manufacture method of semiconductor element according to claim 9, it is characterized in that, after forming this scalariform upper surface or after forming those light doping sections or before forming those light doping sections, more be included in and form two bags of shape implantation regions in this substrate under this grid structure, each those bags shape implantation region is respectively adjacent to each those doped region, and wherein those bags shape implantation region is local bag shape implantation region or complex pocket shape implantation region.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832129A (en) * | 2011-06-17 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103000528A (en) * | 2011-09-16 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with nickel silicide contact regions and method for forming semiconductor structure |
| CN103887310A (en) * | 2012-12-19 | 2014-06-25 | 旺宏电子股份有限公司 | Volatile memory and fabricating method thereof |
-
2009
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832129A (en) * | 2011-06-17 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN102832129B (en) * | 2011-06-17 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103000528A (en) * | 2011-09-16 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with nickel silicide contact regions and method for forming semiconductor structure |
| CN103887310A (en) * | 2012-12-19 | 2014-06-25 | 旺宏电子股份有限公司 | Volatile memory and fabricating method thereof |
| CN103887310B (en) * | 2012-12-19 | 2016-05-11 | 旺宏电子股份有限公司 | Non-volatility memory and preparation method thereof |
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