CN101901754A - Method for preparing semiconductor material with nanocrystal embedded insulating layer - Google Patents
Method for preparing semiconductor material with nanocrystal embedded insulating layer Download PDFInfo
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- CN101901754A CN101901754A CN 201010211448 CN201010211448A CN101901754A CN 101901754 A CN101901754 A CN 101901754A CN 201010211448 CN201010211448 CN 201010211448 CN 201010211448 A CN201010211448 A CN 201010211448A CN 101901754 A CN101901754 A CN 101901754A
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Abstract
The invention provides a method for preparing a semiconductor material with a nanocrystal embedded insulating layer, comprising the following steps: providing a support substrate and a device substrate; growing an insulating layer on the surface of the support substrate or the device substrate; injecting nanocrystal modified ions in the insulating layer; bonding the support substrate and the device substrate through the insulating layer; and annealing and reinforcing after bonding. The invention has the advantages that by ingenious adjustment of process sequence, on the premise of having no influence on other processes, the adopted step of ion injection for forming nanocrystals is adjusted to be implemented ahead of the bonding step, thus having no influence on lattice integrity of a device layer and improving crystal quality of the prepared SOI material.
Description
[technical field]
The present invention relates to the semi-conducting material preparation field, relate in particular to a kind of nanocrystalline method for preparing semi-conducting material that in insulating barrier, embeds.
[background technology]
Develop rapidly along with space technology, the electronic system that is applied under the radiation environment is more and more, because radiation can cause the degeneration and the change of electronic devices and components and performance of integrated circuits, thereby the reliability of the electronic system that influence is formed thus, shorten life-span of system, when serious even can cause the failure of task.For spacecraft in orbit, radiation will cause disabler in short-term and shorten the life-span in orbit.(semiconductor on the silicon on the insulator: Silicon-On-Insulator or the insulator: Semiconductor-On-Insulator) technology is just for the demand that satisfies spaces such as Aero-Space, guided missile and satellite electron system and military electronic applications and a kind of technology that grows up for SOI.Four during the last ten years, and the development of this technology is applied as background with the military affairs and the space of radiation hardening always, and its target is to improve the prominent anti-of strategic arms and prolong satellite life-span in orbit.
The SOI material is because the existence of insulating buried layer, reduce the parasitic capacitance of device, improved the speed of device, and fundamentally eliminated the latch up effect of body silicon CMOS technology, the single-particle inversion cross section is than a body silicon CMOS technology young waiter in a wineshop or an inn order of magnitude, and the ability of anti-prompt dose rate improves two orders of magnitude.
But on the other hand because the existence of its insulating buried layer makes its preventing total dose radiation performance be restricted, this is that the radiation induced charge is captured on whole buried regions because when the SOI insulating buried layer is subjected to ionizing radiation.The trapped charge that these radiation are inducted mainly is electropositive.These electric charges can cause the back of the body channel interface transoid of n trench transistor, thereby cause part depletion (PD) and exhaust (FD) transistorized leakage current entirely and increase considerably.For full depleted transistor, positive gate transistor and back-gated transistor have the electric coupling effect, and the induct accumulation of positive charge of radiation can cause the reduction of positive gate transistor threshold voltage in the insulating buried layer.
At present, the anti-irradiation reinforcement technique of SOI material mainly is to utilize the insulating buried layer of ion implantation technique with silicon or other elements injection SOI material, and the hole trap electric charge that a large amount of electron trap of generation produces in buried regions with compensating for radiation in insulating buried layer reduces the quantity of positive charge in the buried regions.But the process of injecting atom in the SOI material can cause the damage of top layer silicon lattice, has reduced the crystal mass of top layer silicon.
[summary of the invention]
Technical problem to be solved by this invention is, a kind of nanocrystalline method for preparing semi-conducting material that embeds in insulating barrier is provided, in insulating buried layer, introduce in the silicon nanocrystal, can avoid silicon ion to inject the top layer silicon lattice damage that causes, improve the crystal mass of prepared SOI material.
In order to address the above problem, the invention provides a kind of nanocrystalline method for preparing semi-conducting material that in insulating barrier, embeds, comprise the steps: to provide support substrate and device substrate; Superficial growth insulating barrier in support substrates or device substrate; In insulating barrier, inject nanocrystalline modification ion; By insulating barrier support substrates and device substrate are bonded together; Annealing behind the enforcement bonding is reinforced.
As optional technical scheme, described method further is included in the step of injecting the foaming ion in the device substrate, this step is implemented after oxide layer growth finishes He before the bonding step, and before injecting the step of nanocrystalline modification ion or implement afterwards all can.Described foaming ion is selected from a kind of in hydrogen ion or the helium ion or two kinds.It is characterized in that described foaming ion is a hydrogen ion, the implantation dosage scope is 1 * 10
15Cm
-2～8 * 10
17Cm
-2In the bonding post-reinforcing process of described bonding step, device substrate will take place in the injection phase of foaming ion to bubble and peel off.Annealing reinforcement process behind the described bonding comprises two stages successively: the temperature range of phase I is 200 ℃～800 ℃, time range is 0.5 hour to 5 hours, the reinforcing temperature range of second stage is 900 ℃～1300 ℃, and consolidation time is 10 minutes～6 hours.
As optional technical scheme, the material of described insulating barrier is a silica, and described nanocrystalline modification ion is selected from one or both in silicon ion and the germanium ion.
As optional technical scheme, described nanocrystalline modification ion injection phase distance range between insulating barrier and the device substrate interface behind the bonding is 10nm～700nm.
As optional technical scheme, described nanocrystalline modification ion is a silicon ion, and the implantation dosage scope is 1 * 10
14Cm
-2～2 * 10
16Cm
-2
As optional technical scheme, the reinforcing temperature range of the annealing reinforcement process behind the described bonding is 900 ℃～1300 ℃, and consolidation time is 10 minutes～6 hours.
The invention has the advantages that, by ingenious adjustment to process sequence, under the prerequisite that does not influence other technologies, be adjusted at and implement before the bonding forming step that the nanocrystalline ion that adopts injects, thereby can not have influence on the perfection of lattice of device layer, improve the crystal mass of prepared SOI material.
[description of drawings]
Accompanying drawing 1 is the implementation step schematic diagram of the specific embodiment of the present invention;
Accompanying drawing 2 is process schematic representations of the specific embodiment of the present invention to accompanying drawing 6.
[embodiment]
Below in conjunction with accompanying drawing a kind of embodiment that embeds nanocrystalline method for preparing semi-conducting material in insulating barrier provided by the invention is elaborated.
Be the implementation step schematic diagram of the specific embodiment of the invention shown in the accompanying drawing 1, comprise the steps: step S10, provide support substrate and device substrate; Step S11 is at device substrate superficial growth insulating barrier; Step S12 injects the foaming ion in device substrate; Step S13 injects nanocrystalline modification ion in insulating barrier; Step S14 is bonded together support substrates and device substrate by insulating barrier; Step S15, the annealing behind the enforcement bonding is reinforced.
Accompanying drawing 2 is to shown in the accompanying drawing 6 being the process schematic representation of this embodiment.
Shown in the accompanying drawing 2, refer step S10 provides support substrate 100 and device substrate 190.
The material of described support substrates 100 can be to comprise common backing material in any this area of monocrystalline silicon, and this embodiment is a monocrystalline silicon.
Described device substrate 190 is used for forming top-layer semiconductor at subsequent step, be referred to as device layer again, therefore the material of this device substrate 190 should be a single-crystal semiconductor material commonly used such as monocrystalline silicon or compound semiconductor, and this embodiment is a monocrystalline silicon.
Shown in the accompanying drawing 3, refer step S11 is at device substrate 190 superficial growth insulating barriers 180.
In the present embodiment, the material of insulating barrier 180 is a silica.The method of growing silicon oxide can be a common method in this areas such as chemical vapour deposition (CVD) or thermal oxidation.
In other execution mode, insulating barrier 180 also can be grown in the surface of support substrates 100, perhaps promptly is grown in the surface of device substrate 190, also is grown in the surface of support substrates 100.
Shown in the accompanying drawing 4, refer step S12 and step S13 inject the foaming ion in device substrate 190, form foaming layer 199; In insulating barrier 180, inject nanocrystalline modification ion, form nanometer crystal layer 181.
The step of injecting the foaming ion is an optional step, and its purpose is in the subsequent technique that attenuate device substrate 190 is to form device layer more easily.
Described foaming ion is selected from a kind of in hydrogen ion or the helium ion or two kinds.The foaming ion is a hydrogen ion in this embodiment, and the implantation dosage scope is 1 * 10
15Cm
-2～8 * 10
17Cm
-2The energy that injects particle determines by final SOI top material layer silicon thickness, 5keV-500keV normally for hydrogen ion.If select the combination of helium ion or hydrogen ion and helium ion for use in other mode, its energy and dosage range should be made adjustment to above-mentioned parameter according to the character of helium ion.
Nanocrystalline modification ion is selected from one or both in silicon ion and the germanium ion.Nanocrystalline modification ion is a silicon ion described in this embodiment, and the implantation dosage scope is 1 * 10
14Cm
-2～2 * 10
16m
-2Nanocrystalline modification ion has formed nanocrystalline cluster among being injected into insulating barrier 180, can in insulating barrier 180, produce a large amount of electron traps, in case receive the radiation of radioactive ray, the hole trap electric charge that these electron traps can compensating for radiation produce in buried regions reduces the quantity of positive charge in the buried regions.
In this embodiment, nanocrystalline modification ion injection phase is that 10nm～700nm is preferable injection phase apart from the distance range between insulating barrier 180 and device substrate 190 interfaces, and is preferably 30nm～70nm, especially 50nm.In other execution mode, if insulating barrier 180 is the surfaces that are grown in support substrates 100, the distance range that then should control between injection phase and insulating buried layer 180 Free Surfaces is that 10nm～700nm is excellent, and further preferred 50nm, can guarantee like this that after bonding the injection phase is 10nm～700nm apart from the distance range between insulating barrier 180 and device substrate 190 interfaces.In the execution mode of insulating barrier is all grown on the surface of support substrates 100 and device substrate 190, then should determine which insulating barrier nanocrystalline modification ion should be infused in according to the thickness of insulating layer on device substrate 190 surfaces, and inject the degree of depth and be what, satisfy above-mentioned condition to guarantee bonding injection phase afterwards.
Since the ion that injects substrate can not strictness be distributed in a certain fixing position, but be Gaussian Profile along the direction injected, therefore the injection phase of the ion of being mentioned in this specification should be the peak of ion in the injection direction Gaussian Profile, and this also is the degree of depth is injected in this area to ion an a kind of common expression method.
The order of above-mentioned steps S12 and step S13 is not have strict priority to divide other, promptly can first implementation step S12, and also can first implementation step S13.In the present embodiment, because the injection degree of depth of foaming ion is greater than the modification ion, therefore preferable injection mode is at first to inject the foaming ion.
Shown in the accompanying drawing 5, refer step S14 is bonded together support substrates 100 and device substrate 190 by insulating barrier 180.
Insulating barrier 180 behind the bonding and has comprised the nanometer crystal layer 181 form nanocrystalline cluster owing to injecting in insulating barrier 180 between support substrates 100 and device substrate 190.
Bonding can be that hydrophilic bonding also can be a hydrophobic bonding, can use argon or oxygen plasma treatment substrate surface before the hydrophilic bonding.The bonding mode of optimizing is to adopt hydrophilic bonding, elder generation to use Ar+ to handle 5 minutes after the plasma treatment, washed with de-ionized water surface and drying subsequently, and substrate surface is adsorbed with one deck hydrone.Behind the bonding.
Shown in the accompanying drawing 6, refer step S15, the annealing behind the enforcement bonding is reinforced.
In this embodiment, consolidation process is divided into two stages, the temperature of phase I is 200 ℃～800 ℃, optimizing temperature is 600 ℃, consolidation time is 0.5 hour～5 hours, and the optimization time is 2 hours, in this process, the foaming ion that injects can further be assembled, and produces in device substrate 190 and peels off; Second stage will be warming up in 900 ℃～1300 ℃ intervals a certain temperature further annealing in process of carrying out 10 minutes to 6 hours become nanocrystallinely with the brilliant modification ion of activated nano, and strengthen the bond strength at bonded interface interface.The optimization temperature that heats up is 1100 ℃, the annealing of optimization 2 hours.
After above-mentioned steps was implemented to finish, device substrate 190 was peeled off in the position that the foaming ion injects, and had kept the device layer 191 that the device substrate 190 by remnants forms on the surface of insulating barrier 180.If the surface of device layer 191 is smooth inadequately, can also adopt polishing to wait flatening process that further correction is done on its surface.
As above-mentioned, the step of injecting the foaming ion is an optional step, in the execution mode that does not have implementation step S12, phase I among the step S15 is intended to realize that the technology of substrate desquamation can omit fully, and the method that only adopts a step annealing to reinforce, the technology of only implementing second stage is with the brilliant modification ion of activated nano and reinforce the bond strength of bonded interface.And after reinforcing, annealing adopt grinding or corrosion to wait other technology attenuate device substrate 190 to suitable thickness, as the device layer of final products.
After above-mentioned steps was implemented to finish, the substrate of acquisition comprised insulating barrier 180 and device layer 191, and had comprised the nanometer crystal layer 181 that forms nanocrystalline cluster owing to injecting in the insulating barrier 180.The step that the ion that formation nanometer crystal layer 181 is adopted injects was implemented before bonding, did not therefore have influence on the perfection of lattice of device layer 191.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. one kind embeds nanocrystalline method for preparing semi-conducting material in insulating barrier, it is characterized in that, comprises the steps:
Provide support substrate and device substrate;
Superficial growth insulating barrier in support substrates or device substrate;
In insulating barrier, inject nanocrystalline modification ion;
By insulating barrier support substrates and device substrate are bonded together;
Annealing behind the enforcement bonding is reinforced.
2. method according to claim 1, it is characterized in that, further be included in the device substrate step of injecting the foaming ion, this step is implemented oxide layer growth finishes after He before the bonding step, and before the step of the nanocrystalline modification ion of injection or enforcement afterwards all can.
3. method according to claim 2 is characterized in that, described foaming ion is selected from a kind of in hydrogen ion or the helium ion or two kinds.
4. according to claim 2 or 3 described methods, it is characterized in that described foaming ion is a hydrogen ion, the implantation dosage scope is 1 * 10
15Cm
-2～8 * 10
17Cm
-2
5. according to claim 2 or 3 described methods, it is characterized in that in the bonding post-reinforcing process of described bonding step, device substrate will take place in the injection phase of foaming ion to bubble and peel off.
6. method according to claim 1 is characterized in that, the material of described insulating barrier is a silica, and described nanocrystalline modification ion is selected from one or both in silicon ion and the germanium ion.
7. method according to claim 1 is characterized in that, described nanocrystalline modification ion injection phase distance range between insulating barrier and the device substrate interface behind the bonding is 10nm～700nm.
8. according to claim 1 or 7 described methods, it is characterized in that described nanocrystalline modification ion is a silicon ion, the implantation dosage scope is 1 * 10
14Cm
-2～2 * 10
16Cm
-2
9. method according to claim 1 is characterized in that, the reinforcing temperature range of the annealing reinforcement process behind the described bonding is 900 ℃～1300 ℃, and consolidation time is 10 minutes～6 hours.
10. according to claim 2 or 3 described methods, it is characterized in that, annealing reinforcement process behind the described bonding comprises two stages successively: the temperature range of phase I is 200 ℃～800 ℃, time range is 0.5 hour to 5 hours, the reinforcing temperature range of second stage is 900 ℃～1300 ℃, and consolidation time is 10 minutes～6 hours.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437087A (en) * | 2011-12-14 | 2012-05-02 | 中国科学院微电子研究所 | SOI structure with reinforced anti-irradiation performance and manufacturing method thereof |
| CN103117235A (en) * | 2013-01-31 | 2013-05-22 | 上海新傲科技股份有限公司 | Plasma-assisted bonding method |
| CN103311172A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | SOI (Silicon On Insulator) substrate formation method |
| CN106683980A (en) * | 2016-12-27 | 2017-05-17 | 上海新傲科技股份有限公司 | Preparation method of substrate with carrier capture center |
| CN107146758A (en) * | 2016-12-27 | 2017-09-08 | 上海新傲科技股份有限公司 | The preparation method of substrate with Carrier Trapping Centers |
| CN108155562A (en) * | 2016-12-05 | 2018-06-12 | 上海新微科技服务有限公司 | A kind of preparation method of aluminium, phosphor codoping silicon nanocrystal |
| US10388529B2 (en) | 2016-12-27 | 2019-08-20 | Shanghai Simgui Technology Co., Ltd. | Method for preparing substrate with insulated buried layer |
| CN111739838A (en) * | 2020-06-23 | 2020-10-02 | 中国科学院上海微***与信息技术研究所 | Preparation method of radiation-resistant SOI material |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437087B (en) * | 2011-12-14 | 2015-02-18 | 中国科学院微电子研究所 | SOI structure with reinforced anti-irradiation performance and manufacturing method thereof |
| CN102437087A (en) * | 2011-12-14 | 2012-05-02 | 中国科学院微电子研究所 | SOI structure with reinforced anti-irradiation performance and manufacturing method thereof |
| CN103311172A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | SOI (Silicon On Insulator) substrate formation method |
| US8980729B2 (en) | 2012-03-16 | 2015-03-17 | Semiconductor Manufacturing International Corp. | Silicon-on-insulator substrate and fabrication method |
| CN103117235A (en) * | 2013-01-31 | 2013-05-22 | 上海新傲科技股份有限公司 | Plasma-assisted bonding method |
| CN108155562A (en) * | 2016-12-05 | 2018-06-12 | 上海新微科技服务有限公司 | A kind of preparation method of aluminium, phosphor codoping silicon nanocrystal |
| CN108155562B (en) * | 2016-12-05 | 2019-12-10 | 上海新微科技服务有限公司 | Preparation method of aluminum and phosphorus co-doped silicon nanocrystal |
| CN107146758A (en) * | 2016-12-27 | 2017-09-08 | 上海新傲科技股份有限公司 | The preparation method of substrate with Carrier Trapping Centers |
| US10361114B2 (en) | 2016-12-27 | 2019-07-23 | Shanghai Simgui Technology Co., Ltd. | Method for preparing substrate with carrier trapping center |
| US10388529B2 (en) | 2016-12-27 | 2019-08-20 | Shanghai Simgui Technology Co., Ltd. | Method for preparing substrate with insulated buried layer |
| CN106683980A (en) * | 2016-12-27 | 2017-05-17 | 上海新傲科技股份有限公司 | Preparation method of substrate with carrier capture center |
| CN106683980B (en) * | 2016-12-27 | 2019-12-13 | 上海新傲科技股份有限公司 | Method for preparing substrate with carrier capture center |
| CN107146758B (en) * | 2016-12-27 | 2019-12-13 | 上海新傲科技股份有限公司 | Method for preparing substrate with carrier capture center |
| CN111739838A (en) * | 2020-06-23 | 2020-10-02 | 中国科学院上海微***与信息技术研究所 | Preparation method of radiation-resistant SOI material |
| CN111739838B (en) * | 2020-06-23 | 2023-10-31 | 中国科学院上海微***与信息技术研究所 | Preparation method of anti-radiation SOI material |
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Inventor after: Wei Xing Inventor after: Wang Xi Inventor after: Lin Chenglu Inventor after: Zhang Zhengxuan Inventor after: Zou Shichang Inventor after: Chen Ming Inventor after: Bi Dawei Inventor after: Wu Aimin Inventor after: Wang Xiang Inventor after: Li Xianyuan Inventor after: Zhang Miao Inventor before: Wei Xing Inventor before: Wang Xiang Inventor before: Li Xianyuan Inventor before: Zhang Miao Inventor before: Wang Xi Inventor before: Lin Chenglu |
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