CN101894810A - 复合底胶、半导体封装物及其形成方法 - Google Patents
复合底胶、半导体封装物及其形成方法 Download PDFInfo
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Abstract
本发明公开了一种复合底胶、半导体封装物及其形成方法。本发明的实施例借由于复合底胶内使用纳米结构而利用了纳米结构的物理特性。复合底胶的一实施例,包括涂布于基板与半导体芯片之间的一环氧树脂基材以及分布于该环氧基材内的纳米结构的悬浮物。于另一实施例的半导体封装物则包括一半导体芯片、一载具,其中半导体芯片连接于载具,而于载具与半导体芯片之间设置有包括分布于一环氧树脂基材内的多个纳米结构。于其他实施例中的半导体封装物的形成方法包括了复合底胶。本发明具有较佳热膨胀系数匹配情形、底胶的较高玻璃转换温度、较佳热整合性、底胶内较少的孔洞与沉淀情形、较高的抗湿气特性、较佳的静电放电保护情形以及较高的强度与弹性。
Description
技术领域
本发明涉及半导体封装物(semiconductor package)内的底胶(underfill),尤其涉及一种复合底胶(composite underfill)、半导体封装物以及半导体封装物的形成方法。
背景技术
一般于倒装芯片(flip chip)技术中,于半导体芯片(semiconductor chip)与载具(carrier)之间使用底胶(underfill)并借由降低焊锡凸块(solder bump)上的应力而增加封装物的可靠度。然而,可还改善底胶以助长公知底胶的功能。
倒装芯片组件(flip chip assembly)包括位于如陶瓷基板或电路板的一载具上的朝下面向(即覆盖)半导体芯片(chip)或裸片(die)的一直接电性连接情形,其使用了芯片上的导电凸块焊垫(conductive bump bond pads)而达成。倒装芯片组件通常借由于芯片的凸块焊垫(bump bond pad)上设置焊锡凸块(solder bump)、将形成有焊锡凸块的芯片贴附于载具上以及涂布粘着性的底胶于芯片与载具之间。公知底胶例如为Hitachi的3730及Namics的UA28。
倒装芯片组件的凸块具有多种功能,但其仍可能因为应力而产生故障。于上述功能中,凸块形成了自芯片至用于安装芯片的导电路径。这些凸块也构成了基板上的部分芯片的机械安装情形。不幸地,凸块通常基于应力问题而易破裂,而上述应力包括介于芯片与载具基板之间的热膨胀不匹配情形造成的应力。当热能变化产生时,上述的显著热膨胀系数差异将于结构处产生应力。图1A显示了于热平衡状态下通过焊锡凸块8而安装于载具4上的芯片2。图1B则显示了加热至高于热平衡状态的一温度时的芯片2’、载具4’与凸块8’。此时芯片2’膨胀了一长度ΔlFC,而载具4’则膨胀了一长度ΔlC。上述两长度间的差异于凸块8’上产生了会造成破裂或其他问题的应力。
解决起因于热膨胀系数差异所导致问题的一方案为使用环氧树脂底胶(epoxy underfill)以填入位于芯片与基板之间的间隙。图2A显示了加入于芯片2与载具4之间并环绕凸块8的底胶6。底胶帮助了应力的分散并保护了焊锡凸块。但是有时候底胶具有一高热膨胀系数(coefficient of thermalexpansion,CTE),其于芯片与底胶之间产生了不匹配(mismatch)的热膨胀情形。如此的不匹配情形于封装物内产生了更多应力,且其导致了故障问题。上述情形显示于图2B,其中底胶6”依照较封装物内其他元件更高的一比率而膨胀。底胶6”可能于芯片2”与载具4”之间产生***(bubble out)而造成了芯片2”的破裂(cracking)或脱附(delamination)。另外,底胶6”可膨胀了一高度Δhu并于凸块8”处产生了更高应力。
随着于芯片内低介电常数介电材料的广泛应用,对于凸块与低介电常数介电材料的保护形成两难。保护易碎的凸块需要高强度的底胶。然而,低介电常数介电层却可能受到上为高强度底胶的损害,而发生脱附等问题。为了保护低介电常数介电膜层,底胶较佳地具有低的玻璃转换温度(glass transitiontemperature,Tg)。低玻璃转换温度的底胶于相对低的温度产生软化。当芯片的温度上升时,底胶的模数(modulus)便减少,使得施加于低介电常数介电材料的应力得以降低。然而,基于此低模数,低玻璃转换温度的底胶对于焊锡凸块所提供的保护便降低,使得焊锡凸块面临可能造成断路(open circuit)的破裂情形。于图3内的放大情形10显示了当底胶6具有一高玻璃转换温度时,位于芯片2的低介电常数介电层内的破裂12。而放大情形14则显示了当底胶6具有低玻璃转换温度时,于一凸块8内的破裂16。
低介电常数介电材料可因底胶未能传导散去芯片的热能所引起的热疲劳(thermal fatique)而产生破裂。另外,低介电常数介电材料也可因如前所述的基于不匹配的热膨胀系数而产生破裂。
基于孔洞(void)或沉淀(settling)问题,公知底胶于分散应力以保护焊锡凸块方面并非一直有效。有时候,由于位于凸块焊垫上的焊锡凸块的间距(pitch)问题,于底胶内邻近焊锡凸块处会形成孔洞。当凸块与芯片之间的接合处的间距过小时,底胶内的微粒(particle)可能太大而填满此空间,因此便产生了孔洞。图4内的放大情形18则显示了邻近于凸块8与芯片2的焊垫(未显示)的一孔洞20的范例。孔洞将阻止底胶散布应力并可于孔洞处造成封装物的弱化。另外,于底胶中有时会混入有如二氧化硅的微粒。当这些微粒于硬化(curring)过程中产生沉淀或于底胶内形成不均匀的悬浮情形,如此将弱化底胶。图4内的放大情形22则显示了底胶6内的微粒24的沉淀情形。
此外,公知底胶通常并不具有良好的抗湿气(moisture resistance)特性。当湿气可穿透底胶时,于焊锡凸块之间将形成电性连接并造成短路(short circuit)问题。短路导致了整个封装物的故障。
因此,便需要一种较佳的底胶,以克服上述公知问题。
发明内容
有鉴于此,本发明的实施例中利用了纳米结构的物理特性并制造了包括纳米结构的底胶,以解决或避免了上述问题或其他问题并达成技术优点。
依据一实施例,本发明提供了一种复合底胶,包括:
一环氧树脂基材,涂布于一基板与一半导体芯片之间;以及纳米结构的一悬浮物,分散于该环氧树脂基材内。
依据另一实施例,本发明提供了一种半导体封装物,包括:
一半导体裸片;一基板,其中该半导体裸片借由焊锡凸块而电性耦接于该基板;以及一复合底胶,其包括散布于一树脂内的纳米结构,其中该复合底胶设置于该半导体裸片与该基板之间并环绕该焊锡凸块。
依据又一实施例,本发明提供了一种半导体封装物,包括:
一半导体裸片;一载具,其中该半导体裸片连接于该载具上;以及一复合底胶,包括分布于位于该载具与该半导体裸片间的一环氧树脂内的多个纳米结构。
依据另一实施例,本发明提供了一种半导体封装物的形成方法,包括:
于一半导体芯片上形成多个焊锡凸块;连接所述多个焊锡凸块与一载具;涂布包括纳米结构的一复合底胶;以及硬化该复合底胶。
本发明的实施例的优点在于半导体芯片与底胶之间具有较佳热膨胀系数匹配情形、底胶的较高玻璃转换温度、较佳热整合性、底胶内较少的孔洞与沉淀情形、较高的抗湿气特性、较佳的静电放电保护情形以及较高的强度与弹性。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举一优选实施例,并配合所附的附图,作详细说明如下:
附图说明
图1A显示了不具有处于热平衡状态的底胶的一倒装芯片组件;
图1B显示为具有处于热平衡状态的底胶的一倒装芯片组件;
图2A为具有处于热平衡状态的底胶的一倒装芯片组件;
图2B为具有经热膨胀的底胶的一倒装芯片组件;
图3显示了于一倒装芯片组件内于具有硬底胶的芯片的破裂情形以及具有软底胶的凸块的破裂情形;
图4显示了于一倒装芯片组件内凸块与芯片的接合处的孔洞情形以及底胶内的颗粒沉淀情形;
图5为一图表,显示了用于包括不同浓度的纳米结构的底胶的玻璃转换温度(Tg);
图6显示了具有包括纳米管的一底胶的倒装芯片组件;以及
图7为一表格,总结了包括不同浓度的纳米管的底胶的物理性质。
其中,附图标记说明如下:
2、2’、2”~芯片/倒装芯片;
4、4’、4”~载具;
6、6’、6”~底胶;
8、8’、8”~焊锡凸块/凸块;
10、14~放大情形;
16~破裂;
20~孔洞;
18、22~放大情形;
30~复合底胶;
32~纳米管;
34~放大情形;
ΔlFC~芯片的膨胀长度;
ΔlC~载具的膨胀长度;
Δhu~底胶的膨胀高度。
具体实施方式
本发明将借由以下关于倒装芯片技术内复合底胶的实施例而加以说明。本发明也适用于任何底胶的应用情形,例如于芯片级封装物(chip scalepackage,CSP)或球栅阵列(ball grid array,BGA)等应用。
纳米管(nanotube)、纳米纤维(nanofiber)或纳米颗粒(nanoparticles)通常为碳的同素异构物(allotropes),但其可包括碳、氮化碳、氮碳化硅(silicon carbonnitride)、钨或银。纳米管具有位于圆柱内的蜂巢结晶晶格(honeycomb crystallattice)形状。纳米管通常具有约100nm或更少的一直径。纳米纤维相似于纳米管,除了其具有大于100nm的直径。纳米微粒为化合物的单一分子。于下文中仅于提及了包括纳米管、纳米纤维及/或纳米微粒的纳米结构。另外,可以理解的是纳米管或纳米纤维包括各种形态的纳米管或纳米纤维,包括扶椅形(armchair)、锯齿形(zig-zag)及对掌形(chiral)的纳米管及纳米纤维及单层壁(single-walled)或多层壁(multi-walled)的纳米管与纳米纤维。
具有特殊物理特性的纳米结构于其材料应用方面已进行了热烈且不间断的研究。纳米结构具有惊人的强度与拉伸特性。此外,纳米结构具有非常高的热导率(thermal conductivity)。另外,纳米结构具有相似于半导体材料的电性特性,且于某些情形中其具有相似于金属的电性特性。
本发明的实施例中欲利用纳米结构的特性,而形成包括公知环氧树脂基材(epoxy matrix)与纳米结构的复合底胶。环氧树脂基材通常为于环氧树脂材料包覆有另一材料。于环氧树脂基材内的纳米结构可为一悬浮物,并可使得纳米结构大体均匀地分布于环氧树脂基材内,虽然其仍可部分沉淀。如此的复合底胶相较于公知底胶可具有一较佳表现,其借由具有较佳的热膨胀系数以及较高的玻璃转换温度、较佳的热整合性、底胶内的孔洞与沉淀的减少,及对外界环境的较佳抵抗特性所达成。
复合底胶可包括任一浓度的纳米结构,但较特别地,复合底胶具有约0.5~10重量百分比(concentration by weight)的纳米结构。换句话说,纳米结构与环氧树脂具有1∶199~1∶9的重量比例。较佳地,底胶具有0.5重量百分比的纳米结构浓度。
当纳米结构中使用纳米管时,纳米管可为任何公知的结构,但较佳地使用多层壁的纳米管而不是使用单层壁的纳米管,此由于多层壁的纳米管具有较接近类似于半导体材料的电性特性。商用纳米管的供应商例如为ShenzhenNanotech Port Company Ltd。
混合纳米管与公知底胶可形成了一复合底胶,其具有可降低底胶与芯片之间的热膨胀不匹配情形的较低热膨胀系数。随着底胶内的较高的纳米管浓度,纳米结构可贡献较多以形成具低热膨胀系数的底胶。因此,具有高浓度的纳米管的复合底胶相较于具有低浓度的纳米管的复合底胶通常具有低的热膨胀系数。
另外,纳米管具有可增加复合底胶的整体玻璃转换温度的较高玻璃转换温度。图5显示了包括了约0%、0.5%、1%、2%、3%的纳米浓度的纳米管的复合底胶的玻璃转换温度。于各线段中采用箭头显示的不连续处显示了玻璃转换温度(Tg)。当于底胶内未出现有纳米管时,玻璃转换温度约为113℃。当复合底胶具有0.5%的纳米结构浓度时,玻璃转换温度约为201℃。于纳米结构浓度为1%时的玻璃转换温度约为217℃、为2%时的玻璃转换温度约为248℃,而3%时的玻璃转换温度约为233℃。玻璃转换温度的增加使得底胶的强度增加至可保护焊锡凸块的较佳强度。虽然于玻璃转换温度的增加仍负面地影响了低介电常数介电材料,然而上述效应可借由工艺的改善而降低。
于底胶内纳米结构的添加情形形成了整体较高的热整合性。通常,纳米结构具有为3000W/m·k的一热导率。上述热导率使得纳米结构也可散逸来自于芯片的热能并进而有助于防止低介电常数介电材料的热疲劳与破裂情形。
纳米结构可填入于孔洞且通常不会于底胶内形成沉淀。纳米结构的直径使得复合底胶可填入于介于凸块间的窄小空间以及接近凸块接点的芯片处。如前所述,纳米管通常具有约为100nm的尺寸。另外,公知底胶具有通常直径约为5微米的微粒,但纳米管通常具有约100nm的直径。纳米管的较小直径使得纳米结构可填满了一般公知底胶无法填入的空间。另外,上述的较小尺寸可使得具有纳米结构的复合底胶适用于较小尺寸的封装物的应用,例如N22或更少的技术应用。此外,纳米结构的物理特性使得纳米结构可共价接合于环氧树脂,因而避免纳米结构的沉淀。借由阻止了孔洞与沉淀形成,封装物与底胶可较公知底胶更为强化。图6显示了孔洞与沉淀的阻止情形。复合底胶30位于倒装芯片2与载具4之间并环绕凸块8。放大情形34显示了悬浮于复合底胶30的基材内的纳米管32。
混合于底胶内的纳米结构可增加底胶的湿气阻挡率(moisture resistivity)。纳米结构通常为疏水的。如此可避免湿气穿透复合底胶而造成封装物的电性故障情形。
于底胶内混合纳米结构的另一特征为静电放电故障情形(electrostaticdischarge failure)的减少,其由于纳米结构改善了导电率。纳米结构的较佳电性特征使得了纳米结构可释放静电,因而最小化了对于芯片的任何影响。
另外,对于复合底胶,纳米结构通常提供了较佳的机械强度(mechanicalstrength)与弹性(elasticity)。图7内总结了具有包括0%、0.5%、1%、2%与3%浓度的多层壁纳米管的纳米结构浓度的底胶的部分性质。
底胶与纳米管的混合可采用超音波(ultrasonic force)达成。上述超音波具有介于100转/分钟至5500转/分钟的表现。而上述超音波可采用一旋转涂布机器(spin coating machine)或一超音波机台(ultrasonic too1)而施行。旋转涂布机台的商用产品例如为由Chemat科技有限公司产制的Chemalux机台,而超音速机台的商用产品例如为Chinasource公司的B2B机台。
于载具基板与倒装芯片芯片接合之后可采用如毛细管(capillarity)技术的公知工艺以提供复合底胶,但复合底胶也可于基板与倒装芯片芯片接合之前直接提供至载具基板上。于涂布复合底胶之后,可采用公知技术硬化底胶而将之转变成一固体材料,例如是借由热方式,特别是于75℃~200℃的温度下。
虽然本发明已以优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (16)
1.一种复合底胶,包括:
一环氧树脂基材,涂布于一基板与一半导体芯片之间;以及
纳米结构的一悬浮物,分散于该环氧树脂基材内。
2.如权利要求1所述的复合底胶,其中该纳米结构占该复合底胶的0.5~10重量百分比。
3.如权利要求1所述的复合底胶,其中该纳米结构包括碳、氮化碳、氮碳化硅、钨或银。
4.如权利要求1所述的复合底胶,其中该纳米结构包括多层壁的纳米管。
5.一种半导体封装物,包括:
一半导体裸片;
一基板,其中该半导体裸片借由焊锡凸块而电性耦接于该基板;以及
一复合底胶,其包括散布于一树脂内的纳米结构,其中该复合底胶设置于该半导体裸片与该基板之间并环绕该焊锡凸块。
6.如权利要求5所述的半导体封装物,其中该纳米结构包括碳、氮化碳、氮碳化硅、钨或银。
7.如权利要求5所述的半导体封装物,其中该纳米结构包括多层壁的纳米管。
8.如权利要求5所述的半导体封装物,其中该纳米结构与该环氧树脂具有介于1∶199~1∶9的重量比。
9.一种半导体封装物,包括:
一半导体裸片;
一载具,其中该半导体裸片连接于该载具上;以及
一复合底胶,包括分布于位于该载具与该半导体裸片间的一环氧树脂内的多个纳米结构。
10.如权利要求9所述的半导体封装物,其中所述多个纳米结构占该复合底胶的0.5~10%重量百分比。
11.如权利要求9所述的半导体封装物,其中所述多个纳米结构为多个多层壁的纳米管。
12.一种半导体封装物的形成方法,包括:
于一半导体芯片上形成多个焊锡凸块;
连接所述多个焊锡凸块与一载具;
涂布包括纳米结构的一复合底胶;以及
硬化该复合底胶。
13.如权利要求12所述的半导体封装物的形成方法,其中该复合底胶的纳米结构占该复合底胶0.5~10%重量百分比。
14.如权利要求12所述的半导体封装物的形成方法,其中涂布该复合底胶包括:
于连接所述多个焊锡凸块与该载具之前,直接涂布该复合底胶于基板上。
15.如权利要求12所述的半导体封装物的形成方法,其中涂布该复合底胶包括:
于连接所述多个焊锡凸块与该载具后,涂布该复合底胶于该半导体芯片与该载具之间并环绕所述多个焊锡凸块。
16.如权利要求12所述的半导体封装物的形成方法,其中硬化该复合底胶包括:
加热该复合底胶至介于75~200℃的一温度。
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