CN101894753A - Method for preparing dielectric film embedded with high-density palladium nano-crystal - Google Patents
Method for preparing dielectric film embedded with high-density palladium nano-crystal Download PDFInfo
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- CN101894753A CN101894753A CN 201010221406 CN201010221406A CN101894753A CN 101894753 A CN101894753 A CN 101894753A CN 201010221406 CN201010221406 CN 201010221406 CN 201010221406 A CN201010221406 A CN 201010221406A CN 101894753 A CN101894753 A CN 101894753A
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Abstract
The invention belongs to the technical field of semiconductor memory manufacturing and in particular relates to a method for preparing a dielectric film embedded with a high-density palladium nano-crystal. The method comprises the steps of performing co-sputtering in oxygen atmosphere to deposit the dielectric film which contains palladium oxide and performing high-temperature fast thermal annealing treatment to obtain the dielectric film embedded with the high-density palladium nano-crystal, wherein the diameter of the palladium nano-crystal is about 3 to 15 nanometers. The dielectric film embedded with the high-density palladium nano-crystal prepared by the method shows good charge storage effect when used as a charge trapping layer in a flash device.
Description
Technical field
The invention belongs to the manufacturing technology field of semiconductor memory, be specifically related to a kind of method for preparing the embedded with high-density palladium nano-crystal dielectric film, can be used for the electric charge capture layer in the flush memory device.
Technical background
Along with the continuous development of semiconductor process techniques, in the past few decades in, flash memory market develops rapidly, according to ITRS in 2007 prediction, to the year two thousand twenty, the size of flash memory cells will be reduced to 1000nm
2Traditional Nonvolatile flash memory based on multi-crystal silicon floating bar has faced a series of problems after 65 nm technology node, most importantly the data holding ability that causes of tunnel oxide attenuate is degenerated
[1]Compare with traditional floating gate structure, adopt discrete electric charge memory technology can improve the data hold time of memory
[2]Near numerous advantages such as big quantity research shows that metallic nano crystal has the higher density of states Fermi level, does not have the multidimensional effect of carrier confinement, and the work function range of choice is bigger, thereby have good application prospects
[3]
Palladium (Pd) has bigger work function (5.1 eV) as a kind of metal, if adopt Pd nanocrystalline as the electric charge capture center, then can obtain the very big potential well degree of depth, thereby effectively stop charge loss, and good charge-retention property is provided
[4]In addition, the chemical stability between Pd and the high dielectric constant is good.Therefore, Pd is nanocrystalline has a good application prospects in flush memory device.Yet, how to obtain that highdensity Pd is nanocrystalline to become extremely important.Simultaneously, its preparation technology is also compatible mutually with standard CMOS process, and can not cause damage to gate oxide in preparation process.The nanocrystalline Two dimensional Distribution that mainly is of open report is grown at present
[5], because nanocrystalline size and distribution are wayward, so nanocrystalline surface density is relatively limited.People such as Wang have reported that the HfAlO medium of embedded germanium nanocrystal does the electric charge capture layer of memory, because the germanium nanocrystal size of gained is little, and the density height, and be distributed in three dimensions, therefore obtained good electric property
[6]
Therefore, the present invention proposes a kind of method of utilizing cosputtering,, prepared and in medium, embedded the nanocrystalline method of high density Pd in conjunction with single step annealing.
Summary of the invention
It is compatible mutually with CMOS technology to the purpose of this invention is to provide a kind of processing step, and can reduce the method for preparing the embedded with high-density palladium nano-crystal dielectric film of memory cost.
The method for preparing the embedded with high-density palladium nano-crystal dielectric film that the present invention proposes is the method by cosputtering and after annealing, and it is nanocrystalline to embed the high density Pd that is distributed in three dimensions in dielectric.It specifically is the method for utilizing magnetron sputtering, cosputtering obtains including medium (as the titanium oxide) laminated film of palladium oxide in the plasma of oxygen and argon gas, laminated film with gained carries out rapid thermal annealing then, obtains medium (as the titanium oxide) film of embedded with high-density palladium nano-crystal.Wherein, the particle diameter of palladium nano-crystal is 3-15nm, and average grain diameter is about 10nm.
And all processing steps are compatible mutually with CMOS technology, greatly reduce the manufacturing cost of memory.
The preparation method's that the present invention proposes concrete operations step is as follows:
1, adopt the deposit of cosputtering method to contain the dielectric film of palladium oxide (as TiO
2).Two used targets of magnetron sputtering are respectively palladium (Pd) and medium (as titanium), and sputter gas is argon gas (Ar) and oxygen (O
2).O
2With the flow-rate ratio of Ar be 1:3～1:20, operating air pressure is 0.5 ~ 1Pa in the chamber.In order to control the relative amount of Pd and Ti in the film, the direct current power that is loaded on palladium target and medium (as the titanium) target is than being 1:1 ~ 1:60, and underlayer temperature is controlled in 20 ~ 350 ℃ of scopes, and the substrate rotating speed is 3 ~ 12 rpm.
2, the gained film is carried out rapid thermal annealing, can obtain the nanocrystalline dielectric film of embedded Pd (as TiO
2).Annealing atmosphere is nitrogen (N
2) or oxygen (O
2).In the annealing process, kept 2 ~ 5 minutes at 150 ~ 200 ℃ earlier, purpose is to remove in the annealing furnace cavity and the adsorbed moisture content of sample surfaces, is warmed up to arbitrary temperature in 500 ~ 900 ℃ of scopes then, and constant temperature 15 ~ 60 seconds.
The dielectric material of mentioning is not limited to TiO among the present invention
2, it can be Al
2O
3, HfO
2, SiO
2Deng dielectric, also can be the composite material of two or more dielectric material.
The present invention has the following advantages:
1, the present invention adopts the method deposit original metal sull of cosputtering, the film of different Pd content can be obtained by the watt level that is loaded on the control different metal target (as Pd and Ti target), thereby nanocrystalline size and the density of the annealing formed Pd in back can be controlled.
2, contain palladium oxide in the initial film, it can resolve into metal Pd in the high-temperature quick thermal annealing process, and the metal Pd atom can organize themselves into nucleus growth, makes the nanocrystalline TiO of being evenly dispersed in of Pd
2In the dielectric film, be distributed in three dimensions.Compare with the nanocrystalline of Two dimensional Distribution, improved nanocrystalline surface density greatly.
3, the technology that is adopted among the present invention can guarantee the uniformity of film in than large tracts of land, can not introduce pollution, and is compatible mutually with existing CMOS technology.
4, it is nanocrystalline to adopt this method to prepare Pd, and required rapid thermal annealing temperature is lower, helps reducing fire damage and energy consumption in the device manufacturing processes.
The processing step of the inventive method is compatible mutually with CMOS technology, greatly reduces the manufacturing cost of memory.Show good charge-storage effect during as the electric charge capture layer in the flush memory device by the dielectric film of the embedded with high-density palladium nano-crystal of the inventive method preparation.
Description of drawings
X-ray diffraction (XRD) collection of illustrative plates of the sample that obtains under the different annealing temperature of Fig. 1.
Capacitance-voltage (C-V) characteristic curve of the unannealed sample of Fig. 2 (it is nanocrystalline not contain Pd).
The C-V characteristic curve of Fig. 3 gained sample (it is nanocrystalline to contain Pd) after 800 ℃ of annealing.
Embodiment
The invention is further illustrated by the following examples.
Embodiment:
P type (100) silicon chip is through after the standard cleaning, by the Al of the about 6nm thickness of atomic layer deposition (ALD) method growth one deck
2O
3Film is as the electric charge tunnel layer.The silicon chip that is coated with above-mentioned film is put into the magnetron sputtering reaction chamber, and two targets of cosputtering are Pd and Ti.Sputtering condition is: chamber vacuum degree 4.2 * 10
-5Pa, argon gas (Ar) flow is 37sccm, oxygen (O
2) flow is 4sccm, added direct current power is respectively 25W and 100W on Pd target and the Ti target, and operating air pressure is 0.72Pa, and substrate does not heat, and the substrate rotating speed is 8 rpm, the cosputtering time is 840 seconds.Test analysis shows that the film that obtains by the cosputtering method is palladium oxide (PdO
x) and titanium oxide (TiO
x) mixed film.Then, the gained sample is put into rapid thermal anneler carry out rapid thermal annealing, annealing atmosphere is a nitrogen.Kept 2 minutes at 200 ℃ earlier, rise to specific annealing temperature then, heating rate is 20 ℃/second, and annealing time is 15 seconds.In this example, selected specified temp comprises 600 ℃, 800 ℃, 900 ℃.Then, adopt method growth one deck Al of atomic layer deposition
2O
3As electric charge barrier layer, the about 24nm of thickness.At last, form the Metal Palladium gate electrode of 100 nanometer thickness through processing steps such as photoetching, electron beam evaporations.
Fig. 1 is the X ray diffracting spectrum (XRD) of the sample that obtains under different annealing temperatures.As can be seen, Pd is nanocrystalline not to be formed when unannealed, forms after 600 ℃ of annealing.Along with the rising of annealing temperature, become gradually greatly corresponding to the intensity of the diffraction maximum of Pd, show that the Pd crystallite dimension is along with the rising of annealing temperature constantly becomes big.Table 1 is the nanocrystalline average diameter of Pd that calculates according to the Scherrer formula, and the result shows that the nanocrystalline diameter of Pd increases to 21 nanometers from about 9nm along with annealing temperature rises to 900 ℃ from 600 ℃.Fig. 2 is unannealed sample (it is nanocrystalline not contain Pd) pairing capacitance-voltage (C-V) hysteresis loop, shows very little hysteresis window.Fig. 3 is 800 ℃ of pairing C-V hysteresis loops of sample (it is nanocrystalline to contain Pd) after the annealing.The result shows that along with the increase of scanning voltage scope, C-V hysteresis window also constantly increases.This is because the nanocrystalline generation of Pd causes charge-storage effect remarkable.
List of references
[1]?A.?Thean,?J.?P.?Leburton,?“Flash?memory:?towards?single-electronics”,?IEEE?Potentials?21,?4?(2002)。
[2]?Yoo-Sung?Jang,?Jong-Hwan?Yoon,?and?Robert?G..Elliman,?“Formation?of?nickel-based?nanocrytal?monolayers?for?nonvolatile?memory?applications”,?Appl.?Phys.?Lett.?92,?253108?(2008)。
[3]?J.?Y.?Yang,?K.?S.?Yoon,?W.?J.?Choi,?Y.?H.?Do,?J.?H.?Kim,?C.?O.?Kim,?J.?P.?Hong,?“Efficient?fabrication?and?characterization?of?cobalt?nanoparticles?embedded?in?metal/oxide/semiconductor?structures?for?the?application?of?nonvolatile?memory”,?J.?Vac.?Sci.?Technol.B?24,?6?(2006)。
[4]?K.?S.?Seol,?S.?J.?Choi,?J.-Y.?Choi?et?al.,?“Pd-?nanocrystal-based?nonvolatile?memory?structures?with?asymmetric?SiO2/HfO2?tunnel?barrier”?,?Appl.?Phys.?Lett.?89,?083109?(2006)。
[5]?Z.?T.?Liu,?C.?Lee,?V.?Narayanan?et?al,?“Metal?nanocrystal?memories-?partⅠ:?device?design?and?fabrication”,?IEEE?Trans.?Elec.?Dev.?49,?9?(2002)。
[6]Ying?Qian?Wang?,Jing?Hao?Chen,Won?Jong?Yoo,et?al.?“Formation?of?Ge?nanocrystals?in?HfAlO?high-k?dielectric?and?application?in?the?memory?device”,?Appl.?Phys.?Lett.?84?,?26?(2004)。
Claims (3)
1. the preparation method of the dielectric film of an embedded with high-density palladium nano-crystal, it is characterized in that: the method for utilizing magnetron sputtering, cosputtering obtains including the complex thin film of palladium oxide in the plasma of oxygen and argon gas, laminated film with gained carries out rapid thermal annealing then, obtains the dielectric film of embedded with high-density palladium nano-crystal; Wherein, the material of described medium is the single insulating dielectric material, or the composite material of two or more dielectric materials.
2. preparation method according to claim 1 is characterized in that said dielectric material is TiO
2, Al
2O
3, HfO
2Or SiO
2.
3. preparation method according to claim 1 and 2 is characterized in that the concrete operations step is as follows:
The first step, the deposit of employing cosputtering method contain the dielectric film of palladium oxide, and two used targets of magnetron sputtering are respectively palladium and medium, and sputter gas is argon gas and oxygen, and the flow-rate ratio of oxygen and argon gas is 1:3～1:20, and operating air pressure is 0.5 ~ 1Pa in the chamber; The direct current power that is loaded on palladium target and the medium target is than being 1:1 ~ 1:60, and underlayer temperature is controlled in 20 ~ 350 ℃ of scopes, and the substrate rotating speed is 3 ~ 12 rpm;
Second the step, the gained film is carried out rapid thermal annealing, promptly obtain the nanocrystalline dielectric film of embedded Pd; Annealing atmosphere is nitrogen or oxygen, and annealing process is, keeps 2 ~ 5 minutes at 150 ~ 200 ℃ earlier, is warmed up to arbitrary temperature in 500 ~ 900 ℃ of scopes then, and constant temperature 15 ~ 60 seconds.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235064A1 (en) * | 2002-06-21 | 2003-12-25 | Shubneesh Batra | Method of forming a non-volatile electron storage memory and the resulting device |
| US20050045943A1 (en) * | 2003-08-25 | 2005-03-03 | Hsiang-Lan Lung | [non-volatile memory cell and fabrication thereof] |
| US20070090444A1 (en) * | 2005-10-21 | 2007-04-26 | Samsung Electronics Co, Ltd. | Nonvolatile memory device including nano dot and method of fabricating the same |
| CN100477095C (en) * | 2007-05-17 | 2009-04-08 | 复旦大学 | Manufacture method of sputtering deposition of high-density Ru nanocrystalline for flash memory |
-
2010
- 2010-07-08 CN CN201010221406A patent/CN101894753B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235064A1 (en) * | 2002-06-21 | 2003-12-25 | Shubneesh Batra | Method of forming a non-volatile electron storage memory and the resulting device |
| US20050045943A1 (en) * | 2003-08-25 | 2005-03-03 | Hsiang-Lan Lung | [non-volatile memory cell and fabrication thereof] |
| US20070090444A1 (en) * | 2005-10-21 | 2007-04-26 | Samsung Electronics Co, Ltd. | Nonvolatile memory device including nano dot and method of fabricating the same |
| CN100477095C (en) * | 2007-05-17 | 2009-04-08 | 复旦大学 | Manufacture method of sputtering deposition of high-density Ru nanocrystalline for flash memory |
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