CN101894084A - Device for writing operation in CLB bus - Google Patents
Device for writing operation in CLB bus Download PDFInfo
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- CN101894084A CN101894084A CN 201010156996 CN201010156996A CN101894084A CN 101894084 A CN101894084 A CN 101894084A CN 201010156996 CN201010156996 CN 201010156996 CN 201010156996 A CN201010156996 A CN 201010156996A CN 101894084 A CN101894084 A CN 101894084A
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Abstract
The invention discloses a device for writing operation in a CLB bus. The device comprises a microprocessor, a CLB bus and equipment, wherein the equipment is accessed by the microprocessor; a command buffer for latching a reading/writing operation instruction and data is arranged between the CLB bus and the equipment; a first-level command storage unit is arranged in the command buffer and comprises a first command significance bit, a first sign storage area, a first bit width storage area, a first address storage area and a first data storage area; the first command significance bit is used for identifying whether the first-level command storage unit stores information waiting to be executed; the first sign storage area is used for identifying access attributes; the first bit width storage area controls the bit width of the operation data; the first address storage area is used for storing access addresses; and the first data storage area is used for storing the data. The device ensures that the microprocessor can perform successive bus operation without waiting for slow equipment to finish writing operation, so that the system efficiency is improved.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to the device that is used for write operation in a kind of CLB bus.
Background technology
In the C*CORE system, the C*CORE microprocessor carries out read-write operation by CLB (C-Core Local Bus) bus to equipment, and CLB (C-Core Local Bus) bus is that the applicant reuses the open bus of having carried out on the basis of standard improving and having optimized and come at Motorola Inc.'s semiconductor.In the prior art equipment being carried out read-write operation can finish 2 clock period the soonest.
The connection layout of existing C * CORE microprocessor and external unit is shown in accompanying drawing three, no matter the device rate speed all is directly connected on the CLB bus.Like this, equipment (such as register) can respond the read and write access of C*CORE microprocessor in a clock period fast, but equipment at a slow speed can't be finished the read-write operation of CCORE in a clock period, so need latent period promptly to insert the latent period of sufficient amount in operation.This paper is by simple control, can realize reducing or eliminating CCORE slow devices is carried out latent period in the write operation, to improve the efficient of system.Write operation for slow devices, the way of prior art is exactly to insert the latent period of sufficient amount in operation, till equipment echo reply signal, shown in accompanying drawing two, the problem of doing like this is the C*CORE microprocessor can not carry out other again in latent period a bus operation, inefficiency.
Therefore, how to develop the stand-by period that reduces the C*CORE microprocessor, become the direction that those skilled in the art make great efforts to improve resource utilization ratio.
Summary of the invention
The object of the invention provides the device that is used for write operation in a kind of CLB bus, and this device makes the C*CORE microprocessor needn't wait for that the slow devices write operation finishes, and can carry out follow-up bus operation, thereby improve the efficient of system.
For achieving the above object, the technical solution used in the present invention is: be used for the device of write operation in a kind of CLB bus, this device comprises:
Microprocessor, this microprocessor sends information according to CLB bus protocol equipment in system;
The CLB bus is used for according to CLB bus protocol transmission information between microprocessor and equipment;
Be used for equipment for microprocessor access;
Be provided with the commands buffer that is used to latch the read/write operation instruction and data between described CLB bus and the equipment, be provided with first order command storage unit in this commands buffer, this first order command storage unit comprises: be used to identify the first bit wide memory block, the memory block, first address that is used for the memory access address that whether have the first order significance bit of waiting for the information that is performed, the first sign memory block that is used for the identification access attribute, control operation data bit width in the first order command storage unit, be used to store first region of data storage of write data;
This commands buffer is configured as follows:
When bus read or write signal is in write operation state level, microprocessor this visit is a write operation, deposit bus read or write signal, bus operation data bit width signal and bus operation address signal in first sign memory block, the first bit wide memory block and memory block, first address respectively
With the first order active position be effective, simultaneously, deposits total line write transactions data in first region of data storage, and commands buffer sends effective bus operation answer signal and bus read or write signal respectively to described microprocessor and equipment,
After microprocessor received the bus operation answer signal, microprocessor finished this write operation, and commands buffer continues the write operation of control to equipment,
When commands buffer receives the answer signal that returns from equipment, commands buffer finishes this write operation that equipment is carried out;
When bus read or write signal is in read operation state level, microprocessor this visit is read operation, deposit bus read or write signal, bus operation data bit width signal and bus operation address signal in first sign memory block, the first bit wide memory block and memory block, first address respectively
With the first order active position be effectively, and simultaneously, and commands buffer is to described equipment transmission bus read or write signal, bus operation data bit width signal and bus operation address signal, and microprocessor is waited for the answer signal of this read operation,
When equipment to commands buffer echo reply signal, read operation is this time finished, commands buffer sends the bus operation answer signal to microprocessor, microprocessor finishes this read operation that equipment is carried out after receiving the bus operation answer signal.
Related content in the technique scheme is explained as follows:
1, in the such scheme, also be provided with second level command storage unit in the described commands buffer, this second level command storage unit comprises: be used to identify second level command storage unit and whether have the second order significance bit of waiting for the information that is performed, be used for the second sign memory block, the control operation data bit width of identification access attribute the second bit wide memory block, be used for the memory access address memory block, second address, be used to store second region of data storage of write data;
This commands buffer also is configured to, when commands buffer is carried out write operation promptly the first order significance bit effectively and microprocessor receives the bus operation answer signal to equipment after, will deposit second sign memory block, the second bit wide memory block and the memory block, second address respectively in from the new bus read or write signal of described microprocessor, new bus operation data bit width signal and new bus operation address signal;
Finishing when described write operation visit is the answer signal that the commands buffer equipment of receiving returns, this moment first, the order significance bit was invalid, again corresponding information reproduction in the command storage unit of the second level is arrived in the corresponding zone of first order command storage unit, the first order active position is effectively simultaneously, and the second order active position is invalid.
2, in the such scheme, described commands buffer adopts the first in first out storage queue of the secondary degree of depth.
Because technique scheme utilization, the present invention are compared with prior art, the present invention is by increasing simple control, makes microprocessor needn't wait for that the slow devices write operation finishes, thereby can carry out follow-up bus operation immediately, improved the efficient of system.Secondly,, make and in the write operation process, can carry out next read or write, thereby improved system resource arrangement utilization factor by increasing second level command storage unit.
Description of drawings
Accompanying drawing 1 is the total line write transactions synoptic diagram of CLB of no slow devices;
Accompanying drawing 2 is for there being the total line write transactions synoptic diagram of CLB of slow devices;
Accompanying drawing 3 is existing C * CORE microprocessor and peripheral hardware connection diagram;
Accompanying drawing 4 is for having the C*CORE microprocessor and the peripheral hardware connection diagram of commands buffer.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment: be used for the device of write operation in a kind of CLB bus,
This device comprises:
The C*CORE microprocessor, this microprocessor sends information according to CLB bus protocol equipment in system;
The CLB bus is used for according to CLB bus protocol transmission information between C*CORE microprocessor and equipment;
Be used for equipment for the C*CORE microprocessor access;
Be provided with the commands buffer that is used to latch the read/write operation instruction and data between described CLB bus and the equipment, described commands buffer adopts the first in first out storage queue of the secondary degree of depth, be provided with first order command storage unit in this commands buffer, this first order command storage unit comprises: be used to identify whether have the first order significance bit V that waits for the information that is performed in the first order command storage unit
1, be used for the identification access attribute first the sign memory block RW
1, the control operation data bit width the first bit wide memory block SZ
1, be used for first address memory block A of memory access address
1, be used to store the first region of data storage D of write data
1Also be provided with second level command storage unit in the described commands buffer, this second level command storage unit comprises: be used to identify second level command storage unit and whether have the second order significance bit V that waits for the information that is performed
2, be used for second of identification access attribute and indicate memory block RW
2, the control operation data bit width the second bit wide memory block SZ
2, be used for second address memory block A of memory access address
2, be used to store the second region of data storage D of write data
2
This commands buffer is configured as follows:
P_rw_b is in write operation state level when bus read or write signal, the this visit of C*CORE microprocessor is a write operation, with bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz[1:0] and bus operation address signal p_addr[31:0] deposit in respectively first the sign memory block RW
1, the first bit wide memory block SZ
1With first address memory block A
1,
With the first order significance bit V
1Be changed to effectively, simultaneously, with total line write transactions data p_data_out[31:0] deposit the first region of data storage D in
1, and commands buffer sends effective bus operation answer signal p_ta_b and bus read or write signal p_rw_b respectively to described C*CORE microprocessor and equipment,
After the C*CORE microprocessor received bus operation answer signal p_ta_b, the C*CORE microprocessor finished this write operation, and commands buffer continues the write operation of control to equipment,
When commands buffer receives the answer signal that returns from equipment, commands buffer finishes this write operation that equipment is carried out;
P_rw_b is in read operation state level when bus read or write signal, the this visit of C*CORE microprocessor is read operation, with bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz[1:0] and bus operation address signal p_addr[31:0] deposit in respectively first the sign memory block RW
1, the first bit wide memory block SZ
1With first address memory block A
1,
With the first order significance bit V
1Be changed to effectively, simultaneously, and commands buffer sends bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz[1:0 to described equipment] and bus operation address signal p_addr[31:0], the C*CORE microprocessor is waited for the answer signal of this read operation
When equipment to commands buffer echo reply signal, read operation is this time finished, commands buffer sends bus operation answer signal p_ta_b to the C*CORE microprocessor, and the C*CORE microprocessor finishes this read operation that equipment is carried out after receiving bus operation answer signal p_ta_b.
When commands buffer is carried out the i.e. first order significance bit V of write operation to equipment
1Effectively and after the C*CORE microprocessor receives bus operation answer signal p_ta_b, will be from the new bus read or write signal p_rw_b of described C*CORE microprocessor, new bus operation data bit width signal p_tsiz[1:0] and new bus operation address signal p_addr[31:0] deposit second respectively in and indicate memory block RW
1, the second bit wide memory block SZ
1With second address memory block A
1
Finishing when described write operation visit is the answer signal that the commands buffer equipment of receiving returns, and order significance bit V this moment first
1Invalid, more corresponding information reproduction in the command storage unit of the second level is arrived in the corresponding zone of first order command storage unit, simultaneously the first order significance bit V
1Be changed to effectively the second order significance bit V
2It is invalid to be changed to.
The present embodiment foregoing specific explanations and the course of work are as follows.
The definition of CLB bus coherent signal:
P_treq_b, the bus operation request signal, low level is effective, shows that when effective CCORE is carrying out a bus operation request.Only p_ta_b or p_tea_b effectively or p_tbusy_b invalid in, this request just can be accepted and initiate.
P_ta_b, the bus operation answer signal, low level is effective, shows that when effective equipment finished a bus operation.
P_tea_b, the bus operation answer signal of makeing mistakes, low level is effective, shows that when effective equipment makes mistakes when carrying out current bus operation, and the current current period that operates in finishes in the mode of mistake.
P_tbusy_b, bus busy signal, low level is effective, shows that when effective CCORE is carrying out a bus operation.
P_rw_b, bus read or write signal is accepted concurrent time-out in current bus operation request, and specifying this operation is a read operation (p_rw_b is for high) or write operation (p_rw_b is low).
P_tsiz[1:0], bus operation data bit width signal, be accepted concurrent time-out in current bus operation request, specifying this operation is one 32 bit manipulation (p_tsiz is 00), 16 bit manipulations (p_tsiz is 10) or 8 bit manipulations (p_tsiz is 01), and p_tsiz is 11 undefined.
P_addr[31:0], the bus operation address signal is accepted concurrent time-out in current bus operation request, specifies the address of this operation.
P_data_out[31:0], total line write transactions data are write operation and when being accepted and initiating in current bus operation request, the data of specifying this write operation to transmit.
Stipulate that in the total line write transactions agreement of CLB the C*CORE microprocessor divides two processes to finish to the write operation of CLB bus, shown in accompanying drawing one:
First process C*CORE microprocessor sends write order to the CLB bus and comprises: bus operation request signal p_treq_b, bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz, bus operation address signal p_addr.First clock period that is combined in of these four signals has constituted a special state, has sent a write order to bus exactly.
Second process, the C*CORE microprocessor sends total line write transactions data p_data_out to the CLB bus.Wherein the first step only continues a clock period, and second step can continue one or more clock period, and this depends on the response speed of accessed equipment.The complement mark in second step is the bus operation answer signal p_ta_b that accessed equipment returns.If accessed equipment can just be finished write operation at second period, then should immediately bus operation answer signal p_ta_b be driven and be low level, otherwise drive bus operation answer signal p_ta_b is high level and maintenance always, finish up to this write operation, just bus operation answer signal p_ta_b being driven is low level; In second step, the C*CORE microprocessor remains unchanged to total line write transactions data p_data_out that the CLB bus sends.Shown in accompanying drawing two.
Make mistakes one of answer signal p_tea_b and three signals of bus busy signal p_tbusy_b of expression bus operation answer signal p_ta_b, bus operation satisfy that requirement can start this write operation among the figure in accompanying drawing one and accompanying drawing two centre circles, and arrow is represented the time that bus operation next time can start.
Equipment bus operation answer signal p_ta_b is driven for high level during this period of time in, the answer signal of C*CORE microprocessor waiting facilities can't carry out follow-up bus operation, is called latent period.In fact from second period, all that this write operation is required information of C*CORE microprocessor all send on the CLB bus, and the action that the follow-up clock period does only is to wait for; Therefore, commands buffer can latch this write operation of C*CORE microprocessor and timely echo reply signal, and the follow-up read-write operation that other equipment are carried out can carry out simultaneously with this write operation fully.Commands buffer is arranged in equipment (as figure three Device2) and CLB bus at a slow speed, in to the Device2 write operation, deposits this write order in commands buffer, simultaneously at once to C*CORE microprocessor echo reply signal; Write operation to Device2 is then carried out by commands buffer replaced C * CORE microprocessor.The C*CORE microprocessor can begin next bus access immediately and not need to do any wait like this.If next bus operation is the read and write access to miscellaneous equipment, then these visits can be carried out with before the Device2 write operation being walked abreast.If next bus operation must also be operated Device2, so such operation must wait until that the ongoing write operation to Device2 of commands buffer could begin after finishing, thereby avoids relevant data operations to make a mistake.In actual applications, by software is optimized, under most situations, can guarantee after not the write operation of slow devices can be and then to the read-write operation of same equipment; Thereby can be left in the basket to the latent period of the write operation of this slow devices like this and accelerate overall system efficiency.The connection layout that has increased the C*CORE microprocessor of commands buffer and external unit is commands buffer shown in the red square frame among the figure shown in figure four.After the utility command impact damper, the answer signal of equipment no longer returns to the C*CORE microprocessor but returns to commands buffer.The read data that the equipment of it is noted that returns still is delivered directly on the data bus.
Commands buffer is the first in first out storage queue FIFO of the secondary degree of depth, and its structure is shown in figure five.Be numbered 0 the first behavior first order command storage unit among the figure, first order command storage unit is always stored in new order earlier into; Be numbered 1 the second behavior second level command storage unit, when the first order has effective order, have new order to need storage again, then deposit second level command storage unit in.The territory of respectively storing of commands buffer is described as follows:
1, order significance bit V comprises the first order significance bit V
1With the second order significance bit V
2, the second order significance bit V
1Effectively promptly put 1 and show that first order command storage unit is performed, by the operation of commands buffer control bus, V
2Be 1 to show that second level command storage unit is being waited for and be performed; May there be V
1And V
2All be 0 situation, show that the current command impact damper is maybe needing to carry out without any order, commands buffer is not when applying any control to bus like this.
2, sign memory block RW comprises the first sign memory block RW
1With the second sign memory block RW
2, be used for the identification access attribute and read or write sign, memory bus read or write signal p_ rw_b.
3, bit wide memory block SZ[1:0], comprise the first bit wide memory block SZ
1With the second bit wide memory block SZ
2, visit data width indicator, memory bus service data bit wide signal p_tsiz[1:0].
4, memory block, address A[31:0], comprise first address memory block A
1With second address memory block A
2, be used for the memory access address, memory bus operation address signal p_addr[31:0].
5, region of data storage D[31:0], comprise the first region of data storage D
1With the second region of data storage D
2, be used to store write data, memory bus write operation data p_data_out[31:0]; If RW is that 1 D value can be ignored.
Describe the renewal of commands buffer below in detail and to the control procedure of slow devices.
A, original state, commands buffer are empty, i.e. the first order significance bit V
1With the second order significance bit V
2All be 0.
B, when commands buffer be empty, if the C*CORE microprocessor carries out write operation to equipment, then in first cycle bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz and bus operation address signal p_addr are stored in the corresponding first order command storage unit of commands buffer, do not do any operation to equipment this moment.
C, then with V
1Be changed to 1, first region of data storage that deposits total line write transactions data p_data_out the first order command storage unit of commands buffer in is the D territory, and send effective bus operation answer signal p_ta_b to the C*CORE microprocessor, send the write operation order to equipment simultaneously.The write operation order that commands buffer sends to equipment remains to equipment echo reply signal always and just finishes.When equipment was finished this write operation, to commands buffer echo reply signal, commands buffer was cancelled the write operation that equipment is being carried out in next clock period.
D, when commands buffer be empty, if the C*CORE microprocessor carries out read operation to equipment, then bus read or write signal p_rw_b, bus operation data bit width signal p_tsiz and bus operation address signal p_addr are being stored in the commands buffer first order command storage unit, do not do any operation to equipment this moment.
E, then with the first order significance bit V
1Be changed to 1, send the read operation order to equipment.Commands buffer remains to equipment echo reply signal always and just finishes to the read operation order that equipment sends.When equipment is finished this read operation, to commands buffer echo reply signal, commands buffer is sending effective bus operation answer signal p_ta_b with one-period to the C*CORE microprocessor, and cancels the read operation of equipment being carried out in following one-period.
F, if before the read-write operation that commands buffer is being carried out equipment is finished, i.e. V
1Be 1, the C*CORE microprocessor has new visit to carry out same equipment again, and then new order will be stored in second command storage unit, waits for that the ongoing visit of first command storage unit just can be performed after finishing.
G, the visit of equipment being carried out when commands buffer finish, and promptly equipment is to commands buffer echo reply signal, and first command storage unit need be updated.If order significance bit V this moment second
2Be changed to 0, then with V
1Put 0, commands buffer switches to state A; If V
2Be 1, then all the elements (comprising the V position) with second level command storage unit all copy to the first order, and initiate new operation to equipment immediately, simultaneously with V
2Put 0.If new operation is a write operation, then switch to state C; If new operation is read operation, then switch to state E.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (3)
1. be used for the device of write operation in the CLB bus, this device comprises:
Microprocessor, this microprocessor sends information according to CLB bus protocol equipment in system;
The CLB bus is used for according to CLB bus protocol transmission information between microprocessor and equipment;
Be used for equipment for microprocessor access;
It is characterized in that: be provided with the commands buffer that is used to latch the read/write operation instruction and data between described CLB bus and the equipment, be provided with first order command storage unit in this commands buffer, this first order command storage unit comprises: be used to identify the first order significance bit (V that whether has the information that need be performed in the first order command storage unit
1), be used for the identification access attribute first the sign memory block (RW
1), the first bit wide memory block (SZ of control operation data bit width
1), be used for the first address memory block (A of memory access address
1), be used to store the first region of data storage (D of write data
1);
This commands buffer is configured as follows:
When bus read or write signal (p_rw_b) is in write operation state level, microprocessor this visit is a write operation, deposits bus read or write signal (p_rw_b), bus operation data bit width signal (p_tsiz[1:0]) and bus operation address signal (p_addr[31:0]) in first sign memory block (RW respectively
1), the first bit wide memory block (SZ
1) and first address memory block (A
1),
With the first order significance bit (V
1) be changed to effectively, simultaneously, deposit total line write transactions data (p_data_out[31:0]) in first region of data storage (D
1), and commands buffer sends effective bus operation answer signal (p_ta_b) and bus read or write signal (p_rw_b) respectively to described microprocessor and equipment,
After microprocessor received bus operation answer signal (p_ta_b), microprocessor finished this write operation, and commands buffer continues the write operation of control to equipment,
When commands buffer receives the answer signal that returns from equipment, commands buffer finishes this write operation that equipment is carried out;
When bus read or write signal (p_rw_b) is in read operation state level, microprocessor this visit is read operation, deposits bus read or write signal (p_rw_b), bus operation data bit width signal (p_tsiz[1:0]) and bus operation address signal (p_addr[31:0]) in first sign memory block (RW respectively
1), the first bit wide memory block (SZ
1) and first address memory block (A
1),
With the first order significance bit (V
1) be changed to effectively, simultaneously, and commands buffer sends bus read or write signal (p_rw_b), bus operation data bit width signal (p_tsiz[1:0]) and bus operation address signal (p_addr[31:0]) to described equipment, and microprocessor is waited for the answer signal of this read operation
When equipment to commands buffer echo reply signal, read operation is this time finished, commands buffer sends bus operation answer signal (p_ta_b) to microprocessor, and microprocessor receives bus operation answer signal (p_ta_b) back and finishes this read operation that equipment is carried out.
2. device according to claim 1, it is characterized in that: also be provided with second level command storage unit in the described commands buffer, this second level command storage unit comprises: be used to identify second level command storage unit and whether have the second order significance bit (V that waits for the information that is performed
2), be used for second of identification access attribute and indicate memory block (RW
2), the second bit wide memory block (SZ of control operation data bit width
2), be used for the second address memory block (A of memory access address
2), be used to store the second region of data storage (D of write data
2);
This commands buffer also is configured to, when commands buffer is carried out the i.e. first order significance bit (V of write operation to equipment
1) effectively and after microprocessor receives bus operation answer signal (p_ta_b), will deposit second respectively in from the new bus read or write signal (p_rw_b) of described microprocessor, new bus operation data bit width signal (p_siz[1:0]) and new bus operation address signal (p_addr[31:0]) and indicate memory block (RW
1), the second bit wide memory block (SZ
1) and second address memory block (A
1);
Finishing when described write operation visit is the answer signal that the commands buffer equipment of receiving returns, and order significance bit (V this moment first
1) invalid, more corresponding information reproduction in the command storage unit of the second level is arrived in the corresponding zone of first order command storage unit, simultaneously the first order significance bit (V
1) be changed to effectively the second order significance bit (V
2) be changed to invalid.
3. device according to claim 1 and 2 is characterized in that: described commands buffer adopts the first in first out storage queue of the secondary degree of depth.
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| CN 201010156996 CN101894084B (en) | 2010-04-13 | 2010-04-13 | Device for writing operation in CLB bus |
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|---|---|---|---|
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| CN101894084B CN101894084B (en) | 2012-06-27 |
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| CN103116551B (en) * | 2013-01-31 | 2016-05-04 | 苏州国芯科技有限公司 | Be applied to the NorFLASH store interface module of CLB bus |
| CN105205027A (en) * | 2015-09-14 | 2015-12-30 | 江苏金智科技股份有限公司 | Bus data access method and device for power distribution network terminal, as well as power distribution network terminal equipment |
| CN105205027B (en) * | 2015-09-14 | 2018-08-21 | 江苏金智科技股份有限公司 | Bus data access method, device and the power distribution network terminal equipment of power distribution network terminal |
| CN105786758A (en) * | 2016-02-26 | 2016-07-20 | 同济大学 | Processor device with data caching function and data read-write method of processor device |
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