CN101887905B - Image display system and manufacturing method thereof - Google Patents
Image display system and manufacturing method thereof Download PDFInfo
- Publication number
- CN101887905B CN101887905B CN200910136346.3A CN200910136346A CN101887905B CN 101887905 B CN101887905 B CN 101887905B CN 200910136346 A CN200910136346 A CN 200910136346A CN 101887905 B CN101887905 B CN 101887905B
- Authority
- CN
- China
- Prior art keywords
- patterned
- district
- layer
- semiconductor layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to an image display system comprising a display panel and a manufacturing method thereof, the display panel comprises a substrate with a first area, a second area and a third area, a first patterned semiconductor layer is arranged on the first area of the substrate, a first insulating layer is covered on the first patterned semiconductor layer and the first area, the second area and the third area of the substrate, a second patterned semiconductor layer is respectively arranged on the first insulating layer of the first area and the third area, a second insulating layer is covered on the second patterned semiconductor layer and the first insulating layer, and a patterned conductive layer is arranged on the second insulating layer, wherein the first area constitutes a first thin film transistor, and the third area constitutes a second thin film transistor.
Description
Technical field
The present invention, relevant for a kind of image display system that comprises display floater, is particularly to a kind of capacitance arrangement design and manufacture method thereof of organic LED display panel.
Background technology
In recent years, Organic Light Emitting Diode (organic light emitting diode, abbreviation OLED) display has been widely used in display, wherein in active type matrix organic led (active matrixOLED, abbreviation AMOLED) in display, usually utilize thin-film transistor (thin film transistor is called for short TFT) as the switch element of pixel region and the driving element of light-emitting component.
Refer to Fig. 1, it shows the circuit diagram of a pixel cell 100 in known active type matrix organic led (AMOLED) display.There is driving thin-film transistor (driving TFT) 112 for driving light-emitting component 116 in pixel cell 100, Organic Light Emitting Diode (OLED) for example, switching thin-film transistor (switching TFT) 106 is for switching the state of pixel cell, and storage capacitors 108 is for the store images data.The grid of switching thin-film transistor 106 is coupled to scan line 102, and its drain electrode couples with data wire 104, and source electrode couples with an end of storage capacitors and the grid of driving thin-film transistor 112.In addition, the other end of storage capacitors 108 couples via electric capacity line 110 and power line 114, and couples with the source electrode that drives thin-film transistor 112.The two ends of light-emitting component 116 are connected to respectively anode 118 and negative electrode 120, drive the drain electrode of thin-film transistor 112 to couple with the anode 118 of light-emitting component 116.
Usually the thin-film transistor in the AMOLED display is in order to coordinate the heat resisting temperature of glass substrate, use low temperature polycrystalline silicon (low temperature polysilicon, be called for short LTPS) its active layer of fabrication techniques, it has advantages of high carrier transport factor and high drive circuit integrated level and low-leakage current.Yet, except above-mentioned advantage, the AMOLED display more needs high storage capacitors and high aperture, to meet the demand of display.
In view of this, industry is needed a kind of capacitance arrangement design of organic LED display panel badly, and it can meet the demand of high storage capacitors and high aperture.
Summary of the invention
The invention provides a kind of image display system that comprises display floater, this display floater comprises: substrate has the firstth district, Second Region Ji 3rd district, the first patterned semiconductor layer is arranged on the firstth district of substrate, the first insulating barrier is covered in the firstth district of the first patterned semiconductor layer and substrate, in Second Region Ji 3rd district, the second patterned semiconductor layer is arranged on first insulating barrier in the first district Ji 3rd district, the second insulating barrier is covered on the second patterned semiconductor layer and the first insulating barrier, and patterned conductive layer is arranged on the second insulating barrier, wherein be positioned at first patterned semiconductor layer in the firstth district, the first insulating barrier and the second patterned semiconductor layer form the first film transistor, be positioned at second patterned semiconductor layer in the 3rd district, the second insulating barrier and patterned conductive layer form the second thin-film transistor.
In addition, the present invention also provides a kind of manufacture method of image display system, comprise and form a display floater, comprise: substrate is provided, there is the firstth district, Second Region Ji 3rd district, form the first patterned semiconductor layer on the firstth district of substrate, forming the first insulating barrier is covered on the first patterned semiconductor layer and substrate, form the second patterned semiconductor layer on first insulating barrier in the first district Ji 3rd district, forming the second insulating barrier is covered on the second patterned semiconductor layer, and form patterned conductive layer on second insulating barrier in the first district Ji 3rd district, wherein be positioned at first patterned semiconductor layer in the firstth district, the first insulating barrier and the second patterned semiconductor layer form the first film transistor, be positioned at second patterned semiconductor layer in the 3rd district, the second insulating barrier and patterned conductive layer form the second thin-film transistor.
For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, below coordinate appended graphicly, be described in detail below.
The accompanying drawing explanation
Fig. 1 is the circuit diagram that shows a pixel cell in known active type matrix organic led (AMOLED) display;
Fig. 2 is the floor map of demonstration according to a pixel region of the organic LED display panel of one embodiment of the invention;
Fig. 3 is the generalized section shown along the hatching 3-3 ' in Fig. 2;
Fig. 4 A-4F shows the generalized section that forms the organic LED display panel of Fig. 3 according to the manufacture method of one embodiment of the invention;
Fig. 5 is the floor map of demonstration according to a pixel region of the organic LED display panel of another embodiment of the present invention;
Fig. 6 is the generalized section shown along the hatching 5-5 ' in Fig. 5;
Fig. 7 is the configuration schematic diagram shown according to the image display system that comprises display floater of one embodiment of the invention.
The main element symbol description
100～pixel cell; 102,202～scan line; 104,204～data wire; 106,206～switching thin-film transistor; 108,208～electric capacity; 110,210～electric capacity line; 112,212～driving thin-film transistor; 114～power line; 116～light-emitting component; 118～anode; 120～negative electrode; 400,600～inferior pixel region; 410th～the first district; 420～Second Region; 430～3rd district; 500～substrate; 502,504～the first dielectric layers; 508～the first insulating barriers; 516,518～the second insulating barriers; 520,530～the second dielectrics layer by layer; 505,506,506a～first patterned semiconductor layer; 509,510,512,514,514a, 514b, 514c, 710,712～the second patterned semiconductor layer; 402a, 402b, 402c～patterned conductive layer; The ledge of 402d～patterned conductive layer; 532,534,536,538,540～contact hole; 541,544,548～mask; 542～P type heavy doping step; 546～N-type light dope step; 550～N-type heavy doping step; 560a～second patterned electrode layer; 560b～first patterned electrode layer; 560c～the 3rd patterned electrode layer; 20～display floater; 30～image display system; 40～control unit; 50～electronic installation.
Embodiment
Capacitance arrangement (layout) design that the present invention is directed to organic LED display panel is improved, and to increase the storage capacitors of display floater, and improves aperture opening ratio.
Refer to Fig. 2, it shows according to the floor map of a pixel region 400 of the organic LED display panel of one embodiment of the invention, at pixel region 400, along hatching 3-3 ', can be divided into the first district 410, Second Region 420 Ji tri-districts 430.In the present embodiment, drive thin-film transistor to be positioned in the first district 410, there is electric capacity on Second Region 420, switching thin-film transistor is positioned in the 3rd district 430, wherein the patterned conductive layer 402b in the patterned conductive layer 402b of the patterned conductive layer 402a in the first district 410, Second Region 420 and the 3rd district 430 forms the upper electrode layer of electric capacity, and the planar configuration of this upper electrode layer is as shown in the 402a and 402b of Fig. 2.Capacitance arrangement design by the present embodiment, can make the storage capacitors of organic LED display panel of the present invention increase and increase aperture opening ratio.
Then, refer to Fig. 3, it is the generalized section shown along Fig. 2 section line 3-3 '.Being coated with the first dielectric layer 502 and 504, the first patterned semiconductor layer 506 and 506a on substrate 500 is arranged on first dielectric layer 502 and 504 in the first district 410.Cover the first insulating barrier 508 on the first patterned semiconductor layer 506 and 506a and the first dielectric layer 502 and 504, on first insulating barrier 508 in the first district 410, Second Region 420 Ji tri-districts 430, form respectively the second patterned semiconductor layer 510,512,514,514a, 514b and 514c.Then, form the second insulating barrier 516 and 518 on the second patterned semiconductor layer 510,512,514,514a, 514b and 514c.Then form respectively patterned conductive layer 402a, 402b and 402c on second insulating barrier 516 and 518 in the first district 410, Second Region 420 Ji tri-districts 430, with the electric capacity of the driving thin-film transistor, the first district 410 and the Second Region 420 that form the first district 410 and the switching thin-film transistor in the 3rd district 430.
It should be noted that in the display floater of Fig. 3 to there is patterned conductive layer 402a on the grid 510 of the driving thin-film transistor in the first district 410, therefore can form extra electric capacity in the first district 410.In addition, in this embodiment, the second patterned semiconductor layer 514a in the second patterned semiconductor layer 512 Yu tri-districts 430 of Second Region 420 is the semiconductor layer (in the present embodiment, being for example the heavily doped polysilicon layer of N-type) with identical first conductivity type, and is connected to each other.
Then, refer to Fig. 4 A-4F, it is the manufacture method shown according to one embodiment of the invention, forms the section flow chart of the display floater of Fig. 3.In Fig. 4 A, at first substrate 500 is provided, be for example glass substrate or other bendable plastic substrates, form two-layer the first dielectric layer 502 and 504 on substrate 500, then on first dielectric layer 504 in the first district 410, form the first patterning intrinsic semiconductor layer 505.
Consult Fig. 4 B, cover the first insulating barrier 508 on the first patterning intrinsic semiconductor layer 505 and the first dielectric layer 504, and carry out Patternized technique on first insulating barrier 508 in the first district 410, Second Region 420 Ji tri-districts 430, to form the second patterning intrinsic semiconductor layer 509.Then, form mask 541 on the second patterning intrinsic semiconductor layer 509, and the first patterning intrinsic semiconductor layer 505 is carried out to heavy doping technique 542, can also can be N-type heavy doping for the heavy doping of P type.
Consult Fig. 4 B and 4C, form heavily doped source/drain regions 506a and polysilicon channel region 506 in the first district 410 after, mask 541 is removed, then in 410 Ji tri-districts 430, the firstth district, form mask 544, the second patterning intrinsic semiconductor layer 509 is carried out to the light dope 546 of one first conductivity, wherein the first conductivity is N-type or P type.Then, consult Fig. 4 D, in the first district 410, Second Region 420 Ji tri-districts 430 form lightly doped the second patterned semiconductor layer 514b of the first conductivity.Then the upper mask 548 that forms of the second patterned semiconductor layer 514b in tri-districts 430, carry out the first conductivity heavy doping 550, in the present embodiment the first conductivity, can be N-type or P type.
Consult Fig. 4 E, remove the mask 548 of Fig. 4 D, and form the second patterned semiconductor layer 510 of the first conductivity types in the first district 410, as the grid of the driving thin-film transistor in the first district 410; Form the second patterned semiconductor layer 512 of the first conductivity type on Second Region 420, as the lower electrode layer of the electric capacity of Second Region 420; Form the source/drain regions of the lightly doped second patterned semiconductor layer 514b of the heavily doped second patterned semiconductor layer 514a of the first conductivity and 514c and the first conductivity as the switching thin-film transistor in the 3rd district 430 in tri-districts 430, and form unadulterated polysilicon channel region 514.Then, form two-layer the second insulating barrier 516 and 518 and cover the second patterned semiconductor layer 510,512,514,514a, 514b and 514c.
Consult Fig. 4 F, form respectively patterned conductive layer 402a, 402b and 402c (for example metal) on the second insulating barrier 518, wherein the patterned conductive layer 402a in the first district 410 forms an extra electric capacity with the second patterned semiconductor layer 510 that drives thin-film transistor, the patterned conductive layer 402b of Second Region 420 as the patterned conductive layer 402c in upper electrode layer ， tri-districts 430 of electric capacity as the grid of switching thin-film transistor.In this embodiment, switching thin-film transistor is two grid thin-film transistor
Finally consult again Fig. 3, form the first contact hole 532 in the first insulating barrier 508, the second insulating barrier 516 and the 518 and second dielectric layer 520 and 530; Form the second contact hole 534 in the second dielectric layer 520 and 530; Form the 3rd contact hole 536 in the second insulating barrier 516 and the 518 and second dielectric layer 520 and 530 after, then, form a patterned electrode layer 560a and 560b (for example metal) on this second dielectric layer 520 and 530, patterned electrode layer 560a is electrically connected via the second patterned semiconductor layer 514a in the 3rd contact hole 536 Yu tri-districts 430; Patterned electrode layer 560b is electrically connected via the second patterned semiconductor layer (source/drain region) 514a in patterned electrode layer 402b Ji tri-districts 430 of the source area 506a in the first contact hole 532 and the second contact hole 534 and the first district 410, Second Region 420.Because second thin-film transistor in the present embodiment 3rd district is the first conductivity (N-type (N-type)) thin-film transistor, and the second patterned semiconductor layer 512 is the first conductivity (N-type) heavy doping, and Second Region 420 Ji tri-district's 430 second patterned semiconductor layer 512,514a, 514b and 514c are connected, thereby can drive the second thin-film transistor by patterned electrode layer 560b, do not need extra electrode.Thus, can effectively increase pixel aperture ratio.
Then, refer to Fig. 5, it is the floor map of demonstration according to a pixel region 600 of the organic LED display panel of another embodiment of the present invention.The difference of the electric capacity planar configuration of Fig. 5 and Fig. 2 is that the metal level of the electric capacity of Fig. 5 comprises that a protuberance 402d extends to the 3rd district 430.
Refer to Fig. 6, it shows the profile along Fig. 5 section line 5-5 '.The difference of Fig. 6 and Fig. 3 is that the lower electrode layer 712 of the electric capacity of the grid 710 of driving thin-film transistor in the first district 410 and Second Region 420 is all the second patterned semiconductor layer of the first conductivity (as the heavy doping of P type).The polysilicon layer that the second patterned semiconductor layer 514a in ， tri-districts 430 is the second conductivity (as N-type heavy doping) in addition, its second patterned semiconductor layer 712 with first conductivity (heavy doping of P type) of Second Region 420 is not connected.Therefore, also need to form the 4th contact hole 538 in second insulating barrier 516 in tri-districts 430 and the 518 and second dielectric layer 520 and 530, the second patterned semiconductor layer 514a with the switching thin-film transistor that exposes the 3rd district 430, and in the 4th contact hole 538 filling pattern polarizing electrode layer 560c, make between the switching thin-film transistor in electric capacity Yu tri-districts 430 of Second Region 420 and produce and be electrically connected.Please consult again Fig. 5, on the second dielectric layer 530 of Second Region 420, a contact hole 540 is also additionally arranged, and patterned electrode layer (not being illustrated in Fig. 5) is electrically connected with pattern conductive utmost point layer 560c through this contact hole 540.
Each above-mentioned dielectric layer 502, 504, 520 and 530, and each insulating barrier 508, 516 and 518 can be silicon nitride, silica or aforesaid combination, in addition, the first above-mentioned patterned semiconductor layer 506 and 506a and the second patterned semiconductor layer 510, 710, 512, 712, 514, 514a, 514b and 514c are formed by different crystallization process, wherein the first patterned semiconductor layer can be formed by non-laser crystallization technology, for example solid phase crystallization method, metal induced crystallization method, metal induced side crystallization method, electric field strengthens metal induced side crystallization method, or electric field strengthens the rapid thermal annealing method, the second patterned semiconductor layer can be formed by the laser crystallization technology, quasi-molecule laser annealing method for example.
Although in the above-described embodiments, it is example explanation the present invention that the P type of take drives thin-film transistor and N-type switching thin-film transistor, have and usually know that the knowledgeable is when understanding in this technical field, in organic LED display panel of the present invention, also can use N-type to drive thin-film transistor and P type switching thin-film transistor, and the combination of the N-type of each polysilicon layer or P type doping is not limited to above-described embodiment, can be depending on the circumstances or the needs of the situation Selection and Constitute in addition.
In sum, organic LED display panel of the present invention utilizes polysilicon layer as the grid that drives thin-film transistor, and form metal level in the grid top that drives thin-film transistor, to form extra electric capacity, and increase storage capacitors and the aperture opening ratio of display floater by the configuration design of the upper electrode layer of electric capacity.In addition, organic LED display panel of the present invention also utilizes non-laser crystallization technology to form the active layer that drives thin-film transistor, and utilizes the active layer of laser crystallization technology formation switching thin-film transistor, improves by this Luminescence Uniformity of display floater.
Please refer to Fig. 7, show the configuration schematic diagram of image display system of the present invention, wherein image display system is for example an electronic installation 50 or a display unit 30.Display unit 30 comprises a display floater 20, and display unit 30 is for example an organic light emitting diode display, and display floater 20 is an organic LED panel.In general, display unit 30 can be the part of an electronic installation 50, and electronic installation 50 also comprises an input unit 40, with display unit 30, couples, and wherein input unit 40 signal transmissions are to display floater 20, so that display floater 20 shows images.Image display system 50 can be for example mobile phone, digital still camera, PDA (personal digital assistant), notebook computer, desktop computer, TV, vehicle display or Portable DVD projector.
Although the present invention has disclosed preferred embodiment as above; so it is not in order to limit the present invention, any those who are familiar with this art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (10)
1. an image display system comprises:
Display floater, this display floater comprises:
Substrate, have the firstth district, Second Region Ji 3rd district;
The first patterned semiconductor layer, be arranged on this firstth district of this substrate;
The first insulating barrier, be covered in this firstth district, this Second Region and Gai 3rd district of this first patterning semiconductive layer and this substrate;
The second patterned semiconductor layer, be arranged at respectively on this first insulating barrier in this firstth district and Gai 3rd district;
The second insulating barrier, be covered on this second patterned semiconductor layer and this first insulating barrier; And
Patterned conductive layer, be arranged on this second insulating barrier, and be positioned at this firstth district and this Second Region,
This first patterned semiconductor layer, this first insulating barrier and this second patterned semiconductor layer that wherein are positioned at this firstth district form the first film transistor, this second patterned semiconductor layer, this second insulating barrier and this patterned conductive layer that are positioned at Gai 3rd district form the second thin-film transistor, this patterned conductive layer that is positioned at this Second Region forms the upper electrode layer of an electric capacity, and this patterned conductive layer that is positioned at this firstth district forms the upper electrode layer of an extra capacitor.
2. image display system as claimed in claim 1, wherein this second patterned semiconductor is arranged on this first insulating barrier of this Second Region, this second insulating barrier is covered in this second patterned semiconductor layer of this Second Region, and this patterned conductive layer is arranged on this second insulating barrier of this Second Region, this second patterned semiconductor layer, this second insulating barrier and this patterned conductive layer that wherein are positioned at this Second Region form electric capacity.
3. image display system as claimed in claim 2, wherein be positioned at this patterned conductive layer in this firstth district and the patterned conductive layer of this Second Region and be connected to each other, and this patterned conductive layer extension of this Second Region is arranged to this second patterned semiconductor layer in Gai 3rd district.
4. image display system as claimed in claim 2, this second pattern semiconductor layer that wherein is positioned at this Second Region and Gai 3rd district is the first conductivity, this second patterning semiconductive layer that wherein is positioned at this Second Region and Gai 3rd district is connected to each other.
5. image display system as claimed in claim 4 also comprises:
The first dielectric layer, be arranged between this substrate and this first patterned semiconductor layer and this first insulating barrier;
The second dielectric layer, be covered on this patterned conductive layer;
The first patterned electrode layer, be arranged on this second dielectric layer, and by this first patterned semiconductor layer in the first contact hole and the second contact hole and this firstth district and this patterned conductive layer of this Second Region, be electrically connected respectively; And
The second patterned electrode layer, be arranged on this second dielectric layer, and be electrically connected by this second patterned semiconductor layer in the 3rd contact hole and Gai 3rd district.
6. image display system as claimed in claim 2, this second patterned semiconductor layer that wherein is positioned at this firstth district and this Second Region is the first conductivity type, and this second patterned semiconductor layer in Gai 3rd district is the second conductivity type.
7. image display system as claimed in claim 6 also comprises:
The first dielectric layer, be arranged between this substrate and this first patterned semiconductor layer and this first insulating barrier;
The second dielectric layer, be covered on this patterned conductive layer;
The first patterned electrode layer, be arranged on this second dielectric layer, and by this first patterned semiconductor layer in the first contact hole and the second contact hole and this firstth district and this patterned conductive layer of this Second Region, be electrically connected respectively;
The second patterned electrode layer, be arranged on this second dielectric layer, and be electrically connected by this second patterned semiconductor layer in the 3rd contact hole and Gai 3rd district; And
The 3rd patterned electrode layer, be arranged on this second dielectric layer, and be electrically connected by this second patterned semiconductor layer in the 4th contact hole and Gai 3rd district.
8. image display system as claimed in claim 1 also comprises:
Display unit, wherein this display unit comprises this display floater, wherein this display unit is organic light emitting diode display.
9. image display system as claimed in claim 8 also comprises:
Electronic installation comprises:
This display unit; And
Input unit, couple with this display unit;
Wherein this electronic installation is mobile phone, digital still camera, personal digital assistant, notebook computer, desktop computer, TV, vehicle display or Portable DVD player.
10. the manufacture method of an image display system, comprise the formation display floater, and the method comprises:
Substrate is provided, there are the firstth district, Second Region Ji 3rd district:
Form the first patterned semiconductor layer on this firstth district of this substrate;
Form the first insulating barrier, be covered on this first patterned semiconductor layer and this substrate;
Form the second patterned semiconductor layer on this first insulating barrier in this firstth district, this Second Region and Gai 3rd district;
Form the second insulating barrier, be covered on this second patterned semiconductor layer; And
Form patterned conductive layer on this second insulating barrier in this firstth district, this Second Region and Gai 3rd district, and the patterned conductive layer of this firstth district and this Second Region is connected to each other simultaneously;
This first patterned semiconductor layer, this first insulating barrier and this second patterned semiconductor layer that wherein are positioned at this firstth district form the first film transistor, this second patterned semiconductor, this second insulating barrier and this patterned conductive layer that are positioned at this Second Region form electric capacity, this patterned conductive layer that is positioned at this second patterned semiconductor layer, this second insulating barrier and Gai 3rd district in Gai 3rd district forms the second thin-film transistor, and this patterned conductive layer that is positioned at this firstth district forms the upper electrode layer of an extra capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910136346.3A CN101887905B (en) | 2009-05-11 | 2009-05-11 | Image display system and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910136346.3A CN101887905B (en) | 2009-05-11 | 2009-05-11 | Image display system and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101887905A CN101887905A (en) | 2010-11-17 |
| CN101887905B true CN101887905B (en) | 2014-01-01 |
Family
ID=43073722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910136346.3A Active CN101887905B (en) | 2009-05-11 | 2009-05-11 | Image display system and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101887905B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114128062A (en) * | 2019-07-23 | 2022-03-01 | 罗姆股份有限公司 | Semiconductor laser device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4549889B2 (en) * | 2004-05-24 | 2010-09-22 | 三星モバイルディスプレイ株式會社 | Capacitor and light-emitting display device using the same |
| US7535163B2 (en) * | 2006-02-22 | 2009-05-19 | Tpo Displays Corp. | System for displaying images including electroluminescent device and method for fabricating the same |
| US20070236428A1 (en) * | 2006-03-28 | 2007-10-11 | Toppoly Optoelectronics Corp. | Organic electroluminescent device and fabrication methods thereof |
| US7507998B2 (en) * | 2006-09-29 | 2009-03-24 | Tpo Displays Corp. | System for displaying images and method for fabricating the same |
| KR100867926B1 (en) * | 2007-06-21 | 2008-11-10 | 삼성에스디아이 주식회사 | Organic light emitting diode display device and fabrication method of the same |
-
2009
- 2009-05-11 CN CN200910136346.3A patent/CN101887905B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101887905A (en) | 2010-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11264443B2 (en) | Display substrate with light shielding layer and manufacturing method thereof, and display panel | |
| US11574978B2 (en) | Display panel and display apparatus | |
| CN101154346B (en) | System for displaying images and method for fabricating the same | |
| CN107302030B (en) | Display device | |
| WO2017063568A1 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
| US8158986B2 (en) | System for display images and fabrication method thereof | |
| US20080020519A1 (en) | LTPS-LCD Structure and Method for Manufacturing the Same | |
| WO2022179142A1 (en) | Display panel and manufacturing method therefor, and display device | |
| CN100470764C (en) | Two-dimensional display semiconductor structure and producing method thereof | |
| CN109244082B (en) | Display panel, preparation method thereof and display device | |
| CN111755462B (en) | Array substrate and manufacturing method thereof | |
| JP5360756B2 (en) | Organic electroluminescent display device and manufacturing method thereof | |
| KR101425845B1 (en) | Semiconductor device and method of manufacturing the same | |
| CN101887905B (en) | Image display system and manufacturing method thereof | |
| JP6802653B2 (en) | Display device | |
| CN101834189A (en) | Image display system | |
| CN110729312A (en) | Display substrate, preparation method thereof and display device | |
| CN101872779B (en) | Image display system and manufacturing method thereof | |
| CN105633098A (en) | Drive backboard and preparation method and application thereof | |
| CN110649003A (en) | Semiconductor substrate, array substrate, inverter circuit, and switching circuit | |
| CN215771149U (en) | Display substrate and display panel | |
| US20240138192A1 (en) | Display panel and display apparatus | |
| US20240138191A1 (en) | Display panel and display apparatus | |
| CN100407438C (en) | Electroluminescent display element and manufacturing method thereof | |
| CN111146210A (en) | Array substrate, preparation method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: QIMEI ELECTRONIC CO LTD Free format text: FORMER OWNER: TONGBAO OPTOELECTRONICS CO., LTD. Effective date: 20131129 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C53 | Correction of patent of invention or patent application | ||
| CB02 | Change of applicant information |
Address after: Hsinchu Science Park, Taiwan, China Applicant after: INNOLUX DISPLAY CORP. Address before: Miaoli County, Taiwan, China Applicant before: CHI MEI OPTOELECTRONICS CORP. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: QIMEI ELECTRONIC CO LTD TO: INNOLUX DISPLAY CORPORATION |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20131129 Address after: Miaoli County, Taiwan, China Applicant after: CHI MEI OPTOELECTRONICS CORP. Address before: Hsinchu science industry zone, Taiwan, China Applicant before: TOPPOLY OPTOELECTRONICS Corp. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |