CN101867015A - By applying the P-substrate bias and regulating the program current that threshold voltage improves MTJ - Google Patents
By applying the P-substrate bias and regulating the program current that threshold voltage improves MTJ Download PDFInfo
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- CN101867015A CN101867015A CN201010148508A CN201010148508A CN101867015A CN 101867015 A CN101867015 A CN 101867015A CN 201010148508 A CN201010148508 A CN 201010148508A CN 201010148508 A CN201010148508 A CN 201010148508A CN 101867015 A CN101867015 A CN 101867015A
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Abstract
The method of a kind of operation Mram (MRAM) unit comprises: mram cell is set, and this mram cell comprises MTJ (MTJ) device and has the wordline selector of the source-drain path that is connected serially to the MTJ device.Negative substrate bias is connected to the main body of wordline selector, to increase the drive current of wordline selector.Also reduce the threshold voltage of wordline selector.The invention also discloses a kind of by applying the P-substrate bias and regulating the method that threshold voltage improves the program current of MTJ.
Description
The application requires in the U.S. Provisional Application No.61/170 of " the Raising ProgrammingCurrent of Magnetic Tunnel Junctions by Applying P-Sub Bias and AdjustingThreshold Voltage " by name of submission on April 16th, 2009,074 priority, this application is hereby expressly incorporated by reference.
Technical field
The present invention relates generally to memory device, relates in particular to write (programming) of Mram (MRAM) device.
Background technology
Semiconductor storage unit is used at the integrated circuit that is used for electronic application, and it comprises wireless device, TV, mobile phone and personal computing device.Usually known memory device comprises charge storage device, such as dynamic random access memory (DRAM) and flash memory.
The latest development of memory device relates to spintronics, and it is in conjunction with semiconductor technology and magnetic material.The electric charge of electronic spin polarization rather than electronics is used to indicate the state of " 1 " or " 0 ".A kind of such spin electric device is spin-torque transmission (STT) MTJ (MTJ) device 10, as shown in Figure 1.
When the electric current I 2 that applies from fixed bed 16 to free layer 12, electronics is in that 16 direction flows from free layer 12 to fixed bed.Electronics with polarization identical with the direction of magnetization of fixed bed 16 can flow through tunnel layer 14 and enter fixed bed 16.On the contrary, the electronics with polarization different with the magnetization of fixed bed 16 will be reflected (stopping) by fixed bed 16, and will be accumulated in the free layer 12.Finally, the magnetization of free layer 12 becomes parallel with the reversal of magnetism of fixed bed 16, and MTJ device 10 will be in high impedance status.The respective electronic injection that is caused by electric current I 2 is called as less important injection.
In order to eliminate the parasitism load of mram cell, when mram cell was integrated in the MRAM array, wordline selector was used to make unselected mram cell (undo thereon) and source electrode line electricity to isolate.For example, Fig. 2 shows the mram cell that comprises the MTJ device 10 that is connected to wordline selector 20, and it is by word line 22 controls.When MTJ device 10 is selected for when writing or reading, word line 22 is set to logic high, makes that writing/read electric current I can pass through MTJ device 10.For unselected row, word line 22 has been applied in logic low-voltage.Yet the increase of wordline selector 20 has limited the electric current that can flow through MTJ device 10.The write current I of MTJ device 10 is limited by the electric current providing capability of wordline selector 20.In order effectively and reliably MTJ device 10 to be programmed, write current I needs very high.Yet this requires wordline selector 20 very big.The increase that the increase of the size of wordline selector 20 causes the desired chip area of mram cell to use.The requirement that increases the size of wordline selector 20 conflicts with the requirement of the density that increases the MRAM array.Thereby need a solution.
Summary of the invention
According to an aspect of the present invention, the method of a kind of operation Mram (MRAM) unit comprises: mram cell is set, and this mram cell comprises MTJ (MTJ) device and has the wordline selector of the source-drain path that is connected serially to the MTJ device.Back bias voltage is connected to the main body of wordline selector, to increase the drive current of wordline selector.
According to a further aspect in the invention, a kind of method of operating mram cell comprises: mram cell is set, and this mram cell comprises the MTJ device and has the wordline selector of the source-drain path that is connected serially to the MTJ device.This method further comprises: the main body that back bias voltage is connected to wordline selector; Connect wordline selector; And applying in a period of time of back bias voltage, apply the write current of the source-drain path that flows through wordline selector.
The another aspect that also has according to the present invention, a kind of integrated circuit comprises mram cell, this mram cell comprises the MTJ device and has the wordline selector of the source-drain path that is connected serially to the MTJ device.Power supply is connected to the main body of wordline selector and is configured to provide the main body of back bias voltage to wordline selector.
The another aspect that also has according to the present invention, a kind of integrated circuit comprises mram cell, this mram cell comprises the MTJ device and has the wordline selector of the source-drain path that is connected serially to the MTJ device.Wordline selector has the threshold voltage less than about 0.2V.
Favorable characteristics of the present invention is included under the situation that does not require the size that increases wordline selector, increases the driving force of wordline selector.
Description of drawings
For a more complete understanding of the present invention and advantage, the following description that will be carried out in conjunction with the accompanying drawings now as a reference, wherein:
Fig. 1 shows the sectional view of MTJ (MTJ) unit;
Fig. 2 shows the mram cell by wordline selector control;
Fig. 3 shows the MRAM array;
The negative supply of the mram cell and the main body of wordline selector that provides back bias voltage to mram cell and additional nmos device is be provided Fig. 4 A;
Fig. 4 B schematically shows mram cell and the negative supply of back bias voltage to the main body of the wordline selector of mram cell is provided, and wherein, the main body of additional nmos device is applied with the voltage different with back bias voltage;
Fig. 5 A shows the sectional view of wordline selector shown in Fig. 4 A and additional nmos device;
Fig. 5 B shows the sectional view of wordline selector shown in Fig. 4 B and additional nmos device.
Embodiment
Below will describe the manufacturing and the use of embodiments of the invention in detail.Yet, should expect, but embodiment provides a plurality of application invention thoughts that can specialize in multiple specific environment.Above-mentioned specific embodiment is only represented to make and use ad hoc fashion of the present invention, limits the scope of the invention and be not used in.
New Mram (MRAM) circuit is provided.Change and the operation of embodiment are described.Spread all over a plurality of view of the present invention and illustrative examples, similar reference number is used to indicate similar element.
Fig. 3 shows an embodiment, and it comprises a plurality of mram cells 30 that are arranged in a plurality of row (being marked as row 0, row 1, row 2 etc.) and the multiple row (being marked as row 0, row 1, row 2 etc.).Bit line BL (being marked as BL0, BL1, BL2 etc.) and source line SL (being marked as SL0, SL1 etc.) extend at column direction.Extend at line direction in word line WL (being marked as WL0, WL1, WL2 etc.) and source line source polar curve SL (being marked as SL0, SL1 etc.).Should expect that line direction and column direction can exchange, this depends on the direction of watching MRAM array 100.
In the mram cell 30 each all is connected between one of one of bit line BL and source electrode line SL.In the mram cell 30 each includes MTJ (MTJ) 32 and wordline selector (also being called as word line driver) 40, and it can be N type metal oxide semiconductor (MOS) device (transistor).Wordline selector 40 has the source-drain path that is connected serially to the corresponding MTJ device 32 in the same mram cell, thereby when cutting off, wordline selector can make MTJ device 32 and corresponding source electrode line SL isolate or MTJ device 32 is connected to corresponding source electrode line SL.When the read or write operation carried out one of mram cell 30, corresponding wordline selector 40 is switched on, and makes to read or write current I can flow through mram cell 30.Though it is nearer from corresponding source electrode line SL with respect to corresponding bit line BL that Fig. 3 shows wordline selector 40, wordline selector 40 can also be placed to more approaching corresponding bit line BL.
Fig. 4 A schematically shows semiconductor chip 50, wherein, forms the MRAM array 100 shown in Fig. 3.In order to be clearly shown that, only show one of mram cell 30 in MRAM array 100.Yet, about shown in the instruction of mram cell 30 be applicable to other all mram cells 30 in the MRAM array 100.Back bias voltage power supply 52 provides negative substrate bias Vsb main body 42 (also shown in Fig. 5 A) to wordline selector 40.In one embodiment, negative substrate bias Vsb is lower than pact-0.5V, but can also use higher negative voltage.Because negative substrate bias Vsb, the drive current of wordline selector 40 has increased.
Should be appreciated that except MRAM array 100, have on chip 50 that () other integrated circuits for example, the control circuit of MRAM array 100, it comprises logic nmos device and logic PMOS device such as logical circuit.Example logic nmos device 140 has been shown among Fig. 4 A.In one embodiment, logic MOS device 140 is formed directly in the p type substrate, thereby its main body 142 is the part of respective substrate.Thereby negative substrate bias Vsb can directly be applied to the substrate 56 (not shown in Fig. 4 A, with reference to figure 5A) of chip 50.Fig. 5 A shows the sectional view of the circuit shown in Fig. 4 A.As can be seen, device 40 and 140 is shared common substrate 56, thereby when negative substrate bias Vsb was applied to substrate 56, identical negative substrate bias Vsb also was applied to the main body 142 of MOS device 140.
In optional embodiment, as shown in Fig. 4 B and Fig. 5 B, the main body of wordline selector 40 can be isolated with the main body electricity of MOS device 140, thereby can apply different body voltage.For example, the main body 42 that Fig. 4 B shows wordline selector 40 has been applied in negative substrate bias Vsb, and the main body 142 of MOS device 140 has been applied in different voltages simultaneously, and this difference voltage can be higher than, and is equal to or less than negative substrate bias Vsb.In the exemplary embodiment, main body 142 ground connection of MOS device 140.
Fig. 5 B shows the example cross section of the circuit shown in Fig. 4 B.In one embodiment, wordline selector 40 can be formed in the P-trap 60, and they can be by dark N-trap 58 and p type substrate 56 electric insulations.Thereby negative substrate bias Vsb can be applied to the main body 42 of wordline selector 40, but is not applied to some the main body in other MOS devices in the same chip, such as MOS device 140.In optional embodiment (not shown), MOS device 140 can be formed in the P-trap 60 with substrate 56 electric insulations, and MOS device 40 is formed directly in the substrate 56 simultaneously.Similarly, utilize this structure, main body 42 can also be applied in different voltages with 142.
In one embodiment, when being carried out write operation, mram cell 30 only applies negative substrate bias Vsb.When any mram cell 30 not being carried out write operations, for example, carry out read operation, perhaps undo, the main body of wordline selector 40 can be connected to other voltages, for example, electrical ground.In the embodiment shown in Fig. 4 B and Fig. 5 B, negative substrate bias Vsb can also only be applied to the mram cell that is selected for write operation, unit in other unselected unit or unselected row and the unselected row is applied in the voltage ((0V) for example, electrical ground) that is different from negative substrate bias Vsb simultaneously.In order to realize this function, back bias voltage power supply 52 (Fig. 4 A and Fig. 4 B) can comprise a plurality of outputs, and each all is connected to the delegation of wordline selector 40 or the main body of row.Should expect that can exist about how to distinguish the multiple change of body bias between selected/unselected mram cell, selected/unselected row and/or selected/unselected row, this changes still in the scope of embodiments of the invention.
In order further to increase the drive current of wordline selector 40, can reduce the threshold voltage of wordline selector 40.As be known in the art, the drive current of MOS transistor is relevant with (Vgs-Vt), and wherein, Vgs is a gate source voltage, and Vt is a threshold voltage.Especially, when in the saturation region, operating, the drive current of MOS transistor square proportional with (Vgs-Vt).Thereby the reducing of the threshold voltage vt of wordline selector 40 causes its drive current to increase.In one embodiment, the threshold voltage vt of wordline selector 40 is lower than about 0.2V, perhaps even be lower than about 0.1V.
With reference to figure 5A and Fig. 5 B, in one embodiment, reducing and can realizing by the p type impurity concentration that reduces in the channel region 62 of threshold voltage vt regulated at Vt and introduced p type impurity in the doping step.The p type impurity concentration that increases in the channel region 62 can be so that threshold voltage vt increases, and the p type doping content that reduces simultaneously in the channel region 62 can be so that threshold voltage vt reduces.Thereby, need reduce the p type doping content in the channel region 62.In other words, other devices on the chip 50 may need higher threshold voltage.For example, the threshold voltage of MOS device 140 can be higher than about 0.4V, this can by make than channel region 62 channel region 162 more important place doped p type impurity realize.
Embodiments of the invention have a plurality of favorable characteristics.By utilizing negative voltage that the main body of wordline selector is setovered and/or reduce doping content in the main body of wordline selector 40, can increase under the situation that chip area utilizes not requiring, increase the drive current of wordline selector 40.Thereby, can form high density mram array with improved reliability and improved writing speed.
Although described the present invention and advantage thereof in detail, should be appreciated that, can under the situation of purport of the present invention that does not deviate from the claims qualification and scope, make various change, replace and change.And the application's scope is not limited in the specific embodiment of technology, machine, manufacturing, material component, device, method and the step described in this specification.Should understand as those of ordinary skills, by the present invention, being used to of existing or exploitation from now on carry out with according to the essentially identical function of described corresponding embodiment of the present invention or obtain basic identical result's technology, machine, manufacturing, material component, device, method or step can be used according to the present invention.Therefore, claims should be included in the scope of such technology, machine, manufacturing, material component, device, method or step.In addition, every claim constitutes independent embodiment, and the combination of a plurality of claim and embodiment within the scope of the invention.
Claims (12)
1. the method for operation Mram (MRAM) unit, described method comprises:
Described mram cell is set, and described mram cell comprises:
MTJ (MTJ) device; And
Wordline selector comprises the source-drain path that is connected serially to described MTJ device; And
Negative substrate bias is connected to the main body of described wordline selector.
2. method according to claim 1, wherein, described negative substrate bias is lower than about 0.5V.
3. method according to claim 1, wherein, during the write operation of described mram cell, described negative substrate bias is connected to the main body of described wordline selector.
4. the method for operation Mram (MRAM) unit, described method comprises:
Described mram cell is set, and described mram cell comprises:
MTJ (MTJ) device; And
Wordline selector comprises the source-drain path that is connected serially to described MTJ device;
Negative substrate bias is connected to the main body of described wordline selector;
Connect described wordline selector; And
During applying described negative substrate bias, apply the write current of the described source-drain path that flows through described wordline selector.
5. method according to claim 4, wherein, described negative substrate bias is lower than about 0.5V, and described method further comprises: during the read operation of described mram cell, non-negative voltage is connected to the main body of described wordline selector, and wherein, described non-negative voltage is voltage electrical ground.
6. method according to claim 4, wherein, the main body of described wordline selector comprises the P-trap, wherein, dark N-trap is with described P-trap and p type substrate separation, and wherein, described method further comprises makes described p type substrate ground connection; Perhaps
Described wordline selector has the threshold voltage that is lower than about 0.2V.
7. integrated circuit comprises:
Mram (MRAM) unit comprises:
MTJ (MTJ) device; And
Wordline selector comprises the source-drain path that is connected serially to described MTJ device; And
Power supply is connected to the main body of described wordline selector and is used to provide the main body of negative substrate bias to described wordline selector.
8. integrated circuit according to claim 7, wherein, described negative substrate bias is lower than about 0.1V; Perhaps
The main body of described wordline selector is the part of p type substrate; Perhaps
Described wordline selector has the threshold voltage that is lower than about 0.2V.
9. integrated circuit according to claim 7 further comprises:
P type substrate;
Dark N-trap above described p type substrate;
P-trap above described dark N-trap, wherein, described P-trap is by described dark N-trap and described p type substrate electric insulation, and wherein, the main body of described wordline selector is the part of described P-trap; And
With the nmos device of described wordline selector on same chip, wherein, between described nmos device and described p type substrate, there is not well region.
10. integrated circuit according to claim 9, wherein, described p type substrate ground connection; Perhaps
Described wordline selector has the threshold voltage of the threshold voltage that is lower than described nmos device.
11. an integrated circuit comprises:
Mram (MRAM) unit comprises:
MTJ (MTJ) device; And
Wordline selector comprises the source-drain path that is connected serially to described MTJ device, and wherein, described wordline selector has the threshold voltage that is lower than about 0.2V.
12. integrated circuit according to claim 11 further comprises the main body that is connected to described wordline selector and is used for will negative substrate bias offering the main body of described wordline selector,
Wherein, described negative substrate bias is lower than pact-0.5V.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17007409P | 2009-04-16 | 2009-04-16 | |
| US61/170,074 | 2009-04-16 | ||
| US12/687,720 US8270207B2 (en) | 2009-04-16 | 2010-01-14 | Raising programming current of magnetic tunnel junctions by applying P-sub bias and adjusting threshold voltage |
| US12/687,720 | 2010-01-14 |
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| Publication Number | Publication Date |
|---|---|
| CN101867015A true CN101867015A (en) | 2010-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010148508A Pending CN101867015A (en) | 2009-04-16 | 2010-04-14 | By applying the P-substrate bias and regulating the program current that threshold voltage improves MTJ |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105334899A (en) * | 2014-07-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | PMOS transistor repairing circuit and method |
| CN106663465A (en) * | 2015-03-10 | 2017-05-10 | 株式会社东芝 | Nonvolatile semiconductor memory |
| KR101850198B1 (en) * | 2015-11-13 | 2018-04-18 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Rram cell with pmos access transistor |
| CN109817253A (en) * | 2017-11-21 | 2019-05-28 | 上海磁宇信息科技有限公司 | A kind of MRAM chip controlling bulk potential |
| CN109994137A (en) * | 2019-03-20 | 2019-07-09 | 浙江大学 | A kind of no write de-lay method of single tube list resistance random access memory array |
| CN110197680A (en) * | 2018-02-24 | 2019-09-03 | 上海磁宇信息科技有限公司 | A kind of MRAM storage chip using fully- depleted insulating silicon FD-SOI field-effect tube |
| CN113808648A (en) * | 2020-06-11 | 2021-12-17 | 闪迪技术有限公司 | Forming sub-threshold voltages of selectors in cross-point memory arrays |
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| US20070205824A1 (en) * | 2006-03-06 | 2007-09-06 | Srinivas Perisetty | Adjustable transistor body bias circuitry |
| US7515457B2 (en) * | 2006-02-24 | 2009-04-07 | Grandis, Inc. | Current driven memory cells having enhanced current and enhanced current symmetry |
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- 2010-04-14 CN CN201010148508A patent/CN101867015A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7515457B2 (en) * | 2006-02-24 | 2009-04-07 | Grandis, Inc. | Current driven memory cells having enhanced current and enhanced current symmetry |
| US20070205824A1 (en) * | 2006-03-06 | 2007-09-06 | Srinivas Perisetty | Adjustable transistor body bias circuitry |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105334899A (en) * | 2014-07-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | PMOS transistor repairing circuit and method |
| CN106663465A (en) * | 2015-03-10 | 2017-05-10 | 株式会社东芝 | Nonvolatile semiconductor memory |
| CN106663465B (en) * | 2015-03-10 | 2019-07-09 | 东芝存储器株式会社 | Nonvolatile semiconductor memory |
| KR101850198B1 (en) * | 2015-11-13 | 2018-04-18 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Rram cell with pmos access transistor |
| CN109817253A (en) * | 2017-11-21 | 2019-05-28 | 上海磁宇信息科技有限公司 | A kind of MRAM chip controlling bulk potential |
| CN109817253B (en) * | 2017-11-21 | 2020-11-03 | 上海磁宇信息科技有限公司 | MRAM chip for controlling body potential |
| CN110197680A (en) * | 2018-02-24 | 2019-09-03 | 上海磁宇信息科技有限公司 | A kind of MRAM storage chip using fully- depleted insulating silicon FD-SOI field-effect tube |
| CN110197680B (en) * | 2018-02-24 | 2021-11-23 | 上海磁宇信息科技有限公司 | MRAM memory chip adopting fully-depleted silicon-on-insulator FD-SOI field effect transistor |
| CN109994137A (en) * | 2019-03-20 | 2019-07-09 | 浙江大学 | A kind of no write de-lay method of single tube list resistance random access memory array |
| CN113808648A (en) * | 2020-06-11 | 2021-12-17 | 闪迪技术有限公司 | Forming sub-threshold voltages of selectors in cross-point memory arrays |
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Application publication date: 20101020 |