CN101866634B - Display system for displaying code stream and control method - Google Patents
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Abstract
The invention provides a display system for displaying a code stream, which comprises a decoder, a system memory, an image processing circuit, an LCD control circuit and an LCD screen, wherein the system memory comprises a display memory, the LCD control circuit comprises an FIFO buffer, the image processing circuit obtains code stream data decoded by the decode from the system memory and sends the code stream data to the FIFO buffer in the LCD control circuit, the FIFO buffer sends the data into the display memory in the system memory so that the data is used to be displayed on the LCD screen, the FIFO buffer is monitored, and information is fed back to the image processing circuit to control the write-in for the FIFO buffer, thereby the control for the code stream is realized.
Description
[technical field]
The present invention relates to show code stream, particularly a kind of display system and control method to showing that code stream is controlled.
[background technology]
In the embedded product application of media player more and more widely, image size and sharpness also improve constantly, and be also increasingly high to the requirement of display system.
Fig. 1 is the block scheme of display system 100 in the prior art.See also shown in Figure 1ly, said display system 100 comprises demoder 110, system storage 120, image processing circuit 130, the LCD control circuit 140 that includes the FIFO buffer and LCD display 150.At first 110 pairs of demoders show that code stream is that video data stream is decoded; And decoded video data sent in the system storage 120; Said image processing circuit 130 obtains decoded video data and sends in the LCD control circuit 140 from said system storage 120; Said LCD control circuit 140 can be put into FIFO buffer (the First In First Out in it with the video data that receives; Be a kind of data buffer of first in first out) in; Data in the FIFO buffer will and output in the display-memory (abbreviation video memory) on LCD display, to show according to the time reading of data, and in embedded system, video memory also belongs to system storage 120 usually.
And in the prior art shown in Fig. 1; Said image processing circuit 130 will will be stored in the image data taking-up that the decoded device in the said system storage 120 translates with the shortest time; Give said LCD control circuit 140 after treatment, said LCD control circuit 140 also will write display-memory with it as early as possible.In the image playing process, demoder 110, image processing circuit 130 and LCD control circuit 140 are all wanted access system memory 120 like this, cause the access bandwidth of system storage 120 bottleneck to occur.The access bandwidth that improves system storage brings very big spending of hardware, and certain complicacy is arranged technically.
General; When said system storage 120 access bandwidths are not enough; May cause LCD control circuit 140 the content of previous frame not to be write video memory; And said image processing circuit 130 has been given said LCD control circuit 140 image data of next frame, causes said LCD control circuit 140 interframe mistakes; Or within same frame, said LCD control circuit 140 has caused that said FIFO buffer overflows owing to timely the data in the said FIFO buffer in inside are not write video memory.
So in order to improve system memory bandwidth, generally all will adopt the memory device of more speed, more optimal bus arbitration mechanism makes system's storage control circuit and president's circuit become increasingly complex; Also need software engineer's cooperation simultaneously, the storage control circuit that design is more complicated is also developed rational software flow, makes each equipment of system accessing storage device effectively, reduces the instantaneous burden of bus; Even adopt more advanced technology, make hardware system be operated in higher clock frequency and promptly improve the system works frequency.The above method all can cause the lifting of design cost and the prolongation of development time (as shown in Figure 2), and in consumer electronics, cost and development time all are that can product successful factor of crucial importance.
In the image playing process, reliable bandwidth guarantee is provided even so still can not guarantee for said LCD control circuit 140.And in case mistakes such as said FIFO buffer overflows appear in said LCD control circuit 140; General solution is that the current frame that writes video memory is lost; Wait the next frame arrival and write video memory again, can guarantee that like this each frame data that write video memory all is complete and correct.But within a certain period of time,, just may cause a large amount of frames not write video memory, thereby in the image playing process, tangible frame-skipping phenomenon occur by LCD control circuit 140 if bandwidth is very nervous always.
Therefore being necessary to propose a kind of new technical scheme overcomes the problems referred to above.
[summary of the invention]
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit scope of the present invention.
One of the object of the invention is to provide a kind of display system that shows code stream, its monitoring through bit stream data is write, solved image play in because of the system bandwidth problem produces, like a series of problems such as frame-skippings.
Two of the object of the invention is to provide a kind of control method that shows code stream, through the monitoring that bit stream data is write, solved image play in because of the system bandwidth problem produces, like a series of problems such as frame-skippings.
According to an aspect of the present invention; The present invention provides a kind of system that shows code stream; It comprises demoder, include the system storage of display-memory, image processing circuit, the LCD control circuit that includes the FIFO buffer and LCD screen; Said image processing circuit obtains bit stream data behind the said decoder decode to send in the said FIFO buffer in the said LCD control circuit from said system storage; Said FIFO buffer sends in the said display-memory in the said system storage said data being used for and on said LCD screen, plays, wherein
Also comprise a monitoring module and a threshold register in the said LCD control circuit; But said monitoring module is used for monitoring the remaining r/w cell number of said FIFO buffer; But when the r/w cell number of said FIFO buffer less than threshold register in during pre-set threshold; Said LCD control circuit will send first control signal in said image processing circuit; Said image processing circuit receives said first control signal then to be stopped to send bit stream data to said LCD control circuit; But when the r/w cell number of said FIFO buffer during greater than threshold value, said LCD control circuit will send second control signal in said image processing circuit, and said image processing circuit receives said secondary signal then to be continued to send bit stream data to said LCD control circuit.
Further; But but said FIFO buffer comprises the read pointer and the write pointer of r/w cell and record r/w cell read-write state; Corresponding address, each unit; Said write pointer and said read pointer all move to maximum address from the lowest address of said FIFO buffer, and wherein said read pointer moves on the position that said write pointer moved, and deduct the value of said lowest address but the r/w cell total amount of wherein said FIFO buffer is the value of said maximum address.
Further, when writing data, said write pointer adds 1 automatically, and when reading data, said read pointer adds automatic 1; Reach the lowest address of then returning said FIFO buffer behind the maximum address of said FIFO buffer when said write pointer and said read pointer; When the address of said write pointer during greater than the address of said read pointer, but the value and the value that the value that adds the address of read pointer deducts lowest address again that the value of the maximum address of said FIFO buffer are deducted the address of write pointer then draw residue r/w cell number; When the address of write pointer during, but the address that the address of read pointer deducts write pointer is then drawn residue r/w cell number less than the address of read pointer.
Further, when said first control signal is a kind of in low level or the high level, said second control signal is the another kind in low level or the high level.
According to a further aspect in the invention; The present invention provides a kind of control method that shows code stream; Wherein show and be put in the system storage that contains display-memory after code stream is through decoder decode; Image processing circuit obtains decoded demonstration bit stream data and sends in the FIFO buffer in the LCD control circuit from system storage, from said FIFO buffer, read said data and put in the said display-memory to play at display screen, and it comprises:
In said LCD control circuit, threshold register is set; Calculate the number of available cell in the said FIFO buffer; Pre-set threshold in the number of available cell in the said FIFO buffer and the said threshold register is compared; When available cell number during less than said threshold value; Then send first control signal to said image processing circuit; Said image processing circuit receives said first control signal to be stopped in said FIFO buffer, sending data; When available cell number during greater than said threshold value, then send second control signal to said image processing circuit, said image processing circuit receives said second control signal to be continued in said FIFO buffer, to send data.
Further; But but said FIFO buffer comprises the read pointer and the write pointer of r/w cell and record r/w cell read-write state; Corresponding address, each unit; Said write pointer and said read pointer all move to maximum address from the lowest address of said FIFO buffer, and wherein said read pointer moves on the position that said write pointer moved, and deduct the value of said lowest address but the r/w cell total amount of wherein said FIFO buffer is the value of said maximum address.
Further, when writing data, said write pointer adds 1 automatically, and when reading data, said read pointer adds automatic 1; Reach the lowest address of then returning said FIFO buffer behind the maximum address of said FIFO buffer when said write pointer and said read pointer; When the address of said write pointer during greater than the address of said read pointer, but the value and the value that the value that adds the address of read pointer deducts lowest address again that the value of the maximum address of said FIFO buffer are deducted the address of write pointer then draw residue r/w cell number; When the address of said write pointer during, but the address that the address of said read pointer deducts said write pointer is then drawn residue r/w cell number less than the address of said read pointer.
Further, when said first control signal was a kind of in low level or the high level, said second control signal was the another kind of low level or high level.
Compared with prior art; The present invention is through increasing a monitoring module in the LCD control circuit; It can be according to pre-set threshold to the image processing circuit feedback information; Write code stream information with the control image processing circuit to the LCD control circuit, thereby solved a series of problems that produce because of the system bandwidth problem in the image broadcast.
[description of drawings]
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.Wherein:
Fig. 1 connects synoptic diagram for display system;
Fig. 2 is the method synoptic diagram in traditional raising system broadband;
Fig. 3 is for showing the structural drawing of the system of code stream among the present invention;
Fig. 4 A is for writing an embodiment with reading of data in the FIFO buffer among the present invention;
Fig. 4 B is for writing another embodiment with reading of data in the FIFO buffer among the present invention; With
Fig. 5 is the control flow chart of the system of demonstration code stream of the present invention.
[embodiment]
Detailed description of the present invention is mainly come the running of direct or indirect simulation technical scheme of the present invention through program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then possibly still can realize.Affiliated those of skill in the art use these descriptions here and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the object of the invention of avoiding confusion, because the understanding easily of method of knowing and program, so they are not described in detail.
Alleged here " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent that the sequence of modules and revocable in method, process flow diagram or the functional block diagram of one or more embodiment refers to any particular order, also be not construed as limiting the invention.
Basic thought of the present invention is: the present invention has been through having increased monitoring module in original controlled code stream display system, thereby realized the monitoring to code stream, and its particular content sees also Fig. 3.
Fig. 3 is for showing the structural drawing of the system 300 of code stream among the present invention.See also shown in Figure 3; The display system 300 that shows code stream comprises demoder 310, system storage 320, image processing circuit 330, the LCD control circuit 340 that contains the FIFO buffer and LCD display 350; Wherein concrete code stream procedure for displaying can be referring to the description of the Fig. 1 in the background technology; And in image processing circuit 330, added monitoring module 3401 and threshold register 3402 among the present invention, realize showing the transmission control of code stream image processing circuit 330 is carried out information feedback.
But said monitoring module 3401 is used for monitoring the remaining r/w cell number of said FIFO buffer; But and compare to obtain feedback signal according to pre-set threshold in the threshold register 3402 and said r/w cell number; Afterwards feedback signal is sent to said image processing circuit 330; It is to continue to send data or stop it being sent data to said LCD control circuit 340 that said image processing circuit 330 responds with judgement it; Thereby controlled said image processing circuit 330 and sent data, said FIFO buffer needn't be overflowed to said FIFO buffer.Because generally; When mistakes such as overflowing appears in said FIFO buffer; Can the current frame that writes be lost; Wait the next frame arrival and write said FIFO buffer again; Add said monitoring module 3401 and then can not overflow, thereby can the image data that said image processing circuit 330 obtains intactly be sent in the said FIFO buffer, after image data is handled in said FIFO buffer, send in the display-memory to carry out normal play with the said FIFO buffer in said threshold register 3402 backs.
In one example; But but said FIFO buffer comprises the write pointer and the read pointer of a r/w cell and record r/w cell read-write state; The said write pointers point next one writes the address, has write the back write pointer and has added 1 automatically, and said read pointer points to the next one and reads the address; Run through the back read pointer and add 1 automatically, thereby compare through the state of write pointer and read pointer.
General; But corresponding address of each r/w cell of said FIFO buffer; But in said FIFO buffer between lowest address and the maximum address being r/w cell; But wherein the value of maximum address deduct lowest address value then for the r/w cell total amount of said FIFO buffer, that is to say that it writes and reading of data then is that direction between its lowest address and maximum address and from the lowest address to the maximum address is carried out.Traditional, but move on said write pointer and the said read pointer r/w cell in said FIFO buffer, write and read then principle according to first in first out; So when writing and reading beginning, the lowest address that said write pointer and said read pointer all are in said FIFO buffer is a start address; Subsequently, after writing data, said write pointer begins to add automatically 1; Because the data that read pointer need read are the data that write pointer writes all the time; So read pointer will carry out reading of data along with the position of write pointer process, and after reading data, said read pointer adds 1 automatically.When the address of write pointer during, but the value that the value that the value of the maximum address of said FIFO buffer deducts the value of write pointer and adds read pointer deducts lowest address is more then drawn residue r/w cell number greater than the address of read pointer; When the address of write pointer during, but the value that the value of the address of read pointer deducts the address of write pointer is then drawn residue r/w cell number less than the address of read pointer.
In a concrete example, see also Fig. 4 A and Fig. 4 B, Fig. 4 A is for writing an embodiment with reading of data in the FIFO buffer described in the present invention, and Fig. 4 B is for writing another embodiment with reading of data in the FIFO buffer described in the present invention.But the r/w cell total amount of the said FIFO buffer shown in Fig. 4 A is 20, write pointer IN and read pointer OUT, and the value that makes lowest address is 201; The value of maximum address is 220, and then this moment, the value of the address of write pointer IN is 213; The value of the address of read pointer OUT is 204; The address of write pointer is greater than the address of read pointer, so but the number of remaining r/w cell be: 220-213+204-201=11, but promptly this moment, the r/w cell number was 11; But the r/w cell total amount of the said FIFO buffer shown in Fig. 4 B is 20; The value that makes lowest address is 201; The value of maximum address is 220, and wherein the address of write pointer IN is 215, and the address of read pointer OUT is 204; So but the number of remaining r/w cell is: 215-204=11, but promptly this moment, the r/w cell number was 11.
When writing the maximum address 220 of said FIFO buffer for the write pointer IN among Fig. 4 A certainly; Then return start address 201, that is to say, this moment, the address of write pointer IN became 201 from 220; In like manner, lowest address also can be returned in the address of read pointer OUT after reaching maximum address.
It is pointed out that divided by last method, but the implementation of calculating r/w cell number can also realize that the those of ordinary skill that its concrete implementation is affiliated technical field can both be realized, has just detailed no longer one by one through other modes here.
At this moment, the said threshold register 3402 of design in said LCD control circuit 340, it need pre-set a threshold value; For instance, if said FIFO buffer accounts for 100, pre-set threshold possibly be 5; Certainly in practical application, the setting of said threshold register 3402 is mainly rationally set according to other factorses such as efficient, is 0 like threshold setting; Then mean and continue to write and will overflow, generally not will consider this value, and if said IFFO buffer is 100; Threshold value is made as 50, then carries out in the process of buffer memory, just has a lot of buffer zones and slatterns; By on can know, in the process of practical application, be according to more excellent threshold value of factors such as efficient definition.
In the process of monitoring; But the number of more said r/w cell and the size of said threshold value; But when the number of said r/w cell during less than said threshold value; Represent that then said FIFO buffer has approached overflow status, simultaneously said LCD control circuit 340 can be given said image processing circuit 330 with the feedback of status of said FIFO buffer, and just the feedback signal through a 1bit is to transmit this information.Certainly, feedback signal described here can also be 2bit or other quantity bit, but in the practical application, in order to reduce the internal memory use amount, general need be just enough with 1bit.
In a concrete embodiment; But when the number of said r/w cell during less than said threshold value; Said LCD control circuit 340 outputs first control signal i.e. a low level feedback signal, represent that said image processing circuit 330 does not allow to write data to said FIFO buffer, otherwise said FIFO buffer can overflow; At this moment, said image processing circuit 330 stops the data of said FIFO buffer are write after receiving said first control signal; But when the number of said r/w cell during greater than said threshold value; Control circuit 340 outputs this moment second control signal i.e. the feedback signal of a high level; Represent that then said image processing circuit 330 can also continue to write said FIFO buffer, continue when said image processing circuit 330 receives said second control signal in said FIFO buffer, to write data.When feedback signal is first control signal; Owing to stop said FIFO buffer is write data; But system is reading of data from said FIFO buffer constantly also, but makes remaining r/w cell number increase gradually exactly, thereby makes its number greater than said threshold value; This moment, feedback then became second control signal, and said image processing circuit 330 can continue again to have sent the remaining data of present frame to said LCD control circuit.General, if above-mentioned first control signal is a high level, then second control signal corresponds to low level.
In practical application, when said image processing circuit 330 sends the data to said LCD control circuit 340, also need under a rational speed, carry out, general, image processing circuit 330 can transmit data according to the clock timer of a setting.Certainly, when playing, the speed of broadcast preferentially depends on the speed of reading of data from said FIFO buffer; Under the prerequisite that guarantees the speed of reading of data from said FIFO buffer, said FIFO buffer is write data, at this moment; Unobstructed in order to play, constantly reading of data that is to say; Must guarantee has enough played data in the said FIFO buffer, and said FIFO buffer then will write data under another rational clock timer, and the process that writes data is also wanted to be higher priority with monitoring simultaneously; In other words, when monitoring notifies said FIFO buffer near overflowing the write activity that then stops said FIFO buffer, and no matter whether will write according to clock timer this moment; So just, guaranteed to have data all the time in the said FIFO buffer; And under the code stream monitoring of the present invention design, said FIFO buffer can not overflow, thereby has guaranteed from said FIFO buffer sense data and the fluency of playing.
Fig. 5 is the control flow chart of the system of demonstration code stream of the present invention, sees also shown in Figure 5ly, and said control flow comprises:
In concrete application, the display system of said demonstration code stream and control method can realize through software, hardware or way of hardware and software combination.
In sum; The present invention is through having realized showing the transmission control of code stream in the information feedback of said LCD control circuit to said image processing circuit; Not only improve the system broadband, removed very complicated technology such as improvement bus arbitration equally from, practiced thrift cost effectively; Shortened the development time, realized the function that needs to increase minimum hardware spending.
Above-mentioned explanation has fully disclosed embodiment of the present invention.It is pointed out that any change that technician's specific embodiments of the invention of being familiar with this field is done does not all break away from the scope of claims of the present invention.Correspondingly, the scope of claim of the present invention also is not limited only to previous embodiment.
Claims (8)
1. display system that shows code stream; It comprises demoder, include the system storage of display-memory, image processing circuit, the LCD control circuit that includes the FIFO buffer and LCD screen; Said image processing circuit obtains bit stream data behind the said decoder decode to send in the said FIFO buffer in the said LCD control circuit from said system storage; Said FIFO buffer sends in the said display-memory in the said system storage said data being used for and on said LCD screen, plays, and it is characterized in that:
Also comprise a monitoring module and a threshold register in the said LCD control circuit; But said monitoring module is used for monitoring the remaining r/w cell number of said FIFO buffer; But when the r/w cell number of said FIFO buffer less than threshold register in during pre-set threshold; Said LCD control circuit will send first control signal in said image processing circuit; Said image processing circuit receives said first control signal then to be stopped to send bit stream data to said LCD control circuit; But when the r/w cell number of said FIFO buffer during greater than threshold value, said LCD control circuit will send second control signal in said image processing circuit, and said image processing circuit receives said secondary signal then to be continued to send bit stream data to said LCD control circuit.
2. the display system of demonstration code stream according to claim 1; It is characterized in that: but but said FIFO buffer comprises the read pointer and the write pointer of r/w cell and record r/w cell read-write state; But corresponding address of each r/w cell; Said write pointer and said read pointer all move to maximum address from the lowest address of said FIFO buffer; Wherein said read pointer moves on the position that said write pointer moved, and deducts the value of said lowest address but the r/w cell total amount of wherein said FIFO buffer is the value of said maximum address.
3. the display system of demonstration code stream according to claim 2 is characterized in that: when writing data, said write pointer adds 1 automatically, and when reading data, said read pointer adds automatic 1; Reach the lowest address of then returning said FIFO buffer behind the maximum address of said FIFO buffer when said write pointer and said read pointer; When the address of said write pointer during greater than the address of said read pointer, but the value and the value that the value that adds the address of read pointer deducts lowest address again that the value of the maximum address of said FIFO buffer are deducted the address of write pointer then draw residue r/w cell number; When the address of write pointer during, but the address that the address of read pointer deducts write pointer is then drawn residue r/w cell number less than the address of read pointer.
4. the display system of demonstration code stream according to claim 1 is characterized in that: when said first control signal is a kind of in low level or the high level, said second control signal is the another kind in low level or the high level.
5. control method that shows code stream; It is characterized in that: show after code stream is through decoder decode to be put in the system storage that contains display-memory; Image processing circuit obtains decoded demonstration bit stream data and sends in the FIFO buffer in the LCD control circuit from system storage; From said FIFO buffer, read said data and put in the said display-memory to play at display screen, it comprises:
In said LCD control circuit, threshold register is set;
Calculate the number of available cell in the said FIFO buffer; With
Pre-set threshold in the number of available cell in the said FIFO buffer and the said threshold register is compared; When available cell number during less than said threshold value; Then send first control signal to said image processing circuit; Said image processing circuit receives said first control signal to be stopped in said FIFO buffer, sending data; When available cell number during greater than said threshold value, then send second control signal to said image processing circuit, said image processing circuit receives said second control signal to be continued in said FIFO buffer, to send data.
6. the control method of demonstration code stream according to claim 5; It is characterized in that: but but said FIFO buffer comprises the read pointer and the write pointer of r/w cell and record r/w cell read-write state; But corresponding address of each r/w cell; Said write pointer and said read pointer all move to maximum address from the lowest address of said FIFO buffer; Wherein said read pointer moves on the position that said write pointer moved, and deducts the value of said lowest address but the r/w cell total amount of wherein said FIFO buffer is the value of said maximum address.
7. the control method of demonstration code stream according to claim 6 is characterized in that: when writing data, said write pointer adds 1 automatically, and when reading data, said read pointer adds automatic 1; Reach the lowest address of then returning said FIFO buffer behind the maximum address of said FIFO buffer when said write pointer and said read pointer; When the address of said write pointer during greater than the address of said read pointer, but the value and the value that the value that adds the address of read pointer deducts lowest address again that the value of the maximum address of said FIFO buffer are deducted the address of write pointer then draw residue r/w cell number; When the address of said write pointer during, but the address that the address of said read pointer deducts said write pointer is then drawn residue r/w cell number less than the address of said read pointer.
8. the control method of demonstration code stream according to claim 5 is characterized in that: when said first control signal was a kind of in low level or the high level, said second control signal was the another kind of low level or high level.
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| CN106601160B (en) * | 2016-12-14 | 2020-04-14 | 昆山龙腾光电股份有限公司 | Refresh rate conversion device and method and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903283A (en) * | 1997-08-27 | 1999-05-11 | Chips & Technologies, Inc. | Video memory controller with dynamic bus arbitration |
| JP2000137470A (en) * | 1998-07-17 | 2000-05-16 | Seiko Epson Corp | Device and method for controlling memory, information processing system, and recording medium |
| CN101452695A (en) * | 2007-12-07 | 2009-06-10 | 晨星半导体股份有限公司 | Data access arrangement and method |
| CN101499245A (en) * | 2008-01-30 | 2009-08-05 | 深圳安凯微电子技术有限公司 | Asynchronous first-in first-out memory, liquid crystal display controller and its control method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903283A (en) * | 1997-08-27 | 1999-05-11 | Chips & Technologies, Inc. | Video memory controller with dynamic bus arbitration |
| JP2000137470A (en) * | 1998-07-17 | 2000-05-16 | Seiko Epson Corp | Device and method for controlling memory, information processing system, and recording medium |
| CN101452695A (en) * | 2007-12-07 | 2009-06-10 | 晨星半导体股份有限公司 | Data access arrangement and method |
| CN101499245A (en) * | 2008-01-30 | 2009-08-05 | 深圳安凯微电子技术有限公司 | Asynchronous first-in first-out memory, liquid crystal display controller and its control method |
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