CN101853828B - Chip with convex block and packaging structure of chip with convex block - Google Patents
Chip with convex block and packaging structure of chip with convex block Download PDFInfo
- Publication number
- CN101853828B CN101853828B CN 200910131145 CN200910131145A CN101853828B CN 101853828 B CN101853828 B CN 101853828B CN 200910131145 CN200910131145 CN 200910131145 CN 200910131145 A CN200910131145 A CN 200910131145A CN 101853828 B CN101853828 B CN 101853828B
- Authority
- CN
- China
- Prior art keywords
- chip
- metal layer
- layer
- metal level
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a chip with a convex block and a packaging structure of the chip with the convex block. The chip comprises a chip body, at least one through hole, a protective layer, a metal layer under a sphere and at least one convex block. The through hole penetrates the chip body and is exposed on the usrface of the chip body. The protective layer is positioned on the surface of the chip body, the protective layer comprises at least one opening, and the opening exposes the through hole. The metal layer under the sphere is positioned in the opening of the protective layer and is connected with the through hole. The convex block is positioned on the metal layer under the sphere and comprises a first metal layer, a second metal layer and a third metal layer. The first metal layer is positioned on the metal layer under the sphere. The second metal layer is positioned on the first metal layer. The third metal layer is positioned on the second metal layer. Therefore, the convex block can be connected with two chips and stack up the chips, thereby improving the product density and further reducing the product size.
Description
Technical field
The present invention relates to a kind of chip and have the encapsulating structure of chip, particularly relate to a kind of encapsulating structure that has the chip of projection and have the chip of projection.
Background technology
Fig. 1 is for showing known generalized section with chip of projection.With reference to figure 1, this known chip 1 with projection comprises chip body 11, protective layer 12, ball lower metal layer 14 and at least one projection 13.This chip body 11 has surface 111.This protective layer 12 is positioned on the surface 111 of this chip body 11, and this protective layer 12 has at least one opening 121.This ball lower metal layer 14 is positioned at the opening 121 of this protective layer 12.This projection 13 is positioned on this ball lower metal layer 14.
This is known, and to have the shortcoming of chip 1 of projection following.This projection 13 is made up of single metal, anticipates promptly, and the fusing point of this projection 13 is in fixed range; When carrying out the reflow step, this projection 13 is understood Yin Gaowen and is molten condition, is beneficial to be connected mutually with weld pad; Yet; Its molten condition is wayward, is difficult to be connected with this weld pad really, and reduces the product yield.In addition, if this projection 13 is not with the low metallic cover of activity, and then these projection 13 easy oxidations produce qualitative change.
Therefore, be necessary to provide a kind of encapsulating structure that has the chip of projection and have the chip of projection, to address the above problem.
Summary of the invention
The present invention provides a kind of chip with projection, and it comprises chip body, protective layer, ball lower metal layer and at least one projection.This chip body has a surface.This protective layer is positioned on the surface of this chip body, and this protective layer has at least one opening.This ball lower metal layer is positioned at the opening of this protective layer.This projection is positioned on this ball lower metal layer, and this projection comprises the first metal layer, second metal level, the 3rd metal level and the 4th metal level.This first metal layer is positioned on this ball lower metal layer.This second metal level is positioned on this first metal layer.The 3rd metal level is positioned on this second metal level.The 4th metal level is positioned on the 3rd metal level.
Thus, this projection can link two chips, and this chip can be piled up, with the raising product density, and then shorten product sizes.
The present invention also provides a kind of chip with projection, and it comprises chip body, at least one perforating holes, protective layer, ball lower metal layer and at least one projection.This chip body has a surface.This perforating holes runs through this chip body, and is revealed in the surface of this chip body.This protective layer is positioned on the surface of this chip body, and this protective layer has at least one opening, and this opening appears this perforating holes.This ball lower metal layer is positioned at the opening of this protective layer, and connects this perforating holes.This projection is positioned on this ball lower metal layer.This projection comprises the first metal layer, second metal level and the 3rd metal level.This first metal layer is positioned on this ball lower metal layer.This second metal level is positioned on this first metal layer.The 3rd metal level is positioned on this second metal level.
Thus, this perforating holes makes this surface of this chip body and apparent surface all can form this projection, and the windrow of going forward side by side is folded step, with shorten product sizes.
The present invention provides a kind of encapsulating structure with chip of projection in addition, and it comprises substrate, at least one electric connection body, first chip and second chip.This substrate has upper surface and lower surface.This electric connection body is positioned at the upper surface of this substrate.This first chip is positioned on this electric connection body, and it comprises chip body, at least one perforating holes, protective layer, ball lower metal layer and at least one projection.This chip body has upper surface and lower surface.This perforating holes runs through this chip body, and is revealed in the upper surface of this chip body.This protective layer is positioned on the upper surface of this chip body, and it has at least one opening, and this opening appears this perforating holes.This ball lower metal layer is positioned at the opening of this protective layer, and connects this perforating holes.This projection is positioned on this ball lower metal layer, and it comprises the first metal layer, second metal level and the 3rd metal level.This first metal layer is positioned on this ball lower metal layer.This second metal level is positioned on this first metal layer.The 3rd metal level is positioned on this second metal level.This second chip is positioned on this first chip.
Description of drawings
Fig. 1 is for showing known generalized section with chip of projection;
Fig. 2 has the generalized section of first embodiment of the chip of projection for showing the present invention;
Fig. 3 has the generalized section of second embodiment of the chip of projection for showing the present invention;
Fig. 4 has the generalized section of the 3rd embodiment of the chip of projection for showing the present invention;
Fig. 5 has the generalized section of the 4th embodiment of the chip of projection for showing the present invention; And
Fig. 6 has the generalized section of encapsulating structure of the chip of projection for showing the present invention.
Description of reference numerals
1 known chip with projection
2 the present invention have first embodiment of the chip of projection
3 the present invention have second embodiment of the chip of projection
4 the present invention have the 3rd embodiment of the chip of projection
5 the present invention have the 4th embodiment of the chip of projection
6 the present invention have the encapsulating structure of the chip of projection
7 first chips
11 chip bodies
12 protective layers
13 projections
14 ball lower metal layers
21 chip bodies
22 protective layers
23 projections
24 perforating holes
25 ball lower metal layers
41 chip bodies
42 perforating holes
43 protective layers
44 projections
45 ball lower metal layers
61 substrates
62 electrically connect body
64 second chips
65 soldered balls
71 chip bodies
72 perforating holes
73 protective layers
74 projections
75 ball lower metal layers
76 weld pads
77 ball lower metal layers
111 surfaces
121 openings
211 surfaces
212 perforation
213 apparent surfaces
221 openings
232 the first metal layers
233 second metal levels
234 the 3rd metal levels
235 the 4th metal levels
241 barrier layers
242 electric conductors
411 surfaces
412 perforation
413 apparent surfaces
421 barrier layers
422 electric conductors
431 openings
442 the first metal layers
443 second metal levels
444 the 3rd metal levels
611 upper surfaces
612 lower surfaces
613 conductive through holes
621 the 4th metal levels
622 the 5th metal levels
623 the 6th metal levels
711 upper surfaces
712 perforation
713 lower surfaces
721 barrier layers
722 electric conductors
731 openings
742 the first metal layers
743 second metal levels
744 the 3rd metal levels
Embodiment
Fig. 2 has the generalized section of first embodiment of the chip of projection for showing the present invention.With reference to figure 2, this chip 2 with projection comprises chip body 21, protective layer 22, ball lower metal layer 25 and at least one projection 23.This chip body 21 has surface 211.In the present embodiment, this chip body 21 is blank chip (Dummy Chip), and it comprises perforation 212 and line layer (not shown), and this line layer is positioned at the surface 211 of this chip body 21.Yet in other were used, this chip body 21 can be the chip (Device Chip) of function, and it also comprises active face, at least one weld pad and Image Sensor (CMOS Image Sensor) (not shown).This weld pad is positioned at this chip body 21, and is revealed in this active face.This Image Sensor is positioned at this chip body 21, is revealed in this active face, and is positioned at the outer relative position of this weld pad.
This protective layer 22 is positioned on the surface 211 of this chip body 21, and this protective layer 22 has at least one opening 221.This ball lower metal layer 25 is positioned at the opening 221 of this protective layer 22.In the present embodiment, the material of this ball lower metal layer 25 is titanium copper (TiCu) alloy, and this ball lower metal layer 25 connects this line layer.This projection 23 is positioned on this ball lower metal layer 25, and this projection 23 comprises the first metal layer 232, second metal level 233, the 3rd metal level 234 and the 4th metal level 235.This first metal layer 232 is positioned on this ball lower metal layer 25.This second metal level 233 is positioned on this first metal layer 232.The 3rd metal level 234 is positioned on this second metal level 233.The 4th metal level 235 is positioned on the 3rd metal level 234.
In the present embodiment, the material of the 3rd metal level 234 is identical with this first metal layer 232, is all copper (Cu); The material of this second metal level 233 is nickel (Ni); The material of the 4th metal level 235 is a sn-ag alloy, yet in other were used, the material of the 4th metal level 235 can be tin (Sn).Preferably, the thickness of this first metal layer 232 is 7 μ m, and the thickness of this second metal level 233 is 3 μ m, and the thickness of the 3rd metal level 234 is greater than 7 μ m, and the thickness of the 4th metal level 235 is 3-5 μ m.
In the present embodiment, this chip 2 also comprises at least one perforating holes 24, and this perforating holes 24 runs through this chip body 21, and is revealed in the surface 211 of this chip body 21, and this ball lower metal layer 25 connects this perforating holes 24.This perforating holes 24 comprises barrier layer 241 and electric conductor 242, and this barrier layer 241 is positioned on the hole wall of perforation 212 of this chip body 21, and this electric conductor 242 is positioned at this barrier layer 241.In the present embodiment, the distance definition of the central shaft of two adjacent perforating holes 24 is a space D, and preferably, the diameter d of this projection 23 is less than or equal to 2/3rds of this space D, causes short circuit to avoid these projections 23 to connect mutually.
Thus, this projection 23 can link two chips 2, and this chip 2 can be piled up, with the raising product density, and then shorten product sizes.In addition; After this projection 23 carries out the reflow step,, and consume this first metal layer 232 of part if this second metal level 233 diffuses to this first metal layer 232; And formation Jie metallic compound (Inter-material Compound; IMC), the 3rd metal level 234 can remedy the amount that this first metal layer 232 is consumed, to strengthen the adhesion of this projection 23.In addition, this perforating holes 24 makes this surface 211 of this chip body 21 and apparent surface 213 all can form this projection 23, and the windrow of going forward side by side is folded step, with shorten product sizes.
Fig. 3 has the generalized section of second embodiment of the chip of projection for showing the present invention.With reference to figure 3, the chip with projection 2 (Fig. 2) of the chip with projection 3 of present embodiment and first embodiment is roughly the same, and wherein components identical is given identical numbering.Present embodiment and first embodiment different are in the material of the projection 23 of this chip 3 different.In the present embodiment; The material of the 3rd metal level 234 is different with this first metal layer 232; The material of this first metal layer 232 is copper (Cu); The material of this second metal level 233 is nickel (Ni), and the material of the 3rd metal level 234 is tin (Sn) or sn-ag alloy, and the material of the 4th metal level 235 is a gold (Au).Preferably, the thickness of this first metal layer 232 is 7 μ m, and the thickness of this second metal level 233 is 3 μ m, and the thickness of the 3rd metal level 234 is 3-4 μ m, and the thickness of the 4th metal level 235 is 0.5 μ m.Thus, the 4th metal level 235 can be avoided this first metal layer 232, this second metal level 233 and 234 oxidations of the 3rd metal level.In addition, after choosing instrument (Die Bonder) and choosing this chip 3, when heating, the 4th metal level 235 (gold layer) can be avoided this chip 3 to be stained with sticking on this select tool.
Fig. 4 has the generalized section of the 3rd embodiment of the chip of projection for showing the present invention.With reference to figure 4, this chip 4 comprises chip body 41, at least one perforating holes 42, protective layer 43, ball lower metal layer 45 and at least one projection 44.This chip body 41 has surface 411.In the present embodiment, this chip body 41 is blank chip (Dummy Chip), and it also comprises perforation 412.Yet in other were used, this chip body 41 can be the chip (Device Chip) of function, and it also comprises active face, at least one weld pad and Image Sensor (CMOS Image Sensor) (not shown).This weld pad is positioned at this chip body 41, and is revealed in this active face.This Image Sensor is positioned at this chip body 41, is revealed in this active face, and is positioned at the outer relative position of this weld pad.
This perforating holes 42 runs through this chip body 41, and is revealed in the surface 411 of this chip body 41.In the present embodiment, this perforating holes 42 comprises barrier layer 421 and electric conductor 422, and this barrier layer 421 is positioned on the hole wall of perforation 412 of this chip body 41, and this electric conductor 422 is positioned at this barrier layer 421.In the present embodiment, the distance definition of the central shaft of two adjacent perforating holes 42 is a space D, and preferably, the diameter d of this projection 44 is less than or equal to 2/3rds of this space D, causes short circuit to avoid these projections 44 to connect mutually.This protective layer 43 is positioned on the surface 411 of this chip body 41, and this protective layer 43 has at least one opening 431, and this opening 431 appears this perforating holes 42.This ball lower metal layer 45 is positioned at the opening 431 of this protective layer 43, and connects this perforating holes 42.In the present embodiment, the material of this ball lower metal layer 45 is titanium copper (TiCu) alloy.
This projection 44 is positioned on this ball lower metal layer 45.This projection 44 comprises the first metal layer 442, second metal level 443 and the 3rd metal level 444.This first metal layer 442 is positioned on this ball lower metal layer 45.This second metal level 443 is positioned on this first metal layer 442.The 3rd metal level 444 is positioned on this second metal level 443.In the present embodiment, the material of this first metal layer 442 is copper (Cu), and the material of this second metal level 443 is nickel (Ni), and the material of the 3rd metal level 444 is tin (Sn) or sn-ag alloy.Preferably, the thickness of this first metal layer 442 is 7 μ m, and the thickness of this second metal level 443 is 3 μ m, and the thickness of the 3rd metal level 444 is 2 μ m.In other were used, this chip 4 also comprised line layer, and this line layer is positioned at the surface 211 of this chip body 21, and this ball lower metal layer 45 connects this line layer.
Thus, this perforating holes 42 makes this surface 411 of this chip body 41 and apparent surface 413 all can form this projection 44, and the windrow of going forward side by side is folded step, with shorten product sizes.
Fig. 5 has the generalized section of the 4th embodiment of the chip of projection for showing the present invention.With reference to figure 5, the chip with projection 4 (Fig. 4) of the chip with projection 5 of present embodiment and the 3rd embodiment is roughly the same, and wherein components identical is given identical numbering.Present embodiment and the 3rd embodiment different are in the material of the projection 44 of this chip 5 different.In the present embodiment, the material of this first metal layer 442 is copper (Cu), and the material of this second metal level 443 is nickel (Ni), and the material of the 3rd metal level 444 is a gold (Au).Preferably, the thickness of this first metal layer 442 is 7 μ m, and the thickness of this second metal level 443 is 3 μ m, and the thickness of the 3rd metal level 444 is 0.5 μ m.In addition, after the instrument of choosing at this chip 5, when heating, the 3rd metal level 444 (gold layer) can be avoided this chip 5 to be stained with sticking on this select tool.
Fig. 6 has the generalized section of encapsulating structure of the chip of projection for showing the present invention.With reference to figure 6, this encapsulating structure 6 comprises substrate 61, at least one electric connection body 62, first chip 7, second chip 64 and a plurality of soldered ball 65.This substrate 61 has upper surface 611 and lower surface 612.In the present embodiment, this substrate 61 comprises that also at least one conductive through hole 613 runs through this substrate 61, and is revealed in the upper surface 611 and the lower surface 612 of this substrate 61.This electric connection body 62 is positioned at the upper surface 611 of this substrate 61.In the present embodiment, this electric connection body 62 is a projection.Yet in other were used, this electric connection body 62 can be soldered ball.
This first chip 7 is positioned on this electric connection body 62, and it comprises chip body 71, at least one perforating holes 72, protective layer 73, ball lower metal layer 75 and at least one projection 74.This chip body 71 has upper surface 711 and lower surface 713.This lower surface 713 is an active face, and it is with respect to the upper surface 711 of this chip body 71.In the present embodiment, this chip body 71 is for there being the chip (Device Chip) of function, and it also comprises at least one weld pad 76 and bores a hole 712.This weld pad 76 is positioned at this chip body 71, and is revealed in this lower surface 713.Yet in other were used, this chip body 71 can be blank chip (DummyChip).
This perforating holes 72 runs through this chip body 71, and the one of which end is revealed in the upper surface 711 of this chip body 71, and the other end connects this weld pad 76.In the present embodiment, this perforating holes 72 comprises barrier layer 721 and electric conductor 722, and this barrier layer 721 is positioned on the hole wall of perforation 712 of this chip body 71, and this electric conductor 722 is positioned at this barrier layer 721.In the present embodiment, the distance definition of the central shaft of two adjacent perforating holes 72 is a space D, and preferably, the diameter d of this projection 74 is less than or equal to 2/3rds of this space D, causes short circuit to avoid these projections 74 to connect mutually.
This protective layer 73 is positioned on the upper surface 711 of this chip body 71, and this protective layer 73 has at least one opening 731, and this opening 731 appears this perforating holes 72.This ball lower metal layer 75 is positioned at the opening 731 of this protective layer 73, and connects this perforating holes 72.In the present embodiment, the material of this ball lower metal layer 75 is titanium copper (TiCu) alloy.
This projection 74 is positioned on this ball lower metal layer 75.This projection 74 comprises the first metal layer 742, second metal level 743 and the 3rd metal level 744.This first metal layer 742 is positioned on this ball lower metal layer 75.This second metal level 743 is positioned on this first metal layer 742.The 3rd metal level 744 is positioned on this second metal level 743.In the present embodiment, the material of this first metal layer 742 is copper (Cu), and the material of this second metal level 743 is nickel (Ni), and the material of the 3rd metal level 744 is tin (Sn) or sn-ag alloy.Preferably, the thickness of this first metal layer 742 is 7 μ m, and the thickness of this second metal level 743 is 3 μ m, and the thickness of the 3rd metal level 744 is 2 μ m.
In the present embodiment, this first chip 7 also comprises ball lower metal layer 77, is positioned at this lower surface 713, and connects this weld pad 76.This electric connection body 62 is positioned on this ball lower metal layer 77; It is a projection; And comprise the 4th metal level 621, the 5th metal level 622 and the 6th metal level 623; The 4th metal level 621 is identical with this first metal layer 742, and the 5th metal level 622 is identical with this first metal layer 743, and the 6th metal level 623 is identical with the 3rd metal level 744.
In other were used, this first chip 7 also comprised Image Sensor (CMOS ImageSensor) (not shown) and line layer (not shown).This Image Sensor is positioned at this chip body 71, is revealed in this lower surface 713, and is positioned at the relative position outside this weld pad 76.This line layer is positioned at the upper surface 711 of this chip body 71, and this ball lower metal layer 75 connects this line layer.
This second chip 64 is positioned on this first chip 7, and connects the 3rd metal level 744.In the present embodiment, this second chip 64 is a flip-chip.Yet in other were used, this second chip 64 can have at least one perforating holes.These soldered balls 65 are positioned at the lower surface 612 of this substrate 61.
The foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, persons skilled in the art are made amendment to the foregoing description and are changed and still do not take off spirit of the present invention.The claim that interest field of the present invention should be liked enclosed defines.
Claims (17)
1. chip with projection comprises:
The chip body has a surface;
Protective layer is positioned on the surface of this chip body, and this protective layer has at least one opening;
The ball lower metal layer is positioned at the opening of this protective layer; And
At least one projection is positioned on this ball lower metal layer, and this projection comprises:
The first metal layer is positioned on this ball lower metal layer;
Second metal level is positioned on this first metal layer;
The 3rd metal level is positioned on this second metal level; And
The 4th metal level is positioned on the 3rd metal level,
Wherein the material of the 3rd metal level is identical with this first metal layer, and the material of this first metal layer and the 3rd metal level is a copper, and the material of this second metal level is a nickel, and the material of the 4th metal level is tin or sn-ag alloy.
2. chip as claimed in claim 1, wherein the thickness of this first metal layer is that 7 μ m, this second metal layer thickness are that 3 μ m, the 3rd metal layer thickness are 3-5 μ m greater than 7 μ m and the 4th metal layer thickness.
3. chip as claimed in claim 1 also comprises line layer, and this line layer is positioned at the surface of this chip body, and this ball lower metal layer connects this line layer.
4. chip as claimed in claim 1; Also comprise at least one perforating holes, this perforating holes runs through this chip body, and is revealed in the surface of this chip body; This ball lower metal layer connects this perforating holes; This perforating holes comprises barrier layer and electric conductor, and this barrier layer is positioned on the hole wall of perforation of this chip body, and this electric conductor is positioned at this barrier layer.
5. chip as claimed in claim 4, wherein the distance definition of the central shaft of two adjacent perforating holes is a spacing, and the diameter of this projection is less than or equal to 2/3rds of this spacing.
6. chip with projection comprises:
The chip body has a surface;
Protective layer is positioned on the surface of this chip body, and this protective layer has at least one opening;
The ball lower metal layer is positioned at the opening of this protective layer; And
At least one projection is positioned on this ball lower metal layer, and this projection comprises:
The first metal layer is positioned on this ball lower metal layer;
Second metal level is positioned on this first metal layer;
The 3rd metal level is positioned on this second metal level; And
The 4th metal level is positioned on the 3rd metal level,
Wherein the material of the 4th metal level is a gold, and the material of this first metal layer is a copper, and the material of this second metal level is a nickel, and the material of the 3rd metal level is tin or sn-ag alloy.
7. chip as claimed in claim 6, wherein the thickness of this first metal layer is that 7 μ m, this second metal layer thickness are that 3 μ m, the 3rd metal layer thickness are that 3-4 μ m and the 4th metal layer thickness are 0.5 μ m.
8. chip with projection comprises:
The chip body has a surface;
At least one perforating holes runs through this chip body, and is revealed in the surface of this chip body, and this perforating holes comprises barrier layer and electric conductor, and this barrier layer is positioned on the hole wall of perforation of this chip body, and this electric conductor is positioned at this barrier layer;
Protective layer is positioned on the surface of this chip body, and this protective layer has at least one opening, and this opening appears this perforating holes;
The ball lower metal layer is positioned at the opening of this protective layer, and connects this perforating holes; And
At least one projection is positioned on this ball lower metal layer, and this projection comprises:
The first metal layer is positioned on this ball lower metal layer;
Second metal level is positioned on this first metal layer; And
The 3rd metal level is positioned on this second metal level,
Wherein the material of this first metal layer is a copper, and the material of this second metal level is a nickel, and the material of the 3rd metal level is a gold.
9. chip as claimed in claim 8, wherein the distance definition of the central shaft of two adjacent perforating holes is a spacing, and the diameter of this projection is less than or equal to 2/3rds of this spacing.
10. chip as claimed in claim 8, wherein the thickness of this first metal layer is that 7 μ m, this second metal layer thickness are that 3 μ m and the 3rd metal layer thickness are 0.5 μ m.
11. chip as claimed in claim 8 also comprises line layer, this line layer is positioned at the surface of this chip body, and this ball lower metal layer connects this line layer.
12. the encapsulating structure with chip of projection comprises:
Substrate has upper surface and lower surface;
At least one electric connection body is positioned at the upper surface of this substrate;
First chip is positioned on this electric connection body, comprising:
The chip body has upper surface and lower surface;
At least one perforating holes runs through this chip body, and is revealed in the upper surface of this chip body; This perforating holes comprises barrier layer and electric conductor, and this barrier layer is positioned on the hole wall of perforation of this chip body, and this electric conductor is positioned at this barrier layer;
Protective layer is positioned on the upper surface of this chip body, and this protective layer has at least one opening, and this opening appears this perforating holes;
The ball lower metal layer is positioned at the opening of this protective layer, and connects this perforating holes; And
At least one projection is positioned on this ball lower metal layer, and this projection comprises:
The first metal layer is positioned on this ball lower metal layer;
Second metal level is positioned on this first metal layer; And
The 3rd metal level is positioned on this second metal level; And
Second chip is positioned on this first chip, and connects the 3rd metal level,
Wherein the material of the first metal layer of this first chip is a copper, and the material of this second metal level is a nickel, and the material of the 3rd metal level is a gold.
13. encapsulating structure like claim 12; Also comprise the ball lower metal layer, it is positioned at the lower surface of this chip body, and this electric connection body is a projection; It comprises the 4th metal level, the 5th metal level and the 6th metal level; The 4th metal level is positioned on this ball lower metal layer, and the 5th metal level is positioned on the 4th metal level, and the 6th metal level is positioned on the 5th metal level.
14. like the encapsulating structure of claim 12, wherein the distance definition of the central shaft of two adjacent perforating holes is a spacing, and the diameter of this projection is less than or equal to 2/3rds of this spacing.
15. like the encapsulating structure of claim 12, wherein the thickness of the first metal layer of this first chip is that second metal layer thickness of 7 μ m, this first chip is that the 3rd metal layer thickness of 3 μ m and this first chip is 0.5 μ m.
16. like the encapsulating structure of claim 12, wherein this first chip also comprises line layer, this line layer is positioned at the upper surface of this chip body, and this ball lower metal layer connects this line layer.
17. like the encapsulating structure of claim 12, wherein this second chip has at least one perforating holes or is flip-chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910131145 CN101853828B (en) | 2009-04-03 | 2009-04-03 | Chip with convex block and packaging structure of chip with convex block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910131145 CN101853828B (en) | 2009-04-03 | 2009-04-03 | Chip with convex block and packaging structure of chip with convex block |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101853828A CN101853828A (en) | 2010-10-06 |
| CN101853828B true CN101853828B (en) | 2012-12-26 |
Family
ID=42805207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910131145 Active CN101853828B (en) | 2009-04-03 | 2009-04-03 | Chip with convex block and packaging structure of chip with convex block |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101853828B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190378963A1 (en) * | 2018-06-06 | 2019-12-12 | Advanced Semiconductor Engineering, Inc. | Electronic apparatus and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
| CN101221912A (en) * | 2007-01-12 | 2008-07-16 | 百慕达南茂科技股份有限公司 | Multi-layer projection structure and manufacturing method thereof |
| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
-
2009
- 2009-04-03 CN CN 200910131145 patent/CN101853828B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
| CN101221912A (en) * | 2007-01-12 | 2008-07-16 | 百慕达南茂科技股份有限公司 | Multi-layer projection structure and manufacturing method thereof |
| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101853828A (en) | 2010-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8314490B2 (en) | Chip having a bump and package having the same | |
| US9502394B2 (en) | Package on-Package (PoP) structure including stud bulbs and method | |
| CN101887874B (en) | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package | |
| US8759958B2 (en) | Semiconductor package and method of manufacturing the same | |
| TWI314354B (en) | Semiconductor device having improved mechanical and thermal reliability | |
| US20080257595A1 (en) | Packaging substrate and method for manufacturing the same | |
| TWI343112B (en) | Package substrate having electrical connection structure and method for fabricating the same | |
| US8822841B2 (en) | Package substrate and fabricating method thereof | |
| US20100127047A1 (en) | Method of inhibiting a formation of palladium-nickel-tin intermetallic in solder joints | |
| US20080036079A1 (en) | Conductive connection structure formed on the surface of circuit board and manufacturing method thereof | |
| US10177131B2 (en) | Semiconductor packages and methods of manufacturing the same | |
| TWI230994B (en) | Circuit carrier | |
| US20110122592A1 (en) | First-level interconnects with slender columns, and processes of forming same | |
| CN102446775B (en) | Non-carrier semiconductor packaging component and manufacturing method thereof | |
| US20080290528A1 (en) | Semiconductor package substrate having electrical connecting pads | |
| US20110049708A1 (en) | Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same | |
| CN101360388B (en) | Electricity connection terminal construction of circuit board and preparation thereof | |
| CN101853828B (en) | Chip with convex block and packaging structure of chip with convex block | |
| CN101989587A (en) | Electrical connection structure of circuit board and circuit board device | |
| JP2012174791A (en) | Wiring board, manufacturing method of wiring board, and semiconductor device | |
| CN103208428B (en) | Base plate for packaging and method for making thereof | |
| CN104810344A (en) | Stack set, manufacturing method thereof and substrate structure | |
| EP2924727B1 (en) | Thin NiB or CoB capping layer for non-noble metal bond pads | |
| JP2018125343A (en) | Through electrode substrate and manufacturing method thereof | |
| KR100961308B1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |