CN101847586B - Circuit substrate process and circuit substrate - Google Patents
Circuit substrate process and circuit substrate Download PDFInfo
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- CN101847586B CN101847586B CN 201010184470 CN201010184470A CN101847586B CN 101847586 B CN101847586 B CN 101847586B CN 201010184470 CN201010184470 CN 201010184470 CN 201010184470 A CN201010184470 A CN 201010184470A CN 101847586 B CN101847586 B CN 101847586B
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- layer
- opening
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- conducting block
- connection pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A circuit substrate process and circuit substrate. The circuit substrate process includes: providing a patterned conductive layer arranged on a base layer and provided with an inner pad, a dielectric layer arranged on the base layer and covering the patterned conductive layer, and a cover layer arranged on the dielectric layer. A part of cover layer is removed by a dry etching to form a first opening. One part of dielectric layer exposed by the first opening is removed to form a dielectric opening, wherein one part of inner pad is exposed through the dielectric opening. A patterned mask is formed on the cover layer, wherein the patterned mask has a second opening, and one part of inner pad is exposed through the second opening. A conducting structure is formed, which comprises a conducting block, an outside pad and a remainder layer, the conducting block is full of the dielectric opening, the outside pad is filled of the first opening, the remainder layer is filled with the second opening. Finally, the patterned mask, the remainder layer and the cover layer are removed.
Description
Technical field
The present invention relates to a kind of circuit base plate and technology thereof, and particularly relate to a kind of connection pad and integrally formed circuit base plate and the technology thereof of conducting block.
Background technology
In semiconductor packaging, circuit base plate (circuit substrate) is one of packaging element that often uses at present.Mainly be superimposed forms circuit base plate by multi-layered patterned line layer (patterned conductive layer) and multilayer dielectric layer (dielectric layer), and can see through conductive hole (conductive via) between two line layers and be electrically connected to each other.How raising along with the line density of circuit base plate effectively utilizes limited space to carry out the increasingly important problem of being configured as of circuit.
Summary of the invention
The present invention proposes a kind of circuit substrate process, and it comprises the following steps.One basal layer, a patterned conductive layer, a dielectric layer and a cover layer are provided, and wherein patterned conductive layer is configured on the basal layer and has an inner connection pad, and dielectric layer is configured on the basal layer and the overlay pattern conductive layer, and cover layer is configured on the dielectric layer.Remove part of covering layer through dry-etching, to form one first opening.Remove the part dielectric layer that first opening is exposed, to form a dielectric opening, wherein the dielectric opening exposes the inside connection pad of part.Form a pattern mask on cover layer, wherein pattern mask has one second opening, and second opening exposes the inside connection pad of part.Form conductive structure, wherein conductive structure comprises a conducting block, an external connecting pads and a remainder layer, and conducting block is filled the dielectric opening, and external connecting pads is filled first opening, and remainder layer is filled second opening, and conducting block, external connecting pads and remainder layer are integrally formed.Remove pattern mask, remainder layer and cover layer.
The present invention also proposes a kind of circuit base plate, and it comprises a basal layer, a patterned conductive layer, a dielectric layer and a conducting block.Patterned conductive layer is disposed on the basal layer and has an inner connection pad.Dielectric layer is configured on the basal layer and the overlay pattern conductive layer.Conducting block runs through dielectric layer and flushes in fact with dielectric layer, and connects inner connection pad, and this conducting block is as the electrode of this circuit base plate.
The present invention adopts dry-etching on cover layer, to form opening, and is not only very fast on process speed, and also is beneficial to the formation of subsequent external connection pad.In addition, the present invention utilizes cover layer can effectively control the height of external connecting pads.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Figure 1A to Fig. 1 I illustrates a kind of circuit substrate process of one embodiment of the invention with section.
Fig. 2 is the inside connection pad of Fig. 1 I and the stereogram of conducting block.
Fig. 3 illustrates the final step of a kind of circuit substrate process of another embodiment of the present invention with section.
Fig. 4 is the inside connection pad of Fig. 3 and the stereogram of conducting block.
Fig. 5 A to Fig. 5 B shows the latter two steps of a kind of circuit substrate process of another embodiment of the present invention with section.
Fig. 6 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.
Fig. 7 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.
Fig. 8 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.
Description of reference numerals
110: basal layer
120: patterned conductive layer
122: inner connection pad
124: inner lead
130: dielectric layer
132: the dielectric opening
140: conductive structure
140a: conductive seed layer
142: conducting block
144: external connecting pads
146: remainder layer
150: cover layer
152: the first openings
160: patterned mask layer
162: the second openings
170: sealer
Embodiment
Figure 1A to Fig. 1 I illustrates a kind of circuit substrate process of one embodiment of the invention with section.Please refer to Figure 1A, at first, a basal layer 110, a patterned conductive layer 120, a dielectric layer 130 and a cover layer 150 are provided.Basal layer 110 can be line layer, the line layer on the chip support plate or the line layer on the printed circuit board (PCB) on the chip.Patterned conductive layer 120 is configured on the basal layer 110 and has an inner connection pad 122.Dielectric layer 130 is configured on the basal layer 110 and overlay pattern conductive layer 120, and cover layer 150 is configured on the dielectric layer 130.The material of cover layer 150 for example is the nonmetallic materials or the metal materials of the usefulness of conduct resistance barrier (Barrier) such as organic material.Particularly, in one embodiment, the material of the cover layer of being selected for use 150 has the character that can divest from dielectric layer 130.
In the present embodiment; Dielectric layer 130 can be made by resin; And can with dielectric layer 130 be disposed at cover layer 150 superimposed (laminate) on the dielectric layer 130 to basal layer 110 and patterned conductive layer 120, make dielectric layer 130 overlay pattern conductive layer 120 also between basal layer 110 and cover layer 150.In other words, in the present embodiment, the double-decker that comprises dielectric layer 130 and cover layer 150 can be provided, and be formed on the basal layer 110 with patterned conductive layer 120 with the mode of superimposed (laminate).With technology, provide the double-decker that comprises dielectric layer 130 and cover layer 150 to help the simplification of technology.In another embodiment, can on the basal layer with patterned conductive layer 120 110, form dielectric layer 130 and cover layer 150 in regular turn.
Please refer to Figure 1B, then, (dry etching) removes part of covering layer 150 through dry-etching, to form one first opening 152.In the present embodiment, if the material of cover layer 150 is nonmetallic materials, the dry-etching that step adopted that then removes part of covering layer 150 can be laser-induced thermal etching (laseretching) or plasma etching (plasma etching).In another embodiment,, then can't carry out laser-induced thermal etching, and need to adopt Patternized techniques such as photoetching, etching to form first opening 152 if the material of cover layer 150 is metal materials.Particularly,, use dry-etching (particularly laser-induced thermal etching) to form first opening 152, can reduce the time of technology compared to Patternized technique.
Please again with reference to Figure 1B, then, remove the part dielectric layer 130 that first opening 152 is exposed, to form a dielectric opening 132, wherein dielectric opening 132 exposes the inside connection pad 122 of part.
In the present embodiment, if the material of cover layer 150 is nonmetallic materials, then can remove the part dielectric layer 130 that first opening 152 is exposed through dry-etching.In addition, the dry-etching that step adopted that removes part dielectric layer 130 for example is laser-induced thermal etching or plasma etching.
Please refer to Fig. 1 C, after forming dielectric opening 132, form a conductive seed layer 140a on the inwall and cover layer 150 of the inwall of dielectric opening 132, first opening 152.The material of conductive seed layer 140a for example is a copper.
Please refer to Fig. 1 D; Then; Form a pattern mask 160 on the partially conductive Seed Layer 140a that is positioned on the cover layer 150, wherein pattern mask 160 has one second opening 162, and second opening 162 exposes the inside connection pad 122 of first opening 152, dielectric opening 132 and part.
Please refer to Fig. 1 E, then, is that current path passes through to electroplate formation one conductive structure 140 with conductive seed layer 140a.The material of conductive structure 140 for example is a copper.Conductive structure 140 comprises a conducting block 142, an external connecting pads 144 and a remainder layer 146; Wherein conducting block 142 is filled the inside connection pad 122 of dielectric opening 132 and cover part; External connecting pads 144 is filled first opening 152, and remainder layer 146 is filled second opening 162.Because conducting block 142, external connecting pads 144 and remainder layer 146 form through electroplating technology, so have integrally formed structure.
Please refer to Fig. 1 F, then, remove pattern mask 160.
Please refer to Fig. 1 G, then, remove remainder layer 146 and be positioned at the partially conductive Seed Layer 140a on the cover layer 150.In the present embodiment, can remove remainder layer 146 and be positioned at the partially conductive Seed Layer 140a on the cover layer 150 through grinding (polish) or etching.
Please refer to Fig. 1 H, then, remove cover layer 150.In the present embodiment, can divest cover layer 150 from dielectric layer 130 through after combining between reduction cover layer 150 and the dielectric layer 130.What deserves to be mentioned is that after removing cover layer 150, external connecting pads 144 will come out, and then can be used as the bridge that is connected with electronic components such as chip or packaging bodies.In addition, step can be known thus, and the height of external connecting pads 144 is relevant with cover layer 150, that is thickness that can cover layer 150 is controlled the height of external connecting pads 144.
Please refer to Fig. 1 I, in one embodiment, also can continue to form a sealer 170 on external connecting pads 146 and partially conductive Seed Layer 140a.The material of sealer 170 for example is nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), nickel/tin (Ni/Sn), palladium (Pd), gold (Au) or its alloy, and perhaps sealer 170 is an organic protection layer (OSP).
Fig. 2 is the inside connection pad of Fig. 1 I and the stereogram of conducting block.Please refer to Fig. 1 I and Fig. 2, the external diameter of inner connection pad 122 is greater than the external diameter of conducting block 142.In addition, patterned conductive layer 120 also has an inner lead 124, and the latter end that inner connection pad 122 is extended out for inner lead 124, and the external diameter of inner connection pad 122 is greater than the live width of inner lead 124.In the present embodiment, inner lead 124 can be used as holding wire, earth connection and power line etc.
Fig. 3 illustrates the final step of a kind of circuit substrate process of another embodiment of the present invention with section, and Fig. 4 is the inside connection pad of Fig. 3 and the stereogram of conducting block.Please refer to Fig. 3 and Fig. 4, present embodiment is similar to the embodiment of Figure 1A～1I, but the external diameter of inner connection pad 122 makes conducting block 142 coat inner connection pad 122 less than the external diameter of conducting block 142.In addition, patterned conductive layer 120 also has an inner lead 124, and the latter end that inner connection pad 122 is extended out for inner lead 124, and the external diameter of inner connection pad 122 equals the live width of inner lead 124 in fact.
Fig. 5 A to Fig. 5 B shows the latter two steps of a kind of circuit substrate process of another embodiment of the present invention with section.Please refer to Fig. 5 A; Present embodiment comprises the step of Figure 1A to Fig. 1 H; Then also remove external connecting pads 144 and partially conductive Seed Layer 140a, make conducting block 142 flush in fact with dielectric layer 130, and via the inside connection pad 122 of conductive seed layer 140a coupling part.Please refer to Fig. 5 B, last, can form a sealer 170 on conducting block 142 and partially conductive Seed Layer 140a.
Fig. 6 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.Please refer to Fig. 6, present embodiment is similar to the embodiment of Fig. 5 B, but the external diameter of inner connection pad 122 makes conducting block 142 form the back and coats inner connection pad 122 less than the external diameter of conducting block 142.Such situation also is disclosed among Fig. 4.
Fig. 7 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.Please refer to Fig. 7, be different from the embodiment of Fig. 1 I, the internal diameter of first opening 152 through increasing Figure 1B makes and passed through the external diameter of the external diameter of the formed external connecting pads 144 of Fig. 1 C to Fig. 1 E greater than conducting block 142 afterwards.
Fig. 8 shows the final step of a kind of circuit substrate process of another embodiment of the present invention with section.Please refer to Fig. 8, be different from the embodiment of Fig. 7, the external diameter of inner connection pad 122 makes conducting block 142 coat inner connection pad 122 less than the external diameter of conducting block 142.Such situation also is disclosed among Fig. 4.
In sum, the present invention adopts dry-etching on cover layer, to form opening, and is not only very fast on process speed, and also is beneficial to the formation of subsequent external connection pad.In addition, the present invention utilizes cover layer can effectively control the height of external connecting pads.In addition, the present invention is also integrally formed with conducting block and external connecting pads, makes the problem of external connecting pads with respect to the contraposition skew of conducting block to avoid adopting repeatedly Patternized technique in the past.In addition, the present invention also also can replace the electrode that external connecting pads forms circuit base plate through the conducting block that embeds dielectric layer.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, and those of ordinary skill in any affiliated technical field is not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (15)
1. circuit substrate process comprises:
One basal layer, a patterned conductive layer, a dielectric layer and a cover layer are provided; Wherein this patterned conductive layer is configured on this basal layer and has an inner connection pad; And this dielectric layer is configured on this basal layer and cover this patterned conductive layer, and this cover layer is configured on this dielectric layer;
Remove this cover layer of part through dry-etching, to form one first opening;
Remove this dielectric layer of part that this first opening is exposed, to form a dielectric opening, wherein this dielectric opening exposes this inside connection pad of part;
Form a pattern mask on this cover layer, wherein this pattern mask has one second opening, and this second opening exposes this inside connection pad of part;
Form a conductive structure; Wherein this conductive structure comprises a conducting block, an external connecting pads and a remainder layer, and this conducting block is filled this dielectric opening, and this external connecting pads is filled this first opening; This remainder layer is filled this second opening, and this conducting block, this external connecting pads and this remainder layer are integrally formed; And
Remove this pattern mask, this remainder layer and this cover layer.
2. circuit substrate process as claimed in claim 1, wherein this tectal material is nonmetallic materials, removes the part dry-etching that this tectal step adopted and comprises laser-induced thermal etching or plasma etching.
3. circuit substrate process as claimed in claim 1, the step that wherein removes this dielectric layer of part comprises through dry-etching and removes this dielectric layer of part that this first opening is exposed.
4. circuit substrate process as claimed in claim 3, wherein this tectal material is nonmetallic materials, the dry-etching that step adopted that removes this dielectric layer of part comprises laser-induced thermal etching or plasma etching.
5. circuit substrate process as claimed in claim 1 wherein provides this basal layer, this patterned conductive layer, this dielectric layer and this tectal step to comprise:
Provide and comprise this dielectric layer and this tectal pair of lamina structure;
This basal layer with this patterned conductive layer is provided; And
With superimposed mode this double-decker is formed on this basal layer with this patterned conductive layer.
6. circuit substrate process as claimed in claim 1 also comprises:
Before the step that forms this patterned mask layer; Form a conductive seed layer on the inwall and this cover layer of the inwall of this inside connection pad, this dielectric opening, this first opening; Wherein among the step that forms this pattern mask; This pattern mask is formed on and is positioned on this this conductive seed layer of supratectal part, and among the step that forms this conductive structure, is that current path passes through to electroplate this conductive structure of formation with this conductive seed layer; And
After removing the step of this pattern mask, remove and be positioned at this this conductive seed layer of supratectal part.
7. circuit substrate process as claimed in claim 1 wherein removes this tectal step and comprises:
Weaken combining between this cover layer and this dielectric layer; And
Divest this cover layer from this dielectric layer.
8. circuit substrate process as claimed in claim 1, wherein the height of this external connecting pads is controlled by this tectal thickness.
9. circuit substrate process as claimed in claim 1 also comprises:
After removing this remainder layer, remove this external connecting pads.
10. circuit substrate process as claimed in claim 9 also comprises:
After removing this external connecting pads, form a sealer on this conducting block.
11. a circuit base plate comprises:
One basal layer;
One patterned conductive layer is disposed on this basal layer and has an inner connection pad;
One dielectric layer is configured on this basal layer and covers this patterned conductive layer; And
One conducting block runs through this dielectric layer and flushes in fact with this dielectric layer, and connect should the inside connection pad, and this conducting block is as the electrode of this circuit base plate.
12. circuit base plate as claimed in claim 11 also comprises:
One sealer is configured on this conducting block.
13. greater than the external diameter of this conducting block, making, circuit base plate as claimed in claim 11, external diameter that wherein should the inside connection pad should the inside connection pad on section, form the profile of " T " font with this conducting block.
14. circuit base plate as claimed in claim 11, external diameter that wherein should the inside connection pad, make that this conducting block coats less than the external diameter of this conducting block should the inside connection pad.
15. circuit base plate as claimed in claim 11, wherein this patterned conductive layer also has an inner lead, and a latter end of this inner lead formation should the inside connection pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US31540810P | 2010-03-19 | 2010-03-19 | |
| US61/315,408 | 2010-03-19 |
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| Publication Number | Publication Date |
|---|---|
| CN101847586A CN101847586A (en) | 2010-09-29 |
| CN101847586B true CN101847586B (en) | 2012-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201010184470 Active CN101847586B (en) | 2010-03-19 | 2010-05-21 | Circuit substrate process and circuit substrate |
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| CN (1) | CN101847586B (en) |
| TW (1) | TWI403236B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916732B (en) * | 2010-08-06 | 2013-01-02 | 威盛电子股份有限公司 | Circuit substrate and making process thereof |
| US9706652B2 (en) * | 2010-12-24 | 2017-07-11 | Lg Innotek Co., Ltd. | Printed circuit board and method for manufacturing same |
| CN104066526B (en) * | 2011-11-30 | 2016-03-30 | 施耐德电气It公司 | Manufacture the method for radiator |
| CN103635017B (en) * | 2012-08-24 | 2016-12-28 | 碁鼎科技秦皇岛有限公司 | Circuit board and preparation method thereof |
| CN103887181B (en) * | 2012-12-20 | 2017-10-10 | 深南电路有限公司 | Lead frame processing method |
| CN103887180B (en) * | 2012-12-20 | 2016-09-28 | 深南电路有限公司 | lead frame processing method |
| TWI561133B (en) * | 2014-11-10 | 2016-12-01 | Boardtek Electronics Corp | Circuit board with electroplated type and manufacturing method thereof |
| CN105682336A (en) * | 2014-11-17 | 2016-06-15 | 先丰通讯股份有限公司 | Electroplated circuit board structure and manufacturing method thereof |
| US20180012791A1 (en) * | 2016-07-06 | 2018-01-11 | Globalfoundries Inc. | Interconnects with inner sacrificial spacers |
| TWI822197B (en) * | 2022-01-13 | 2023-11-11 | 欣興電子股份有限公司 | Circuit board structure and manufacturing method thereof |
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| CN101534609A (en) * | 2008-03-12 | 2009-09-16 | 欣兴电子股份有限公司 | Circuit structure of circuit board and method for manufacture same |
| CN101702400A (en) * | 2009-11-16 | 2010-05-05 | 威盛电子股份有限公司 | Circuit substrate and technology thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI254995B (en) * | 2004-01-30 | 2006-05-11 | Phoenix Prec Technology Corp | Presolder structure formed on semiconductor package substrate and method for fabricating the same |
| TWI261329B (en) * | 2005-03-09 | 2006-09-01 | Phoenix Prec Technology Corp | Conductive bump structure of circuit board and method for fabricating the same |
| TWI302811B (en) * | 2006-01-16 | 2008-11-01 | Advanced Semiconductor Eng | Method for fabricating conductive blind via of circuit substrate |
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2010
- 2010-05-21 CN CN 201010184470 patent/CN101847586B/en active Active
- 2010-05-21 TW TW99116309A patent/TWI403236B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534609A (en) * | 2008-03-12 | 2009-09-16 | 欣兴电子股份有限公司 | Circuit structure of circuit board and method for manufacture same |
| CN101702400A (en) * | 2009-11-16 | 2010-05-05 | 威盛电子股份有限公司 | Circuit substrate and technology thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI403236B (en) | 2013-07-21 |
| TW201134335A (en) | 2011-10-01 |
| CN101847586A (en) | 2010-09-29 |
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