CN101847444B - Shift register - Google Patents
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- CN101847444B CN101847444B CN201010202905A CN201010202905A CN101847444B CN 101847444 B CN101847444 B CN 101847444B CN 201010202905 A CN201010202905 A CN 201010202905A CN 201010202905 A CN201010202905 A CN 201010202905A CN 101847444 B CN101847444 B CN 101847444B
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Abstract
The invention discloses a shift register, which comprises an input end, an output end, an enabling controller, a pre-charging circuit, a first switch, a second switch and a third switch, wherein the input end is used for receiving a first driving signal; the output end is used for outputting a second driving signal; the enabling controller is coupled to the input end of the shift register and is used for outputting an enabling signal when receiving the first driving signal; the enabling signal is of opposite phase to the first driving signal; the pre-charging circuit comprises the input end, the output end, a receiving module, a starting module and a resetting module; the receiving module receives the driving signal received by the pre-charging circuit and outputs the received driving signal to the starting module; the starting module is used for outputting a pre-charging signal when receiving the driving signal; and the resetting module is coupled between the receiving module and the starting module and is used for receiving a resetting signal to reset the pre-charging signal. The shift register of the invention has a relatively higher driving force.
Description
The application is divided an application to what female case application (application number: 200710198744.9, denomination of invention: shift register and pre-charge circuit) proposed.
Technical field
The present invention relates to a kind of shift register; Relate in particular to a kind of shift register with more stable precharge potential.
Background technology
Please refer to Fig. 1.Fig. 1 is that prior art is with N type gold oxygen half (metal-oxide-semiconductor; MOS) synoptic diagram of the shift register of transistor technology.As shown in the figure, shift register 100 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 110, activation controller 120 and three switch Q
N2, Q
N3, Q
N4The input end I of shift register 100 is in order to receiving the drive signal of previous stage shift register, and output terminal O is then in order to the drive signal of Output Shift Register 100.Activation controller 120 comprises switch Q
N10And phase inverter INV
1Switch Q
N10First end be coupled to input end I, its control end is in order to receiving frequency signals CLK, switch Q
N10In order to its first end is coupled to its second end according to frequency signal CLK.Phase inverter INV
1Input end be coupled to switch Q
N10Second end, its output terminal is coupled to node N, in order to exporting node N to after the signals reverse that is received on the input end I.Pre-charge circuit 110 comprises switch Q
N1Switch Q
N1Control end be coupled to input end I, its first end is coupled to input end I, its second end then is coupled to node Z, in order to the signal on the input end I is sent to node Z with to node Z precharge.Switch Q
N2Control end be coupled to node N, its first end is coupled to node Z, its second end then is coupled to output terminal O.Switch Q
N3Control end be coupled to node Z, its first end is in order to receiving frequency signals XCK, its second end then is coupled to output terminal O.Frequency signal XCK voltage when high levle is 7.5 volts, and (setting high levle voltage at this is V
DD), voltage is 0 volt when low level.Above-mentioned high levle voltage and low level voltage can be set according to user's demand.This with high levle voltage be 7.5 volts with low level voltage to be 0 volt be example.Switch Q
N4Comprise control end and be coupled to node N, its first end is coupled to voltage source V
SS(at this setting voltage V
SSBe 0 volt), its second end then is coupled to output terminal O.In addition, because shift register 100 adopts N type MOS transistor technology, so switch Q
N1～Q
N4, Q
N10Be all N type MOS transistor.In addition, frequency signal CLK and XCK inversion signal each other.
Please refer to Fig. 2, Fig. 2 is the sequential chart of shift register 100 shown in Figure 1.As shown in the figure, (current potential is promoted to voltage V when input end I receives the drive signal of previous stage shift register
DD, time span is half frequency signal XCK), the drive signal of previous stage is sent to node Z and is sent to node N via activation controller 120 via pre-charge circuit 110 respectively; At this moment, the preceding semiperiod of frequency signal XCK is a low level.Because pre-charge circuit 110 is by switch Q
N1(N type MOS transistor) constitutes, so the current potential of node Z will be lowered a switch Q
N1Source-drain electrodes voltage V
DSVoltage V in the case
DSBe switch Q
D1Critical voltage V
TH1(set critical voltage V at this
TH1It is 2.5 volts).Therefore, the current potential of node Z is 5 volts of (V at this moment
DD-V
TH1).Activation controller 120 is by switch Q
N10With phase inverter INV
1Constitute, so node N will be by voltage V originally
DDDrop to voltage 0, and maintain the cycle of a frequency signal XCK.Because this moment, the current potential of node N was 0, can know switch Q by figure
N2With Q
N4To be closed.In the later half cycle of frequency signal XCK (voltage of frequency signal XCK maintains high levle), switch Q
N1, Q
N2, Q
N4All be closed condition, therefore the electric charge on node Z does not just have the dissipation approach.Because switch Q
N3Between its first end and control end, stray capacitance C is arranged
1, therefore working as switch Q
N3First end on the voltage of frequency signal XCK when rising to high levle by low level, the current potential of node Z also can be promoted a voltage V again
DDAnd become 12.5 volts of (2V
DD-V
TH1=2 * 7.5-2.5).Therefore, just can be with switch Q
N3Conducting and make the current potential of output terminal O be pulled up to voltage V
DD(7.5 volts) are with the drive signal as shift register 100.After rise to voltage V once again when the voltage of node N
DDThe time, switch Q
N2With Q
N4Be switched on, and just the voltage of output terminal O be pulled down to voltage V
SS(0 volt).
From the above, when shift register 100 output drive signals, the current potential of node Z is (2V
DD-V
TH1), the current potential of output terminal O is V
DD, so switch Q
N3Grid-source voltage V
GSShould be 5 volts of (2V
DD-V
TH1-V
DD=V
DD-V
TH1=7.5-2.5).Yet, the driving force of the output terminal O of shift register 100 and switch Q
N3Grid-source voltage V
GSRelevant (voltage V
GSMore greatly then driving force is strong more), and process factors can cause the critical voltage V of switch
THChange to some extent, the voltage V that therefore draws according to following formula
GS(V
DD-V
TH1) also can change, and then influence the driving force of shift register 100. thereupon
Please refer to Fig. 3, Fig. 3 is the synoptic diagram of master's shift register 200 with P type MOS transistor for prior art.As shown in the figure, shift register 200 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 210, activation controller 220 and three switch Q
P2, Q
P3, Q
P4The input end I of shift register 200 is in order to receive the drive signal of previous stage shift register, and the output terminal O of shift register 200 is in order to the drive signal of Output Shift Register 200.Activation controller 220 comprises switch Q
P10And phase inverter INV
2Switch Q
P10First end be coupled to input end I, its control end is in order to receiving frequency signals XCK, switch Q
P10In order to its first end is coupled to its second end according to frequency signal XCK.Phase inverter INV
1Input end be coupled to switch Q
P10Second end, its output terminal is coupled to node N, in order to exporting node N to after the signals reverse that is received on the input end I.Pre-charge circuit 210 comprises switch Q
P10Switch Q
P10Control end be coupled to input end I, its first end is coupled to input end I, its second end is coupled to node Z, in order to the signal on the input end I is sent to node Z with to node Z precharge.Switch Q
P2Control end be coupled to node N, its first end is coupled to node Z, its second end then is coupled to output terminal O.Switch Q
P3Control end be coupled to node Z, its first end is in order to receiving frequency signals CLK, its second end then is coupled to output terminal O.Frequency signal CLK voltage when high levle is V
DD(at this setting voltage V
DDBe 7.5 volts), voltage is 0 when low level.Switch Q
P4Control end be coupled to node N, its first end is coupled to voltage source V
DD(at this setting voltage V
DDBe 7.5 volts), its second end then is coupled to output terminal O.In addition, because shift register 200 is a P type MOS transistor technology, so switch Q
P1～Q
P4And Q
P10It all is P type MOS transistor.
Please refer to Fig. 4, Fig. 4 is the sequential chart of shift register 200 shown in Figure 3.As shown in the figure, (current potential is by V when input end I receives the drive signal of previous stage shift register
DDDrop to 0, keep the length of half frequency signal clk cycle), the drive signal of previous stage is sent to node Z via pre-charge circuit 210; The drive signal of previous stage is sent to node N via activation controller 220, and this moment preceding semiperiod of frequency signal CLK is a noble potential, and voltage is V
DDBecause pre-charge circuit 210 is by switch Q
P1(P type MOS transistor) constitutes, so the current potential of node Z will be raised a switch Q
P1Source-drain electrode voltage V
DS, in voltage V in the case
DSBe switch Q
P1Critical voltage V
TH2(establish critical voltage V
TH2It is 2.5 volts).Therefore, the current potential of node Z is 2.5 volts of (V at this moment
DD-V
DD+ V
TH2).Activation controller 120 is by switch Q
P10With phase inverter INV
2Constitute, so node N will rise to V by voltage 0 originally
DD, and keep the length in the cycle of a frequency signal CLK.Because this moment, the current potential of node N was V
DD, can know switch Q by figure
P2With Q
P1To be closed.In the later half cycle of frequency signal CLK (voltage of frequency signal CLK maintains 0 volt), switch Q
P1, Q
P2, Q
P4All be closed condition, therefore the electric charge on node Z does not just have the dissipation approach.Because switch Q
P3Between its first end and control end, stray capacitance C is arranged
2, therefore working as switch Q
P3First end on the voltage of frequency signal CLK by V
DDDrop at 0 o'clock, the current potential of node Z also can be by a drop-down voltage V again
DDAnd become-2.5 volts of (V
TH1-V
DD=2.5-5).Therefore, just can be with switch Q
P3Conducting and make the current potential of output terminal O be pulled down to 0 volt with drive signal as shift register 200.Afterwards when the voltage of node N drops to 0 volt once again, switch Q
P2With Q
P4Be switched on, and just the voltage of output terminal O be promoted to V
DD
From the above, when shift register 200 output drive signals, the current potential of node Z is (V
DD+ V
TH2), the current potential of output terminal O is 0 volt, so switch Q
P3Grid-source voltage V
GSShould be-5 volts of (V
DD+ V
TH2-0=-7.5+2.5).Yet, the driving force of the output terminal O of shift register 200 and switch Q
P3Grid-source voltage V
GSRelevant (voltage V
GSMore greatly then driving force is strong more), and process factors can cause the critical voltage V of switch
THChange, the voltage V that therefore draws according to following formula
GS(V
DD+ V
TH2) also can change, and then influenced the driving force of shift register 200. thereupon
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of shift register, to solve the problem of the shift register driving force difference of pre-charge circuit in the prior art.
For realizing above-mentioned purpose, the present invention provides a kind of shift register in addition.This shift register comprises input end, output terminal, activation controller, pre-charge circuit, first switch, second switch and the 3rd switch.This input end is in order to receive first drive signal.This output terminal is in order to export one second drive signal.This activation controller is coupled to the input end of this shift register, when being used to receive this first drive signal, and output enable signal.This enable signal is the anti-phase of this first drive signal.This pre-charge circuit comprises input end, output terminal, receiver module, startup module and replacement module.The input end of this pre-charge circuit is coupled to the input end of this shift register, in order to receive this first drive signal.The output terminal of this pre-charge circuit is in order to the output precharging signal.The receiver module of this pre-charge circuit comprises input end, control end and output terminal.The input end of the receiver module of this pre-charge circuit is coupled to the input end of this pre-charge circuit, in order to receive this first drive signal.The control end of the receiver module of this pre-charge circuit is in order to receive control signal.The output terminal of the receiver module of this pre-charge circuit when this receiver module receives this control signal, transmits this first drive signal.The startup module of this pre-charge circuit is coupled between the output terminal of output terminal and this pre-charge circuit of receiver module of this pre-charge circuit, when being used to receive this first drive signal, exports this precharging signal.The replacement module of this pre-charge circuit is coupled between the startup module of output terminal and this pre-charge circuit of receiver module of this pre-charge circuit, in order to receive reset signal with this precharging signal of resetting.This first switch comprises first end, control end and second end.First end of this first switch is in order to receive a frequency signal.The control end of this first switch is coupled to the output terminal of this pre-charge circuit, in order to receive this precharging signal.Second end of this first switch is coupled to the output terminal of this shift register, when being used to this first switch and receiving this precharging signal, is coupled to first end of this first switch.This second switch comprises first end, control end and second end.First end of this second switch is coupled to one first voltage source.The control end of second switch is coupled to the output terminal of this activation controller, in order to receive this enable signal.Second end of second switch is coupled to this output terminal of this shift register, when being used to this second switch and receiving this enable signal, is coupled to first end of this second switch.The 3rd switch comprises first end, control end and second end.First end of the 3rd switch is coupled to the output terminal of this pre-charge circuit.The control end of the 3rd switch is coupled to the output terminal of this activation controller, in order to receive this enable signal.Second end of the 3rd switch is coupled to the output terminal of this shift register, when being used to the 3rd switch and receiving this enable signal, is coupled to first end of the 3rd switch.
Wherein, this startup module comprises: one the 4th switch comprises: one first end is coupled to this output terminal of this pre-charge circuit; One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And one second end, be coupled to one second voltage source, when this control end that is used to the 4th switch receives this drive signal, be coupled to this first end of the 4th switch.
Wherein, this replacement module comprises: one the 5th switch comprises: one first end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; One control end is in order to receive this reset signal; And one second end, being coupled to this first bias generator, when being used to the 5th switch and receiving this reset signal, this first end that is coupled to the 5th switch is with this precharging signal of resetting.
Wherein, this startup module comprises in addition: an electric capacity is coupled between this control end of this first end and the 4th switch of the 4th switch; One the 6th switch comprises: one first end is coupled to this first end of the 4th switch; One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And one second end, when being used to the 6th switch and receiving this first drive signal, be coupled to this first end of the 6th switch; And a minion closes, and comprises: one first end is coupled to this second end of the 6th switch; One control end is in order to receive the inversion signal of this frequency signal; Reach one second end, be coupled to this output terminal of this pre-charge circuit, be used to this minion and close when receiving the inversion signal of this frequency signal, be coupled to this first end that this minion is closed.
Wherein, this startup module comprises in addition: an electric capacity is coupled between this control end of this first end and the 4th switch of the 4th switch; One the 6th switch comprises: one first end is coupled to this first end of the 4th switch; One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And one second end, when being used to the 6th switch and receiving this first drive signal, be coupled to this first end of the 6th switch; And a minion closes, and comprises: one first end is coupled to this second end of the 6th switch; One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; Reach one second end, be coupled to this output terminal of this pre-charge circuit, be used to this minion and close when receiving first drive signal, be coupled to this first end that this minion is closed.
Wherein, this receiver module comprises an octavo in addition and closes, and this octavo is closed and comprised: one first end couples this output terminal of this receiver module; One control end is coupled to this control end of this receiver module, in order to receive this control signal; Reach one second end, be coupled to this input end of this receiver module, be used to this octavo and close when receiving this control signal, be coupled to this first end that this octavo is closed.
Wherein, this control signal is the inversion signal of this first drive signal or this frequency signal.
Wherein, this reset signal is inversion signal or this second drive signal of this frequency signal.
Wherein, this activation controller comprises: one the 9th switch comprises: one first end is coupled to the input end of this shift register; One control end is in order to receive the inversion signal of this frequency signal; And one second end, when being used to the 9th switch and receiving this control signal, be coupled to this first end of the 9th switch; And a phase inverter, comprise: an input end is coupled to this second end of the 9th switch; Reach an output terminal, be coupled to this control end of this second switch.
And the present invention provides a kind of pre-charge circuit, and this pre-charge circuit comprises input end, output terminal, receiver module, startup module and replacement module.This input end is in order to receive drive signal.This output terminal is in order to the output precharging signal.This receiver module comprises input end, control end and output terminal.The input end of this receiver module is coupled to the input end of this pre-charge circuit, in order to receive this drive signal.The control end of this receiver module is in order to receive a control signal.When the output terminal of this receiver module receives this control signal in this receiver module, transmit this drive signal.This starts module, is coupled between the output terminal of this output terminal and this pre-charge circuit of this receiver module, when being used to receive this drive signal, exports this precharging signal.This replacement module is coupled between this output terminal and this startup module of this receiver module, in order to receive reset signal with this precharging signal of resetting.
Wherein, this replacement module comprises: a second switch comprises: one first end is coupled to this output terminal of this receiver module, in order to receive this drive signal; One control end is in order to receive this reset signal; And one second end, being coupled to one second voltage source, when being used to this second switch and receiving this reset signal, this first end that is coupled to this second switch is with this precharging signal of resetting.
Wherein, this startup module comprises in addition: one the 3rd switch comprises: one first end is coupled to this first end of this first switch; One control end is coupled to this output terminal of this receiver module, in order to receive this drive signal; And one second end, when this control end that is used to the 3rd switch receives this drive signal, be coupled to this first end of the 3rd switch; And one the 4th switch, comprise: one first end is coupled to this second end of the 3rd switch; One control end is in order to receive a frequency signal; And one second end, be coupled to this output terminal of this pre-charge circuit, when being used to the 4th switch and receiving this frequency signal, be coupled to this first end of the 4th switch.
Wherein, this receiver module comprises one the 5th switch in addition, and the 5th switch comprises: one first end couples this output terminal of this receiver module; One control end is coupled to this control end of this receiver module, in order to receive this control signal; And one second end, be coupled to this input end of this receiver module, when being used to the 5th switch and receiving this control signal, be coupled to this first end of the 5th switch.
Wherein, this control signal is this drive signal or a frequency signal.
Wherein, this reset signal is a frequency signal.
In sum, pre-charge circuit of the present invention can not receive technogenic influence, makes to utilize the shift register of pre-charge circuit of the present invention that preferable driving force can be arranged.
Describe the present invention below in conjunction with accompanying drawing and specific embodiment, but not as to qualification of the present invention.
Description of drawings
Fig. 1 is the synoptic diagram of prior art with the shift register of N type MOS transistor making;
Fig. 2 is the sequential chart of the shift register of Fig. 1;
Fig. 3 is the synoptic diagram of prior art with the shift register of P type MOS transistor making;
Fig. 4 is the sequential chart of shift register shown in Figure 3;
Fig. 5 is the synoptic diagram of shift register first embodiment of the present invention;
Fig. 6 is the sequential chart of shift register shown in Figure 5;
Fig. 7 is the synoptic diagram of shift register second embodiment of the present invention;
Fig. 8 is the synoptic diagram of shift register the 3rd embodiment of the present invention;
Fig. 9 is the synoptic diagram of shift register the 4th embodiment of the present invention;
Figure 10 is the synoptic diagram of shift register the 5th embodiment of the present invention;
Figure 11 is the synoptic diagram of shift register the 6th embodiment of the present invention.
Wherein, Reference numeral:
100,200,500,700,800,900,1000,1100: shift register
110,210,510,710,810,910,1010,1110: pre-charge circuit
120,220: the activation controller
511,711,811,911,1011,1111: receiver module
512,712,812,912,1012,1112: start module
513,713,813,913,1013,1113: the replacement module
V
DD, V
SS: voltage source
C
1～C
5: electric capacity
INV
1, INV
2: phase inverter
R
1, R
2: reset signal
E
1, E
2: control signal
O: output terminal
I: input end
Z, J, N: node
Q
N1～Q
N9, Q
N10: N type MOS transistor
Q
P1～Q
P9, Q
P10: P type MOS transistor
Embodiment
Please refer to Fig. 5.Fig. 5 is the synoptic diagram of shift register first embodiment of the present invention.Shift register 500 is an example with N type MOS transistor.As shown in the figure, shift register 500 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 510, activation controller 120 and three switch Q
N2, Q
N3, Q
N4The input end I of shift register 500 is in order to receive the drive signal of previous stage shift register, and the output terminal O of shift register 500 is in order to the drive signal of Output Shift Register 500.Activation controller 120 comprises switch Q
N10And phase inverter INV
1Switch Q
N10First end be coupled to input end I, its control end is in order to receiving frequency signals CLK, switch Q
N10In order to its first end is coupled to its second end according to frequency signal CLK.Phase inverter INV
1Input end be coupled to switch Q
N10Second end, its output terminal is coupled to node N, in order to exporting node N to after the signals reverse that is received on the input end I.Pre-charge circuit 510 comprises receiver module 511, starts module 512, replacement module 513 and node J.Switch Q
N2Control end be coupled to node N, its first end is coupled to node Z, its second end then is coupled to output terminal O.Switch Q
N3Control end be coupled to node Z, its first end is in order to receiving frequency signals XCK, its second end then is coupled to output terminal O.Frequency signal XCK voltage when high levle is V
DD(at this setting voltage V
DDBe 7.5 volts), voltage is 0 when low level.Switch Q
N4Control end be coupled to node N, its first end is coupled to voltage source V
SS(at this setting voltage V
SSBe 0 volt), its second end then is coupled to output terminal O.
Please refer to Fig. 6.Fig. 6 is the sequential chart of shift register 500 shown in Figure 5.As shown in the figure, (current potential is promoted to V when input end I receives the drive signal of previous stage shift register
DD, and keep the length of half frequency signal XCK), the drive signal of previous stage is sent to node Z and is sent to node N via activation controller 120 via pre-charge circuit 510 respectively, and this moment preceding semiperiod of frequency signal XCK is an electronegative potential, and voltage is 0.At this moment, in the pre-charge circuit 510, the switch Q of receiver module 511
N5Because control signal E
1And the drive signal of previous stage is sent to node J.Because switch Q
N5Be N type MOS transistor, so the current potential of node J will be lowered a switch Q
N5Source-drain electrode voltage V
DS, in voltage V in the case
DSBe switch Q
N5Critical voltage V
TH5(set critical voltage V at this
TH5It is 2.5 volts).Therefore, the current potential of node J is 5 volts of (V at this moment
DD-V
TH5).Start the switch Q of module 512
N6The conducting because the current potential of node J rises, and the current potential of node Z is promoted to V
DDThe electrical potential energy of node Z is promoted to V this moment
DDBe because switch Q
N6Because stray capacitance C is arranged between node J and Z
3, and rise to V when the voltage of node Z
DDThe time, can be to capacitor C
3The charging and make the current potential of node J rise to voltage (V again
DD+ V
TH6), so just can maintained switch Q
N6Conducting and the current potential of node Z maintains V
DDActivation controller 120 is by phase inverter INV
1Constitute, so node N will be by V originally
DDDrop to voltage 0, and keep the length in the cycle of a frequency signal XCK.Because this moment, the current potential of node N was 0, can know switch Q by figure
N2With Q
N4To be closed.(voltage of frequency signal XCK maintains V in the later half cycle of frequency signal XCK
DD) in, switch Q
N1, Q
N2, Q
N4All be closed condition, therefore the electric charge on node Z does not just have the dissipation approach.Because switch Q
N3Between its first end and control end, stray capacitance C is arranged
1, therefore working as switch Q
N3First end on the voltage of frequency signal XCK rise to V by 0
DDThe time, the current potential of node Z also can be promoted a voltage V again
DDAnd become 15 volts of (2V
DD=2 * 7.5), so just can be with switch Q
N3Conducting and make the current potential of output terminal O be pulled up to V
DD, with drive signal as shift register 500.Voltage as node N rises to V once again afterwards
DDThe time, switch Q
N2With Q
N4Be switched on, and just the voltage of output terminal O be pulled down to V
SSReplacement module 513 also receives reset signal R this moment
1, with switch Q
N7Conducting, and drop-down the current potential of node J, and then close the switch Q that starts module 512
N6And stop to promote the current potential of node Z.
Reset signal R
1The inversion signal (CLK) that can be frequency signal XCK perhaps (is anticipated and is about to switch Q for the drive signal of shift register 500
N7Be coupled to output terminal O); Control signal E
1Can use the drive signal (meaning promptly is coupled to input end I) of previous stage shift register or be the inversion signal (CLK) of frequency signal XCK.
From the above, when shift register 500 output drive signals, the current potential of node Z is (2V
DD), the current potential of output terminal O is V
DD, so switch Q
N3Grid-source voltage V
GSShould be 7.5 volts of (2V
DD-V
DD=V
DD).Yet, the driving force of the output terminal O of shift register 100 and switch Q
N3Grid-source voltage V
GSRelevant, also be voltage V
GSBigger, driving force is strong more; Therefore, the voltage V that draws according to following formula
GS(V
DD) can not receive the caused V of process relation
THChange influence, therefore high and stable driving force are arranged.
Please refer to Fig. 7.The synoptic diagram of Fig. 7 shift register second embodiment of the present invention.Shift register 700 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 710, activation controller 120 and three switch Q
N2, Q
N3, Q
N4 Pre-charge circuit 710 comprises receiver module 711, starts module 712, replacement module 713 and node J.Shift register 700 is similar with shift register 500, and the different startup modules 712 that are in the pre-charge circuit 710 of shift register 700 start module 512 and increased capacitor C newly
4With two switch Q
N8And Q
N9Capacitor C
4Be coupled to node J and switch Q
N6Second end between.Switch Q
N8Control end be coupled to node J, its first end is coupled to switch Q
N6Second end.Switch Q
N9Control end be coupled to node J, its first end is coupled to switch Q
N8Second end, its second end then is coupled to node Z.Switch Q
N8And Q
N9It all is N type MOS transistor.
Please refer to Fig. 8.Fig. 8 is the synoptic diagram of shift register the 3rd embodiment of the present invention.Shift register 800 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 810, activation controller 120 and three switch Q
N2, Q
N3, Q
N4 Pre-charge circuit 810 comprises receiver module 811, starts module 812, replacement module 813 and node J.Shift register 800 is similar with shift register 500, and difference is that the startup module 812 in the pre-charge circuit 810 of shift register 800 starts module 512 and increased capacitor C newly
4With two switch Q
N8And Q
N9Capacitor C
4Be coupled to node J and switch Q
N6Second end between.Switch Q
N8Control end be coupled to node J, its first end is coupled to switch Q
N6Second end.Switch Q
N9Control end in order to the inversion signal (CLK) of receiving frequency signals XCK, its first end is coupled to switch Q
N8Second end, its second end then is coupled to node Z.Switch Q
N8, Q
N9It all is N type MOS transistor.
Please refer to Fig. 9.Fig. 9 is the synoptic diagram of shift register the 4th embodiment of the present invention.Shift register 900 is made with P type MOS transistor.As shown in the figure, shift register 900 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 910, activation controller 220 and three switch Q
P2, Q
P3, Q
P4The input end I of shift register 900 is in order to receive the drive signal of previous stage shift register, and the output terminal O of shift register 900 is in order to the drive signal of Output Shift Register 900.Activation controller 220 comprises switch Q
P10And phase inverter INV
2Switch Q
P10First end be coupled to input end I, its control end is in order to receiving frequency signals XCK, switch Q
P10In order to its first end is coupled to its second end according to frequency signal XCK.Phase inverter INV
2Input end be coupled to switch Q
P10Second end, its output terminal is coupled to node N, in order to exporting node N to after the signals reverse that is received on the input end I.Pre-charge circuit 910 comprises receiver module 911, starts module 912, replacement module 913 and node J.Switch Q
P2Control end be coupled to node N, its first end is coupled to node Z, its second end then is coupled to output terminal O.Switch Q
P3Control end be coupled to node Z, its first end is in order to receiving frequency signals CLK, its second end then is coupled to output terminal O.Frequency signal CLK voltage when high levle is V
DD(set V at this
DDBe 7.5 volts), voltage is 0 when low level.Switch Q
P4Control end be coupled to node N, its first end is coupled to voltage source V
DD, its second end is coupled to output terminal O.
Because shift register 900 is made with P type MOS transistor, so switch Q
P2～Q
P7And Q
P10It all is P type MOS transistor.
The related work principle of shift register 900 is similar with the principle of work of shift register 500, therefore repeats no more.
Reset signal R
2The inversion signal (XCK) that can be frequency signal CLK perhaps (also is about to switch Q for the drive signal of shift register 900
P7Be coupled to output terminal O); Control signal E
2Can use the drive signal (also promptly being coupled to input end I) of previous stage shift register or be the inversion signal (XCK) of frequency signal CLK.
Please refer to Figure 10.Figure 10 is the synoptic diagram of shift register the 5th embodiment of the present invention.Shift register 1000 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 1010, activation controller 220 and three switch Q
P2, Q
P3, Q
P4 Pre-charge circuit 1010 comprises receiver module 1011, starts module 1012, replacement module 1013 and node J.Shift register 1000 is similar with shift register 900, and difference is that the startup module 1012 in the pre-charge circuit 1010 of shift register 1000 starts module 912 and increased capacitor C newly
5With two switch Q
P8And Q
P9Capacitor C
5Be coupled to node J and switch Q
P6Second end between.Switch Q
P8Control end be coupled to node J, its first end is coupled to switch Q
P6Second end.Switch Q
P9Control end be coupled to node J, its first end is coupled to switch Q
P8Second end, its second end then is coupled to node Z.Switch Q
P8And Q
P9It all is P type MOS transistor.
Please refer to Figure 11.Figure 11 is the synoptic diagram of shift register the 6th embodiment of the present invention.Shift register 1100 comprises input end I, node Z, node N, output terminal O, pre-charge circuit 1110, activation controller 220 and three switch Q
P2, Q
P3, Q
NP4 Pre-charge circuit 1110 comprises receiver module 1111, starts module 1112, replacement module 1113 and node J.Shift register 1100 is similar with shift register 900, and difference is that the startup module 1112 in the pre-charge circuit 1110 of shift register 1100 starts module 912 and increased capacitor C newly
5With two switch Q
P8And Q
P9Capacitor C
5Be coupled to node J and switch Q
P6Second end between.Switch Q
P8Control end be coupled to node J, its first end is coupled to switch Q
P6Second end.Switch Q
P9Control end in order to the inversion signal (XCK) of receiving frequency signals CLK, its first end is coupled to switch Q
P8Second end, its second end is coupled to node Z.Switch Q
P8And Q
P9It all is P type MOS transistor.
In sum, pre-charge circuit of the present invention can not receive technogenic influence, makes to utilize the shift register of pre-charge circuit of the present invention that preferable driving force can be arranged.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. a shift register is characterized in that, comprises input end, output terminal, activation controller, pre-charge circuit, first switch, second switch and the 3rd switch, wherein:
This input end is in order to receive one first drive signal;
This output terminal is in order to export one second drive signal;
This activation controller is coupled to the input end of this shift register, when being used to receive this first drive signal, exports an activation signal; This enable signal is the anti-phase of this first drive signal;
This pre-charge circuit comprises an input end, an output terminal, a receiver module, a startup module and a replacement module, wherein:
This input end is coupled to the input end of this shift register, in order to receive this first drive signal;
This output terminal is in order to export a precharging signal;
This receiver module comprises an input end, is coupled to the input end of this pre-charge circuit, in order to receive this first drive signal; One control end is in order to receive a control signal; And an output terminal, when this receiver module receives this control signal, transmit this first drive signal;
This startup module is coupled between the output terminal of this output terminal and this pre-charge circuit of this receiver module, when being used to receive this first drive signal, exports this precharging signal; And
This replacement module is coupled between this output terminal and this startup module of this receiver module, in order to receive a reset signal with this precharging signal of resetting;
This first switch comprises: one first end, in order to receive a frequency signal; One control end is coupled to this output terminal of this pre-charge circuit, in order to receive this precharging signal; And one second end, be coupled to this output terminal of this shift register, when being used to this first switch and receiving this precharging signal, be coupled to this first end of this first switch;
This second switch comprises: one first end is coupled to one first voltage source; One control end is coupled to an output terminal of this activation controller, in order to receive this enable signal; And one second end, be coupled to this output terminal of this shift register, when being used to this second switch and receiving this enable signal, be coupled to this first end of this second switch; And
The 3rd switch comprises: one first end is coupled to this output terminal of this pre-charge circuit; One control end is coupled to this output terminal of this activation controller, in order to receive this enable signal; And one second end, be coupled to this output terminal of this shift register, when being used to the 3rd switch and receiving this enable signal, be coupled to this first end of the 3rd switch.
2. shift register according to claim 1 is characterized in that, this startup module comprises:
One the 4th switch comprises:
One first end is coupled to this output terminal of this pre-charge circuit;
One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And
One second end is coupled to one second voltage source, when this control end that is used to the 4th switch receives this first drive signal, is coupled to this first end of the 4th switch.
3. shift register according to claim 1 is characterized in that, this replacement module comprises:
One the 5th switch comprises:
One first end is coupled to this output terminal of this receiver module, in order to receive this first drive signal;
One control end is in order to receive this reset signal; And
One second end is coupled to one first bias generator, and when being used to the 5th switch and receiving this reset signal, this first end that is coupled to the 5th switch is with this precharging signal of resetting.
4. shift register according to claim 2 is characterized in that, this startup module comprises in addition:
One electric capacity is coupled between this control end of this first end and the 4th switch of the 4th switch;
One the 6th switch comprises:
One first end is coupled to this first end of the 4th switch;
One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And
One second end when being used to the 6th switch and receiving this first drive signal, is coupled to this first end of the 6th switch; And
One minion is closed, and comprises:
One first end is coupled to this second end of the 6th switch;
One control end is in order to receive the inversion signal of this frequency signal; And
One second end is coupled to this output terminal of this pre-charge circuit, is used to this minion and closes when receiving the inversion signal of this frequency signal, is coupled to this first end that this minion is closed.
5. shift register according to claim 2 is characterized in that, this startup module comprises in addition:
One electric capacity is coupled between this control end of this first end and the 4th switch of the 4th switch;
One the 6th switch comprises:
One first end is coupled to this first end of the 4th switch;
One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And
One second end when being used to the 6th switch and receiving this first drive signal, is coupled to this first end of the 6th switch; And
One minion is closed, and comprises:
One first end is coupled to this second end of the 6th switch;
One control end is coupled to this output terminal of this receiver module, in order to receive this first drive signal; And
One second end is coupled to this output terminal of this pre-charge circuit, is used to this minion and closes when receiving first drive signal, is coupled to this first end that this minion is closed.
6. shift register according to claim 1 is characterized in that, this receiver module comprises an octavo in addition and closes, and this octavo is closed and comprised:
One first end couples this output terminal of this receiver module;
One control end is coupled to this control end of this receiver module, in order to receive this control signal; And
One second end is coupled to this input end of this receiver module, is used to this octavo and closes when receiving this control signal, is coupled to this first end that this octavo is closed.
7. shift register according to claim 1 is characterized in that, this control signal is the inversion signal of this first drive signal or this frequency signal.
8. shift register according to claim 1 is characterized in that, this reset signal is inversion signal or this second drive signal of this frequency signal.
9. shift register according to claim 1 is characterized in that, this activation controller comprises:
One the 9th switch comprises:
One first end is coupled to the input end of this shift register;
One control end is in order to receive the inversion signal of this frequency signal; And
One second end when being used to the 9th switch and receiving this control signal, is coupled to this first end of the 9th switch; And
One phase inverter comprises:
One input end is coupled to this second end of the 9th switch; And
One output terminal is coupled to this control end of this second switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010202905A CN101847444B (en) | 2007-12-12 | 2007-12-12 | Shift register |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010202905A CN101847444B (en) | 2007-12-12 | 2007-12-12 | Shift register |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101987449A Division CN101178939B (en) | 2007-12-12 | 2007-12-12 | Displacement register and pre-charge circuit |
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| Publication Number | Publication Date |
|---|---|
| CN101847444A CN101847444A (en) | 2010-09-29 |
| CN101847444B true CN101847444B (en) | 2012-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010202905A Active CN101847444B (en) | 2007-12-12 | 2007-12-12 | Shift register |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655223A (en) * | 2004-02-10 | 2005-08-17 | 夏普株式会社 | Driver circuit for display device and display device |
| CN1674084A (en) * | 2004-03-17 | 2005-09-28 | 夏普株式会社 | Driving device of display device, display device, and driving method of display device |
-
2007
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655223A (en) * | 2004-02-10 | 2005-08-17 | 夏普株式会社 | Driver circuit for display device and display device |
| CN1674084A (en) * | 2004-03-17 | 2005-09-28 | 夏普株式会社 | Driving device of display device, display device, and driving method of display device |
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| Publication number | Publication date |
|---|---|
| CN101847444A (en) | 2010-09-29 |
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