CN101847374B

CN101847374B - Driving device, shift device, buffer, shift register and driving method

Info

Publication number: CN101847374B
Application number: CN2009100483646A
Authority: CN
Inventors: 郑泰宝; 陈飞
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2009-03-23
Filing date: 2009-03-23
Publication date: 2012-10-31
Anticipated expiration: 2029-03-23
Also published as: CN101847374A

Abstract

The invention discloses a driving device, a shifting register, a buffer, a liquid crystal display and a driving method, wherein the driving device comprises: the shift unit comprises at least two stages of shift registers connected in series, and the shift register of the nth stage outputs the shift data of the nth stage and the reverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage and the reverse phase data of the shift data of the (n-1) th stage; and the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, and n is a natural number. The shift data are transmitted between the shift registers of the shift unit in a unidirectional mode, so that the buffer of a certain stage has a problem and cannot influence the connected shift register, and the accuracy of the driving device is higher.

Description

Drive unit, shift unit, impact damper, shift register and driving method

Technical field

The present invention relates to technical field of manufacturing semiconductors, particularly drive unit, shift unit, shift register, impact damper, LCD and driving method.

Background technology

(Liquid Crystal Display LCD) possesses plurality of advantages such as frivolous, energy-conservation, radiationless to LCD, has therefore replaced traditional cathode ray tube (CRT) display gradually.LCD is widely used in the electronic equipments such as HD digital TV, desk-top computer, PDA(Personal Digital Assistant), notebook computer, mobile phone, digital camera at present.

LCD (LCD) generally is made up of display panels and outside driving circuit thereof.Fig. 1 is the schematic equivalent circuit according to a kind of LCD of prior art.As shown in Figure 1, LCD comprises display panels 10, data driven unit 20 and gate drive apparatus 30.Display panels 10 has two glass substrates up and down, between two glass substrates, has liquid crystal.Data line 21 is arranged on the lower glass substrate of display panels 10 with gate line 31.Wherein, Display panels 10 also comprises the capable xj row of the i pixel cell 11 by matrix arrangements; Drive unit 30 is electrically connected with i bar gate line 31, and data driven unit 20 is electrically connected with j bar data line 21, data line 21 and gate line 31 arranged crosswise; Pixel cell 11 is provided with a TFT (thin film transistor (TFT), thin-film-transistor) 12 on each point of crossing.Grid with the TFT12 of delegation is connected on the same gate line 31, and the TFT12 response is from the scanning impulse of gate line 31.1 grade of displacing part and 1 grade of 1 grade of shift module that buffer portion is formed; Drive unit 30 comprises multistage shift module, the output of 1 grade of shift module of each row gate line 31 corresponding drive unit 30, shift module be used for being shifted the successively initial pulse of each horizontal cycle; Produce the one scan pulse; Export to the grid of TFT12 in the pixel cell 11 then, the TFT12 of correspondence is opened, data driven unit 20 is used for voltage being inputed to the electric capacity that links to each other with TFT12 through data line 21.

Shown in Figure 2 is a kind of structural representation of existing gate drive apparatus 30, has wherein adopted amorphous silicon manufacturing grid drive unit 30.Amorphous silicon gate could electrode driving device 30 is usually by multistage shift module series connection; Each grade shift module all need feed back to the driving data that the buffer portion of next stage shift module is exported the displacing part of upper level and could work; If the buffer portion generation problem of certain one-level shift module, the output of whole shift module all can be wrong.The 1st grade of shift module for example shown in Figure 2 receives the shifted data of the 2nd grade of shift module output, and exports the driving data Gate (1) of this grade; The 2nd grade of shift module receives the shifted data of 3rd level shift module output, and exports the driving data Gate (2) of this grade; The 3rd level shift module receives the shifted data of the 4th grade of shift module output, and exports the driving data Gate (3) of this grade; N-1 level shift module receives the shifted data of n level shift module output, and exports the driving data Gate (n-1) of this grade.

From above-mentioned analysis, can know; The shifted data of the gate drive apparatus of LCD of the prior art is bi-directional between shift modules at different levels; The correctness of the output driving data of each grade shift module all depends on the correctness of the driving data of next stage shift module output; If wherein the buffer portion of one-level is made mistakes and made mistakes with regard to the output that causes whole shift module, therefore the accuracy of existing gate drive apparatus is relatively poor.

Summary of the invention

The purpose of this invention is to provide drive unit, shift unit, shift register, impact damper, LCD and driving method, improved the accuracy of drive unit output.

In order to address the above problem this, invention provides a kind of drive unit, comprising:

Shift unit; Said shift unit comprises the shift register of two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data;

Buffer cell, said buffer cell comprise two-stage impact damper at least, and said impact damper links to each other with said shift register, output drive signal, and wherein, n is a natural number.

Preferably, n level shift register connects the said impact damper of n level, and said n level impact damper is exported n level drive signal.

Preferably, said shift register is used for the antiphase data of shifted data and shifted data are shifted respectively, comprising:

Switch element, with the antiphase data of said shifted data and shifted data, and the connection of shift clock signal, be used to control the open and close of said shift register;

The high level output unit is connected with said switch element with high level, and the signal of exporting according to switch element makes said shift register output high level;

The low level output unit is connected with said switch element with low level, and the signal of exporting according to switch element makes said shift register output low level.

Preferably, the structure of said switch element is a symmetrical structure, and said symmetrical structure is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

Preferably; The structure of said high level output unit is a symmetrical structure; Said symmetrical structure is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level; The output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

Preferably; The structure of said low level output unit is a symmetrical structure; Said symmetrical structure is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level; The output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

Preferably; Said first switch element is a first transistor; Said second switch unit is a transistor seconds, and the said first high level output unit is the 3rd transistor, and the said second high level output unit is the 4th transistor; The said first low level output unit is the 5th transistor, and the said second low level output unit is the 6th transistor.

Preferably; N level shift register in the said shift unit comprises plurality of transistors, and wherein, the source electrode of the first transistor is imported n-1 level shifted data; The grid of the first transistor is imported n level shift clock signal, and the drain electrode of the first transistor and the 3rd transistorized grid couple; The source electrode of transistor seconds is imported the antiphase data of n-1 level shifted data, and the grid of transistor seconds is imported n level shift clock signal, and the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of n level shift register, and the 4th transistor drain couples second output terminal of n level register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, the 5th transistorized source electrode input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

Preferably, described impact damper comprises:

Pull-up unit is connected with the output terminal of buffered clock signal and said impact damper, makes said impact damper output high level according to the buffered clock signal;

Drop-down unit, said drop-down unit comprises the first drop-down unit, the second drop-down unit, and control the switch element that the first drop-down unit opens and closes, make said impact damper output low level according to the buffered clock signal.

Preferably, said pull-up unit is for pulling up transistor, and the said first drop-down unit is first pull-down transistor, and the said second drop-down unit is second pull-down transistor, and the switch element that the said control first drop-down unit opens and closes is a switching transistor.

Preferably, the n level impact damper of described buffer cell comprises plurality of transistors, wherein; The source electrode that pulls up transistor and the source electrode of switching transistor couple; As the input end of n level impact damper, said input end is imported the second buffered clock signal, and the said grid that pulls up transistor is imported n level shifted data; The said drain electrode that pulls up transistor couples the output terminal of said n level impact damper; The grid of said switching transistor is imported the antiphase data of n level shifted data, and the drain electrode of said switching transistor couples the first pull-down transistor grid, and the source electrode of first pull-down transistor is imported the first buffered clock signal; The drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said n level impact damper; The grid of said second pull-down transistor is imported the said first buffered clock signal, and the source electrode of said second pull-down transistor is imported the second buffered clock signal, and the output terminal of said n level impact damper is exported n level drive signal.

Preferably, n level shift register connects two-stage impact damper at least, and every grade of said impact damper output one-level drive signal.

Preferably, n level shift register connects 2n level and 2n-1 level impact damper, and said 2n-1 level impact damper is exported 2n-1 level drive signal, and said 2n level impact damper is exported 2n level drive signal.

Preferably; N level shift register in the said shift unit comprises plurality of transistors, and wherein, the source electrode of the first transistor is imported n-1 level shifted data; The grid of the first transistor is imported n level shift clock signal, and the drain electrode of the first transistor and the 3rd transistorized grid couple; The source electrode of transistor seconds is imported the antiphase data of n-1 level shifted data, and the grid of transistor seconds is imported n level shift clock signal, and the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of n level shift register, and the 4th transistor drain couples second output terminal of n level shift register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, the 5th transistorized source electrode input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

Preferably, described impact damper comprises:

Preferably, the 2n-1 level impact damper of described buffer cell comprises plurality of transistors, wherein,

The source electrode that pulls up transistor and the source electrode of switching transistor couple; Input end as 2n-1 level impact damper; The said input end input right side first buffered clock signal; The said grid that pulls up transistor is imported n level shifted data, and the said drain electrode that pulls up transistor couples the output terminal of said 2n-1 level impact damper, and the grid of said switching transistor is imported the antiphase data of n level shifted data; The drain electrode of said switching transistor couples the first pull-down transistor grid; The source electrode input right side second buffered clock signal of first pull-down transistor, the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said 2n-1 level impact damper, and the grid of said second pull-down transistor is imported the said right side second buffered clock signal; The source electrode input right side first buffered clock signal of said second pull-down transistor, the output terminal of said 2n-1 level impact damper is exported 2n-1 level drive signal;

The 2n level impact damper of described buffer cell comprises plurality of transistors; Wherein, the source electrode that pulls up transistor and the source electrode of switching transistor couple, as the input end of 2n level impact damper; The said input end input left side second buffered clock signal; The said grid that pulls up transistor is imported n level shifted data, and the said drain electrode that pulls up transistor couples the output terminal of said impact damper, and the grid of said switching transistor is imported the antiphase data of n level shifted data; The drain electrode of said switching transistor couples the grid of first pull-down transistor; The source electrode input left side first buffered clock signal of said first pull-down transistor, the grid of second pull-down transistor is also imported the said left side first buffered clock signal, and the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said 2n level impact damper; The source electrode input left side second buffered clock signal of said second pull-down transistor, the output terminal of said 2n level impact damper is exported 2n level drive signal.

Preferably, the grid of the first transistor of the source electrode of the grid of said second pull-down transistor of said 2n level impact damper, said first pull-down transistor, said n level shift register and the grid of transistor seconds couple; The grid of the first transistor of the source electrode that pulls up transistor of said 2n level impact damper, the source electrode of second pull-down transistor and n+1 level shift register and the grid of transistor seconds couple.

Preferably, said drive unit comprises two said shift units, is respectively left side shift unit and right side shift unit; Said drive unit comprises two said buffer cells, is respectively left side buffer cell and right side buffer cell; Wherein, Said left side shift unit links to each other with said left side buffer cell; The left side n level shift register of left side shift unit connects the left side n level impact damper of said left side buffer cell; Said left side n level impact damper is according to left side n level buffered clock signal and left side n level shifted data, and the antiphase data of left side n level shifted data, exports 2n-1 level drive signal;

Said right side shift unit links to each other with said right side buffer cell; The right side n level shift register of right side shift unit connects the right side n level impact damper of said right side buffer cell; Said right side n level impact damper is according to right side n level buffered clock signal and right side n level shifted data; And the antiphase data of right side n level shifted data, export 2n level drive signal.

Preferably, left side n level buffered clock signal comprises left side first buffered clock signal and the left side second buffered clock signal; Right side n level buffered clock signal comprises right side first buffered clock signal and the right side second buffered clock signal;

Described left side n level impact damper comprises plurality of transistors; Wherein, The source electrode that pulls up transistor and the source electrode of switching transistor couple; As the input end of left side n level impact damper, the said input end input left side second buffered clock signal, the said grid input left side n level shifted data that pulls up transistor; The said drain electrode that pulls up transistor couples the output terminal of said left side n level impact damper; The antiphase data of the grid input left side n level shifted data of said switching transistor, the drain electrode of said switching transistor couples the first pull-down transistor grid, the source electrode input left side first buffered clock signal of first pull-down transistor; The drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said left side n level impact damper; The grid of said second pull-down transistor is imported the said left side first buffered clock signal, the source electrode input left side second buffered clock signal of said second pull-down transistor, and the output terminal of said left side n level impact damper is exported 2n-1 level drive signal;

The right side n level impact damper of described right side buffer cell comprises plurality of transistors; Wherein, The source electrode that pulls up transistor and the source electrode of switching transistor couple; As the input end of right side n level impact damper, the said input end input right side second buffered clock signal, the said grid input right side n level shifted data that pulls up transistor; The said drain electrode that pulls up transistor couples the output terminal of right side n level impact damper; The antiphase data of the grid input right side n level shifted data of said switching transistor, the drain electrode of said switching transistor couples the first pull-down transistor grid, the source electrode input right side first buffered clock signal of first pull-down transistor; The drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said right side n level impact damper; The grid input right side first buffered clock signal of said second pull-down transistor, the source electrode input right side second buffered clock signal of said second pull-down transistor, the output terminal of said right side n level impact damper is exported 2n level drive signal.

Preferably, said drive unit comprises two said shift units, is respectively left side shift unit and right side shift unit; Said drive unit comprises two said buffer cells, is respectively left side buffer cell and right side buffer cell; Wherein, said left side shift unit links to each other with said left side buffer cell, exports n level drive signal; Said right side shift unit links to each other with said right side buffer cell, exports n level drive signal.

Preferably, the left side n level shift register of said left side shift unit connects the left side n level impact damper of said left side buffer cell, and said left side n level impact damper is exported n level drive signal; The right side n level shift register of said right side shift unit connects said right side n level impact damper, and said right side n level impact damper is exported n level drive signal.

Preferably; The left side n level shift register of said left side shift unit connects the left side 2n-1 level impact damper of said left side buffer cell and the left side 2n level impact damper of said left side buffer cell; Said left side 2n level impact damper is exported 2n level drive signal, and said left side 2n-1 level impact damper is exported 2n-1 level drive signal;

The right side n level shift register of said right side shift unit connects the right side 2n level impact damper of said right side 2n-1 level impact damper and said right side buffer cell; Said right side 2n level impact damper is exported 2n level drive signal, and said right side 2n-1 level impact damper is exported 2n-1 level drive signal.

Accordingly; The present invention also provides a kind of shift register; Be used for the antiphase data of shifted data and shifted data are shifted respectively, comprise: switch element, with the antiphase data of said shifted data and shifted data; And the connection of shift clock signal, be used to control the open and close of said shift register; The high level output unit is connected with said switch element with high level, and the signal of exporting according to switch element makes said shift register output high level; The low level output unit is connected with said switch element with low level, and the signal of exporting according to switch element makes said shift register output low level.

Preferably, the structure of said switch element is a symmetrical structure.

Preferably, the symmetrical structure of said switch element is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

Preferably, the structure of said high level output unit is a symmetrical structure.

Preferably; The symmetrical structure of said high level output unit is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level; The output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

Preferably, the structure of said low level output unit is a symmetrical structure.

Preferably; The symmetrical structure of said low level output unit is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level; The output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

Preferably, the source electrode of the first transistor input shifted data, the grid input shift clock signal of the first transistor, the drain electrode of the first transistor and the 3rd transistorized grid couple; The antiphase data of the source electrode input shifted data of transistor seconds, the grid input shift clock signal of transistor seconds, the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of shift register, and the 4th transistor drain couples second output terminal of shift register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, and the 5th transistorized source electrode couples input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

Accordingly; The present invention also provides a kind of shift unit; Comprise the shift register of two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data.

Accordingly, the present invention also provides a kind of impact damper to comprise:

Preferably, the source electrode that pulls up transistor and the source electrode of switching transistor couple, as the input end of impact damper; Said input end is imported the second buffered clock signal; The said grid input shifted data that pulls up transistor, the said drain electrode that pulls up transistor couples the output terminal of said impact damper, the antiphase data of the grid input shifted data of said switching transistor; The drain electrode of said switching transistor couples the first pull-down transistor grid; The source electrode of first pull-down transistor is imported the first buffered clock signal, and the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said impact damper, and the grid of said second pull-down transistor is imported the said first buffered clock signal; The source electrode of said second pull-down transistor is imported the second buffered clock signal, the output terminal output drive signal of said impact damper.

Accordingly, the present invention also provides a kind of driving method of above-mentioned drive unit, comprises step:

Import the oppisite phase data of n-1 level shifted data and said n-1 level shifted data to n level shift register; According to n level shift clock signal; And the oppisite phase data of said n-1 level shifted data and said n-1 level shifted data, export the oppisite phase data of n level shifted data and said n level shifted data;

The oppisite phase data of said n level shifted data and said n level shifted data is inputed to n level impact damper; Said n level impact damper is according to n level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data; Export n level drive signal, wherein, n is a natural number.

Preferably; Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; And said n level shift clock signal high level lasting time is a half in its cycle; The said n level drive signal of output is a single pulse signal, and its high level lasting time is the half the of said n level shift clock signal period.

Preferably; When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; And said n level shift clock signal high level lasting time is a half in its cycle; The said n level drive signal of output is the dipulse signal, and wherein each high level lasting time is the half the of said n level shift clock signal period.

N level shift register is imported the oppisite phase data of left side n-1 level shifted data and said left side n-1 level shifted data to the left; According to left side n level shift clock signal; And the oppisite phase data of said left side n-1 level shifted data and said left side n-1 level shifted data, the oppisite phase data of output left side n level shifted data and said left side n level shifted data;

The oppisite phase data of said left side n level shifted data and said left side n level shifted data is inputed to left side n level impact damper; Said left side n level impact damper is according to left side n level buffered clock signal; And the oppisite phase data of said left side n level shifted data and said left side n level shifted data, export 2n-1 level drive signal;

N level shift register is imported the oppisite phase data of right side n-1 level shifted data and said right side n-1 level shifted data to the right; According to right side n level shift clock signal; And the oppisite phase data of said right side n-1 level shifted data and said right side n-1 level shifted data, the oppisite phase data of output right side n level shifted data and said right side n level shifted data;

The oppisite phase data of said right side n level shifted data and said right side n level shifted data is inputed to right side n level impact damper; Said right side n level impact damper is according to right side n level buffered clock signal; And the oppisite phase data of said right side n level shifted data and said right side n level shifted data, export 2n level drive signal;

N+1 level shift register is imported the oppisite phase data of left side n level shifted data and said left side n level shifted data to the left; According to left side n+1 level shift clock signal; And the oppisite phase data of said left side n level shifted data and said left side n level shifted data, the oppisite phase data of output left side n+1 level shifted data and said left side n+1 level shifted data;

The oppisite phase data of said left side n+1 level shifted data and said left side n+1 level shifted data is inputed to left side n+1 level impact damper; Said left side n+1 level impact damper is according to left side n+1 level buffered clock signal; And the oppisite phase data of said left side n+1 level shifted data and said left side n+1 level shifted data, export 2n+1 level drive signal;

N+1 level shift register is imported the oppisite phase data of right side n level shifted data and said right side n level shifted data to the right; According to right side n+1 level shift clock signal; And the oppisite phase data of said right side n level shifted data and said right side n level shifted data, the oppisite phase data of output right side n+1 level shifted data and said right side n+1 level shifted data;

The oppisite phase data of said right side n+1 level shifted data and said right side n+1 level shifted data is inputed to right side n+1 level impact damper; Said right side n+1 level impact damper is according to right side n+1 level buffered clock signal; And the oppisite phase data of said right side n+1 level shifted data and said right side n+1 level shifted data; Export 2n+2 level drive signal, wherein, n is a natural number.

Preferably; Equate when the high level lasting time and the said left side n level shift clock signal period of said left side n level shifted data; Said left side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n-1 level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said left side n level shift clock signal period.

Preferably; Equate when the high level lasting time and the said right side n level shift clock signal period of said right side n level shifted data; Said right side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said right side n level shift clock signal period.

Preferably; When the high level lasting time of said left side n level shifted data 2 times of said left side n level shift clock signal period; Said left side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n-1 level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said left side n level shift clock signal period.

Preferably; When the high level lasting time of said right side n level shifted data 2 times of said right side n level shift clock signal period; Said right side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said right side n level shift clock signal period.

The oppisite phase data of said n level shifted data and said n level shifted data is inputed to 2n-1 level impact damper; Said 2n-1 level impact damper is according to 2n-1 level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export 2n-1 level drive signal;

The oppisite phase data of said n level shifted data and said n level shifted data is inputed to 2n level impact damper; Said 2n level impact damper is according to 2n level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export 2n level drive signal;

Import the oppisite phase data of n level shifted data and said n level shifted data to n+1 level shift register; According to n+1 level shift clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export the oppisite phase data of n+1 level shifted data and said n+1 level shifted data;

The oppisite phase data of said n+1 level shifted data and said n+1 level shifted data is inputed to 2n+1 level impact damper; Said 2n+1 level impact damper is according to 2n+1 level buffered clock signal; And the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data, export 2n+1 level drive signal;

The oppisite phase data of said n+1 level shifted data and said n+1 level shifted data is inputed to 2n+2 level impact damper; Said 2n+2 level impact damper is according to 2n+2 level buffered clock signal; And the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data; Export 2n+2 level drive signal, wherein, n is a natural number.

Preferably; Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; Said n level shift clock signal high level lasting time is four of its cycle/for the moment; The said n level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said n level shift clock signal period.

Preferably; When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; Said n level shift clock signal high level lasting time is four of its cycle/for the moment; The said n level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said n level shift clock signal period.

Accordingly; The present invention also provides a kind of LCD that comprises above-mentioned drive unit; Also comprise display panels and data driven unit, said display panels comprises the pel array with at least 4 pixel cells, and each pixel cell comprises a thin film transistor (TFT); Each source electrode that is listed as said thin film transistor (TFT) is connected to same data line; Said data line links to each other with data driven unit, and the grid of each row thin film transistor (TFT) is connected to same gate line, and said gate line links to each other with drive unit.

Preferably, said drive unit comprises two said shift units, and with two buffer cells that are connected with shift unit respectively, said two buffer cells connect the two ends of said gate line respectively.

Preferably; Said drive unit comprises two said shift units; Two buffer cells that are connected with shift unit respectively, one of them said buffer cell connects the even number line gate line from an end of gate line, and another buffer cell connects the odd-numbered line gate line from the other end of gate line.

In the technique scheme; Drive unit comprises shift unit; Said shift unit comprises the shift register of two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data; Buffer cell, said buffer cell comprise two-stage impact damper at least, and said impact damper links to each other with said shift register, output drive signal, and wherein, n is a natural number.Therefore compare with prior art; The present invention has realized the generation drive signal through the shift register of series connection with the buffer cell that links to each other with the shift register output terminal; Shifted data is unidirectional delivery between the shift register of shift unit; Therefore the impact damper generation problem of certain one-level can not influence the shift register that is connected, and the input of the impact damper of each grade is by the shift register that is connected signal to be provided, and is wrong so have only the output result of the impact damper of generation problem; Other result at different levels can not be affected, and makes that like this drive unit accuracy is higher.

Description of drawings

Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.

Fig. 1 is the structural representation of a kind of LCD of the prior art;

Fig. 2 is the structural representation of a kind of gate drivers of the prior art;

Fig. 3 is the schematic equivalent circuit of first embodiment of LCD of the present invention;

Fig. 4 is the structural representation of gate drive apparatus in the LCD shown in Figure 3;

Fig. 5 is the circuit diagram of the gate drive apparatus among Fig. 4;

Fig. 6 is the monopulse working timing figure of gate drive apparatus shown in Figure 5;

Fig. 7 is the dipulse working timing figure of gate drive apparatus shown in Figure 5;

Fig. 8 is the schematic equivalent circuit of second embodiment of LCD of the present invention;

Fig. 9 is the monopulse working timing figure of gate drive apparatus in the LCD shown in Figure 8;

Figure 10 is the dipulse working timing figure of gate drive apparatus in the LCD shown in Figure 8;

Figure 11 is the schematic equivalent circuit of the 3rd embodiment of LCD of the present invention;

Figure 12 is the structural representation of the gate drive apparatus among the 4th embodiment of LCD of the present invention;

Figure 13 is the monopulse working timing figure of gate drive apparatus shown in Figure 12;

Figure 14 is the dipulse working timing figure of gate drive apparatus shown in Figure 12;

Figure 15 is the schematic equivalent circuit of the 5th embodiment of LCD of the present invention;

Figure 16 is the schematic equivalent circuit of the embodiment of shift register of the present invention;

Figure 17 is the schematic equivalent circuit of the embodiment of shift unit of the present invention;

Figure 18 and Figure 19 are input signal and its corresponding output signal schematic representation of each input end of shifting deposit unit for Figure 17;

Figure 20 is the schematic equivalent circuit of the embodiment of impact damper of the present invention;

Figure 21 is the process flow diagram of driving method one embodiment of the present invention.

Embodiment

For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.

Invention provides a kind of drive unit; Comprise: shift unit; Said shift unit comprises the shift register of two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data; Buffer cell, said buffer cell comprise two-stage impact damper at least, and said impact damper links to each other with said shift register, output drive signal, and wherein, n is a natural number.

Accordingly, the present invention also provides a kind of impact damper, comprising: pull-up unit, be connected with the output terminal of buffered clock signal and said impact damper, and make said impact damper output high level according to the buffered clock signal; Drop-down unit, said drop-down unit comprises the first drop-down unit, the second drop-down unit, and control the switch element that the first drop-down unit opens and closes, make said impact damper output low level according to the buffered clock signal.

Accordingly; The present invention also provides a kind of driving method of above-mentioned drive unit; Comprise step: oppisite phase data from said n-1 level shifted data to n level shift register that import n-1 level shifted data and; According to n level shift clock signal, and the oppisite phase data of said n-1 level shifted data and said n-1 level shifted data, export the oppisite phase data of n level shifted data and said n level shifted data; The oppisite phase data of said n level shifted data and said n level shifted data is inputed to n level impact damper; Said n level impact damper is according to n level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data; Export n level drive signal, wherein, n is a natural number.

Accordingly; The present invention also provides a kind of driving method of above-mentioned drive unit; Comprise step: n level shift register is imported the oppisite phase data of left side n-1 level shifted data and said left side n-1 level shifted data to the left; According to left side n level shift clock signal, and the oppisite phase data of said left side n-1 level shifted data and said left side n-1 level shifted data, the oppisite phase data of output left side n level shifted data and said left side n level shifted data;

For the ease of explanation, combine drive unit of the present invention application as gate drive apparatus in LCD to describe among the following embodiment, wherein drive signal is a gate drive signal.

Embodiment one

Fig. 3 is the schematic equivalent circuit of first embodiment of LCD of the present invention.Fig. 4 is the structural representation of gate drive apparatus among first embodiment of LCD of the present invention; Fig. 5 is the circuit diagram of the gate drive apparatus among Fig. 4.Below in conjunction with Fig. 3-Fig. 5 first embodiment of LCD of the present invention and the embodiment of gate drive apparatus are elaborated.

As shown in Figure 3, LCD comprises display panels 100, gate drive apparatus 200, is used for the data driven unit 300 of driving liquid crystal panel 100.Concrete; Display panels 100 comprises two substrates and the liquid crystal layer between said two substrates (for for simplicity the physical arrangement of the display panels that has nothing to do with the present invention not being explained in detail) of relative placement, and wherein display panels 100 is divided into the capable xj row of the i pixel cell 101 by array distribution.Has a TFT102 in each pixel cell 101.The grid of each row TFT102 is connected on the same gate line 103, and the source electrode of each row TFT102 is connected on the same data lines 104.The drain electrode of each TFT102 is connected on the pixel electrode of this pixel, forms liquid crystal capacitance between the public electrode of said pixel electrode and upper substrate.Wherein i and j are natural number.

Gate drive apparatus 200 is connected in the gate line 103 of display panels 100.Data driven unit 300 is connected in the data line 104 of display panels 100.When gate drive apparatus 200 when gate line 103 applies gate drive signal, data driver 300 is to data line 104 outputting data signals.In concrete a realization, LCD adopts the mode of operation of one-sided input gate drive signal.Therefore gate drive apparatus 200 is arranged on the one-sided of display panels 100, and all gate lines 103 are connected with gate drive apparatus 200 from the same side of display panels 100.

As shown in Figure 4, the gate drive apparatus 200 of LCD of the present invention comprises: shift unit 310 and buffering unit 320.Concrete; Said shift unit 310 comprises the shift register 315 of two-stage series connection at least; The said shift register 315 of n level is according to n level shift clock signal CLK_Q (n); The antiphase data QB (n-1) of n-1 level shifted data Q (n-1) and n-1 level shifted data is shifted, exports the antiphase data QB (n) of n level shifted data Q (n) and n level shifted data, for example the shifted data of first order shift register input is Q (0).Said buffer cell 320 comprises two-stage impact damper 325 at least; Said impact damper 325 is according to n level buffered clock signal CLK_G (n) and said n level shifted data Q (n), with and antiphase data QB (n), obtain gate drive signal Gate (n); Wherein, n is a natural number.

Compare with prior art; The present invention has realized the generation gate drive signal through the shift register 315 of series connection with the impact damper 325 that links to each other with shift register 315 output terminals; Shifted data is unidirectional delivery between the shift register 315 of shift unit 310; Just the shift register of this level need not rely on the data of next stage impact damper 325 outputs; Even just the impact damper 325 of this level is made mistakes and also can not had influence on the result of the shift register 315 that links to each other with the impact damper 325 of other grade, thereby make that the export structure accuracy of gate drive apparatus is higher.

In concrete a realization, shift register and impact damper have been adopted with the same number of progression of gate line of LCD.N level shift register 315 connects the said impact damper 325 of n level.Shift registers 315 at different levels are respectively with after the oppisite phase data QB (n-1) of shifted data Q (n-1), Q (n), Q (n+1) and corresponding shifted data, QB (n), QB (n+1) displacement; Output Q (n), Q (n+1), Q (n+2) and corresponding antiphase data QB (n), QB (n+1), QB (n+2) are then through said impact damper 325 output n level gate drive signal Gate (n), Gate (n+1), Gate (n+2).N level shift register 315 links to each other with n bar gate line through n impact damper respectively in proper order, to n bar gate line output gate drive signal.

Concrete, the shift register of the first order connects first order impact damper, and the gate line that the grid of the first order impact damper and the first row TFT is connected couples.The shift register of the first order is according to the 0th grade of shifted data Q (0) and its antiphase data QB (0), and the 1st grade of shift clock signal CLK_Q (1), first order shifted data Q (1) and its antiphase data QB (1) after first order impact damper output displacement.First order impact damper is according to first order shifted data Q (1) and its antiphase data QB (1), and the 1st grade of buffered clock signal CLK_G (1), obtains first order gate drive signal Gate (1).First order impact damper is to first gate line output gate drive signal Gate (1).

By that analogy, the gate line that is connected of the grid of n level impact damper and the capable TFT of n couples.The shift register of n level is according to n-1 level shifted data Q (n-1) and its antiphase data QB (n-1), and n level shift clock signal CLK_Q (n), n level shifted data Q (n) and its antiphase data QB (n) after n level impact damper output displacement.N level impact damper is according to n level shifted data Q (n) and its antiphase data QB (n), and n level buffered clock signal CLK_G (n), obtains n level gate drive signal Gate (n).N level impact damper is to n root gate line output gate drive signal Gate (n).

By that analogy, the gate line that is connected of the grid of n+1 level impact damper and the capable TFT of n+1 couples.The shift register of n+1 level is according to n level shifted data Q (n) and its antiphase data QB (n); And n+1 level shift clock signal CLK_Q (n+1), n+1 level shifted data Q (n+1) and its antiphase data QB (n+1) after n+1 level impact damper output displacement.N+1 level impact damper is according to n+1 level shifted data Q (n+1) and its antiphase data QB (n+1), and n+1 level buffered clock signal CLK_G (n+1), obtains n+1 level gate drive signal Gate (n+1).N+1 level impact damper is to n+1 root gate line output gate drive signal Gate (n+1).

Wherein, n level shift clock signal CLK_Q (n) is the first clock signal C K or second clock signal CKB (with the CK anti-phase).In the present embodiment, the shift clock signal of the shift register of odd level input is the first clock signal C K, and the shift clock signal of the shift register input of even level is second clock signal CKB.

Concrete; Said shift register; Be used for the antiphase data of shifted data and shifted data are shifted respectively, comprise: switch element, with the antiphase data of said shifted data and shifted data; And the connection of shift clock signal, be used to control the open and close of said shift register; The high level output unit is connected with said switch element with high level, and the signal of exporting according to switch element makes said shift register output high level; The low level output unit is connected with said switch element with low level, and the signal of exporting according to switch element makes said shift register output low level.

Wherein, the structure of said switch element is a symmetrical structure, and said symmetrical structure is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

Wherein, The structure of said high level output unit is a symmetrical structure; Said symmetrical structure is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level; The output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

Wherein, The structure of said low level output unit is a symmetrical structure; Said symmetrical structure is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level; The output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

Wherein, Said first switch element is a first transistor; Said second switch unit is a transistor seconds, and the said first high level output unit is the 3rd transistor, and the said second high level output unit is the 4th transistor; The said first low level output unit is the 5th transistor, and the said second low level output unit is the 6th transistor.

Concrete, as shown in Figure 5, any one-level shift register 315 in the said shift unit in 310 comprises plurality of transistors, 6 transistors for example, and wherein, the source electrode of the first transistor T1 is a first input end, imports n-1 level shifted data Q (n-1); The grid of the first transistor T1 is second input end, imports n level shift clock signal CLK_Q; The grid of the drain electrode of the first transistor T1 and the 3rd transistor T 3 couples.The source electrode of transistor seconds T2 is the 3rd input end, imports the antiphase data QB (n-1) of n-1 level shifted data; The grid of transistor seconds T2 is a four-input terminal, imports n level shift clock signal CLK_Q; The grid of the drain electrode of transistor seconds T2 and the 4th transistor T 4 couples.The source electrode of the 3rd transistor T 3 and the 4th transistor T 4 couples high level VGH, and the drain electrode of the 3rd transistor T 3 couples first output terminal, and the drain electrode of the 4th transistor T 4 couples second output terminal; The grid of the 5th transistor T 5 couples the drain electrode of transistor seconds T2, and the drain electrode of the 5th transistor T 5 couples the drain electrode of the 3rd transistor T 3, and the source electrode of the 5th transistor T 5 couples low level VGL; The grid of the 6th transistor T 6 couples the drain electrode of the first transistor T1, and the drain electrode of the 6th transistor T 6 couples the drain electrode of the 4th transistor T 4, and the source electrode of the 6th transistor T 6 couples low level VGL.

The circuit of above-mentioned shift register is simple in structure than shift-register circuit of the prior art, has reduced the area of circuit, thereby has reduced cost.

And present LCD is mainly used in portable product; Because product is stressed the light, thin of display more; The integration capability of device, better reliability, and low cost, therefore the size to LCD has also proposed requirements at the higher level; In order to make LCD have littler size, transistorized number is very important in the minimizing LCD driving circuit.And the circuit of the shift register among the present invention is simple, and number of transistors is few, thereby has practiced thrift substrate area, has realized reducing the requirement of LCD size.

Concrete, described impact damper comprises: pull-up unit, be connected with the output terminal of buffered clock signal and said impact damper, and make said impact damper output high level according to the buffered clock signal; Drop-down unit, said drop-down unit comprises the first drop-down unit, the second drop-down unit, and control the switch element that the first drop-down unit opens and closes, make said impact damper output low level according to the buffered clock signal.

Wherein, said pull-up unit is for pulling up transistor, and the said first drop-down unit is first pull-down transistor, and the said second drop-down unit is second pull-down transistor, and the switch element that the said control first drop-down unit opens and closes is a switching transistor.

Continuation is with reference to figure 5, and is concrete, and the n level impact damper 325 in the described buffer cell 320 comprises plurality of transistors, for example 4 transistors: the Td1 that pulls up transistor, switching transistor Td2, the first pull-down transistor Td3 and the second pull-down transistor Td4.Concrete connected mode is: the source electrode of the source electrode of the Td1 that pulls up transistor and switching transistor Td2 couples; Import the second buffered clock signal as the input end of impact damper; Concrete; The second buffered clock signal equals second clock signal CKB, and the grid of the Td1 that pulls up transistor is imported n level shifted data Q (n), and the drain electrode of the Td1 that pulls up transistor couples gate drive signal output terminal Gate (n); The grid of switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data, and the drain electrode of switching transistor couples the grid of the first pull-down transistor Td3; The drain electrode of the first pull-down transistor Td3 and the second pull-down transistor Td4 also couples gate drive signal output terminal Gate (n), and the source electrode of the first pull-down transistor Td3 is imported the first buffered clock signal.

The first concrete buffered clock signal equals the first clock signal C K; The grid of the second pull-down transistor Td4 is also imported the first buffered clock signal; The just said first clock signal C K, the source electrode of the second pull-down transistor Td4 is imported the second buffered clock signal, just second clock signal CKB.

Certainly; In other embodiments; During concrete the selection; As long as the input signal of the input end of assurance impact damper is opposite with the input end input signal phase place of the second pull-down transistor Td4 grid, and the source electrode input signal phase place of the source electrode input signal of the second pull-down transistor Td4 and the first pull-down transistor Td3 is opposite, and the input signal phase place of the input end of the gate input of the first transistor T1 of shift register and the gate input of transistor seconds T2 and corresponding buffers gets final product on the contrary.

The circuit of above-mentioned impact damper 325 is compared with existing buffer circuit configuration simple, and constitutes drop-down module by switching transistor Td2, the first pull-down transistor Td3 and the second pull-down transistor Td4, reduces transistorized threshold drift, has prolonged the life-span of circuit.

Fig. 6 is the monopulse working timing figure of gate drive apparatus shown in Figure 5.As shown in Figure 6; For n level shift register, first input end is imported n-1 level shifted data Q (n-1), and second input end is imported the first clock signal C K; The 3rd input end is imported the inversion signal QB (n-1) of n-1 level shifted data, and four-input terminal is also imported the first clock signal C K.First output terminal is exported n level shifted data Q (n), second output terminal output antiphase data QB (n).

For n level impact damper; Its input end input second clock signal CKB; The grid that pulls up transistor is imported n level shifted data Q (n), and the grid of switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data, and the source electrode of the first pull-down transistor Td3 is imported the first clock signal C K; The grid of the second pull-down transistor Td4 is also imported the said first clock signal C K, the source electrode input second clock signal CKB of second pull-down transistor; Then n level impact damper is exported n level gate drive signal Gate (n).

By that analogy; For n+1 level shift register, first input end is imported n level shifted data Q (n), second input end input second clock signal CKB; The 3rd input end is imported the inversion signal QB (n) of n level shifted data, and four-input terminal is also imported second clock signal CKB.First output terminal is exported n level shifted data Q (n+1), second output terminal output antiphase data QB (n+1).

For n+1 level impact damper; Its input end is imported the first clock signal C K; The grid that pulls up transistor is imported n+1 level shifted data Q (n+1), and the grid of switching transistor Td2 is imported the antiphase data QB (n+1) of n+1 level shifted data, the source electrode input second clock signal CKB of the first pull-down transistor Td3; The grid of the second pull-down transistor Td4 is also imported said second clock signal CKB, and the source electrode of second pull-down transistor is imported the first clock signal C K; Then n+1 level impact damper is exported n+1 level gate drive signal Gate (n+1).

Fig. 7 is the dipulse working timing figure of gate drive apparatus shown in Figure 5.

As shown in Figure 7; For n level shift register, first input end is imported n-1 level shifted data Q (n-1), and second input end is imported the first clock signal C K; The 3rd input end is imported the inversion signal QB (n-1) of n-1 level shifted data, and four-input terminal is also imported the first clock signal C K; For n level impact damper; Its input end input second clock signal CKB; The grid that pulls up transistor is imported n level shifted data Q (n), and the grid of switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data, and the source electrode of the first pull-down transistor Td3 is imported the first clock signal C K; The grid of the second pull-down transistor Td4 is also imported the said first clock signal C K, the source electrode input second clock signal CKB of second pull-down transistor.

Can know by above description; In monopulse work schedule and dipulse work schedule; The input signal types of each input end of shift register and impact damper is identical; Difference is: in dipulse work schedule shown in Figure 7, the high level lasting time of the n-1 level shifted data Q (n-1) of first input end input is 2 times of the first clock signal C K cycle, and oppisite phase data QB (n-1) low duration of the n-1 level shifted data of the 3rd input end input also is 2 times of the first clock signal C K cycle; Thereby; The high level lasting time of the n level shifted data Q (n) of n level shift register output and the low duration of its antiphase data QB (n) also are 2 times of the first clock signal C K cycle accordingly, and correspondingly, the said n level gate drive signal gate (n) of n level impact damper output is the dipulse signal; In first pulse, the liquid crystal layer electric capacity precharge that couples to drain electrode through TFT102 with TFT102; Second pulse, further charge to the liquid crystal layer electric capacity that the drain electrode with TFT102 couples through TFT102.

By that analogy, in the dipulse work schedule, the principle of work and the sequential of n+1 level shift register and n+1 level impact damper detail at this no longer one by one.

Embodiment two

The structural representation of second embodiment of Fig. 8 LCD of the present invention.

In the present embodiment, display panels 100, data driven unit 200, and element composition and the position relation and embodiment one identical repeating no more of shift unit in the gate drive apparatus 300 and buffering unit.Be with the different of embodiment one: in the present embodiment, LCD adopts the mode of operation of bilateral input gate drive signal.Concrete, said gate drive apparatus comprises two said shift units and two said buffer cells, i.e. left side shift unit, right side shift unit, left side buffer cell and right side buffer cell.Said gate drive apparatus is given the gate line input signal respectively from different directions; In the present embodiment, the opposite side that gate drive apparatus divides two parts to be separately positioned on display panels 100, wherein; The left side shift unit links to each other with the left side buffer cell; Be arranged on the left side of display panels 100, link to each other with the grid of the TFT of said odd-numbered line pixel cell, the left side buffer cell is exported 2n-1 level gate drive signal.The right side shift unit links to each other with the right side buffer cell, is arranged on the right side of display panels 100, links to each other with the grid of the TFT of said even number line pixel cell, and the right side buffer cell is exported 2n level gate drive signal.

In the gate drivers, the original paper of each of the left and right sides grade shift register and impact damper is formed identical with Fig. 5 of connected mode such as embodiment one described in Fig. 8, and just the input signal of each original paper is different, is elaborated below in conjunction with Fig. 9 and Figure 10.

Fig. 9 is the monopulse working timing figure of gate drive apparatus in the LCD shown in Figure 8.

As shown in Figure 9; For left side n level shift register; First input end input left side n-1 level shifted data Q-L (n-1); The second input end input left side first clock signal C K-L, the inversion signal QB-L (n-1) of the 3rd input end input left side n-1 level shifted data, four-input terminal is also imported the left side first clock signal C K-L; For left side n level impact damper; Its input end input left side second clock signal CKB-L; The grid input left side n level shifted data Q-L (n) of Td1 pulls up transistor; The antiphase data QB-L (n) of the grid input left side n level shifted data of switching transistor Td2; The source electrode input left side first clock signal C K-L of the first pull-down transistor Td3, the grid of the second pull-down transistor Td4 is also imported the said left side first clock signal C K-L, the source electrode input left side second clock signal CKB-L of the second pull-down transistor Td4; Left side n level impact damper is exported 2n-1 level gate drive signal Gate (2n-1).

For right side n level shift register; First input end input right side n-1 level shifted data Q-R (n-1); The second input end input right side first clock signal C K-R; The inversion signal QB-R (n-1) of the 3rd input end input right side n-1 level shifted data, four-input terminal is also imported the right side first clock signal C K-R; For right side n level impact damper; Its input end input right side second clock signal CKB-R; The grid input right side n level shifted data Q-R (n) that pulls up transistor; The antiphase data QB-R (n) of the grid input right side n level shifted data of switching transistor Td2; The source electrode input right side first clock signal C K-R of the first pull-down transistor Td3, the grid of the second pull-down transistor Td4 is also imported the said right side first clock signal C K-R, the source electrode input right side second clock signal CKB-R of second pull-down transistor; Right side n level impact damper is exported 2n level gate drive signal Gate (2n).

By that analogy; For left side n+1 level shift register; First input end input left side n level shifted data Q-L (n); Second input end input left side second clock signal CKB-L, the inversion signal QB-L (n) of the 3rd input end input left side n level shifted data, four-input terminal is also imported left side second clock signal CKB-L; For left side n+1 level impact damper; Its input end input left side first clock signal C K-L; The grid input left side n+1 level shifted data Q-L (n+1) that pulls up transistor; The antiphase data QB-L (n+1) of the grid input left side n+1 level shifted data of switching transistor Td2; The source electrode input left side second clock signal CKB-L of the first pull-down transistor Td3, the grid of the second pull-down transistor Td4 is also imported said left side second clock signal CKB-L, the source electrode input left side first clock signal C K-L of second pull-down transistor; Left side n+1 level impact damper is exported 2n+1 level gate drive signal Gate (2n+1).

For right side n+1 level shift register; First input end input right side n level shifted data Q-R (n); Second input end input right side second clock signal CKB-R; The inversion signal QB-R (n) of the 3rd input end input right side n level shifted data, four-input terminal is also imported right side second clock signal CKB-R; For right side n+1 level impact damper; Its input end input right side first clock signal C K-R; The grid input right side n+1 level shifted data Q-R (n+1) that pulls up transistor; The antiphase data QB-R (n+1) of the grid input right side n+1 level shifted data of switching transistor Td2; The source electrode input right side second clock signal CKB-R of the first pull-down transistor Td3, the grid of the second pull-down transistor Td4 is also imported said right side second clock signal CKB-R, the source electrode input right side first clock signal C K-R of second pull-down transistor; Right side n+1 level impact damper is exported 2n+2 level gate drive signal Gate (2n+2).

For the shift register of each grade and the impact damper of its respective stages; When specifically selecting input signal; As long as the input signal of assurance impact damper input end is opposite with the input signal phase place of the second pull-down transistor grid, and the input signal phase place of the input end of the clock signal of shift register input and corresponding buffers gets final product on the contrary.Phase place that it should be noted that signal alleged among the present invention is opposite, and some situation is not opposite completely, and just phase place is in the opposite direction, and concrete condition is confirmed with actual waveform as required.

Figure 10 is the dipulse working timing figure of gate drive apparatus in the LCD shown in Figure 8.

The situation of the difference of present embodiment monopulse sequential and dipulse sequential and embodiment one is similar, those skilled in the art will readily appreciate that, so be not described in detail in this.

Embodiment three

Figure 11 is the structural representation of the 3rd embodiment of LCD of the present invention.

In the present embodiment, display panels 100, data driven unit 200, and element composition and the position relation and embodiment one identical repeating no more of shift unit in the gate drive apparatus 300 and buffering unit.Be with the different of embodiment one: in the present embodiment, said gate drive apparatus 200 comprises two said shift units and two said buffer cells, i.e. left side shift unit, right side shift unit, left side buffer cell and right side buffer cell.Wherein the left side shift unit links to each other with the left side buffer cell, and the left side buffer cell is exported n level gate drive signal; The right side shift unit links to each other with the right side buffer cell, and the right side buffer cell is exported n level gate drive signal.The element composition and the signal input of said left side shift unit and right side shift unit are identical, and the original paper of left side buffer cell and right side buffer cell is formed and signal is imported identical.

In the present embodiment, have identical signal to input to this gate line from the not homonymy of every gate line, the thin film transistor (TFT) that is connected to same gate line both sides like this can be opened simultaneously.Especially for large-sized panel; Because panel is bigger; Gate line is very long; Just have delay if gate drive apparatus, then connects the signal that the thin film transistor (TFT) of opposite side of the gate line of gate drive apparatus receives at the one-sided input signal of gate line, so present embodiment can well solve delay issue.

In the concrete realization of present embodiment, connected mode shown in figure 11, the right side shift unit links to each other with the right side buffer cell, is arranged on the right side of display panels 100; The left side shift unit links to each other with the left side buffer cell, is arranged on the left side of display panels 100.From the identical gate drive signal of left and right sides two side direction pel arrays input, therefore dwindled delay, improved degree of accuracy.

Embodiment four

Figure 12 is the structural representation of the gate drive apparatus among the 4th embodiment of LCD of the present invention.

In the present embodiment, display panels, data driven unit, and element composition and the position relation of shift register in the gate drive apparatus and impact damper is identical with embodiment one, therefore repeats no more.Be with the different of embodiment one: each grade shift register connects two-stage impact damper at least, and the said impact damper of two-stage at least output two-stage gate drive signal.

Concrete, n (in the present embodiment, n is a natural number) level shift register connects 2n-1 level and 2n level impact damper, and said 2n-1 level impact damper is exported 2n-1 level gate drive signal, and said 2n level impact damper is exported 2n level gate drive signal; N+1 level shift register connects the 2nd (n+1)-1 grade and the 2nd (n+1) level impact damper, and said the 2nd (n+1)-1 a grade impact damper is exported the 2nd (n+1)-1 grade gate drive signal, and said the 2nd (n+1) level impact damper is exported the 2nd (n+1) level gate drive signal.For example the 1st grade of shift register connects the 1st grade and the 2nd grade of impact damper, and said the 1st grade of impact damper exported the 1st grade of gate drive signal, and said the 2nd grade of impact damper exported the 2nd grade of gate drive signal; The 2nd grade of shift register connects 3rd level and the 4th grade of impact damper, said 3rd level impact damper output 3rd level gate drive signal, and said the 4th grade of impact damper exported the 4th grade of gate drive signal.

A kind of embodiment of present embodiment; Shown in figure 12; For n level shift register, first input end is imported n-1 level shifted data Q (n-1), and second input end is imported n level shift clock signal; The 3rd input end is imported the inversion signal QB (n-1) of n-1 level shifted data, and four-input terminal is also imported n level shift clock signal.Wherein, n level shift clock signal is the left side first clock signal C K-L.

2n-1 level impact damper is connected with n level shift register; The source electrode of the Td1 that pulls up transistor of said 2n-1 level impact damper and the source electrode of switching transistor Td2 couple; Input end as 2n-1 level impact damper; The said input end input right side first buffered clock signal; The grid of the said Td1 of pulling up transistor is imported n level shifted data Q (n); The drain electrode of the said Td1 of pulling up transistor couples the output terminal of said 2n-1 level impact damper, and the grid of said switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data, and the drain electrode of said switching transistor Td2 couples the grid of the first pull-down transistor Td3; The source electrode input right side second buffered clock signal of the said first pull-down transistor Td3; The drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said 2n-1 level impact damper, and the grid of the said second pull-down transistor Td4 is also imported the said right side second buffered clock signal, and the drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said 2n-1 level impact damper; The source electrode input right side first buffered clock signal of said second pull-down transistor, the output terminal of said 2n-1 level impact damper is exported 2n-1 level gate drive signal Gate (2n-1).Wherein, the right side first buffered clock signal is the right side first clock signal C K-R; The right side second buffered clock signal is right side second clock signal CKB-R.

2n level impact damper is connected with n level shift register; The source electrode of the Td1 that pulls up transistor of said 2n level impact damper and the source electrode of switching transistor Td2 couple; Input end as 2n level impact damper; The said input end input left side second buffered clock signal; The grid of the said Td1 of pulling up transistor is imported n level shifted data Q (n), and the drain electrode of the said Td1 of pulling up transistor couples the output terminal of said 2n level impact damper, and the grid of said switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data; The drain electrode of said switching transistor Td2 couples the grid of the first pull-down transistor Td3; The source electrode input left side first buffered clock signal of the said first pull-down transistor Td3, the grid of the second pull-down transistor Td4 is also imported the said left side first buffered clock signal, and the drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said 2n level impact damper; The source electrode input left side second buffered clock signal of said second pull-down transistor, the output terminal of said 2n level impact damper is exported 2n level gate drive signal Gate (2n).Wherein, the left side first buffered clock signal is the left side first clock signal C K-L; The left side second buffered clock signal is left side second clock signal CKB-L.

For n+1 level shift register; First input end is imported n level shifted data Q (n); Second input end is imported n+1 level shift clock signal, and the 3rd input end is imported the inversion signal QB (n) of n level shifted data, and four-input terminal is also imported n+1 level shift clock signal.Wherein, n+1 level shift clock signal is left side second clock signal CKB-L.

The 2nd (n+1)-1 grade impact damper is connected with n+1 level shift register; The source electrode of the Td1 that pulls up transistor of said the 2nd (n+1)-1 grade impact damper and the source electrode of switching transistor Td2 couple; Input end as the 2nd (n+1)-1 grade impact damper; The said input end input right side second buffered clock signal; The grid of the said Td1 of pulling up transistor is imported n+1 level shifted data Q (n+1); The drain electrode of the said Td1 of pulling up transistor couples the output terminal of said 2 (n+1)-1 grade impact dampers; The grid of said switching transistor Td2 is imported the antiphase data QB (n+1) of n+1 level shifted data, and the drain electrode of said switching transistor Td2 couples the grid of the first pull-down transistor Td3, the source electrode input right side first buffered clock signal of the said first pull-down transistor Td3; The grid of the second pull-down transistor Td4 is also imported the said right side second buffered clock signal; The drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said the 2nd (n+1)-1 grade impact damper, the source electrode input right side second buffered clock signal of said second pull-down transistor, and the output terminal of said the 2nd (n+1)-1 grade impact damper is exported the 2nd (n+1)-1 grade gate drive signal Gate (2 (n+1)-1).Wherein, the right side first buffered clock signal is the right side first clock signal C K-R; The right side second buffered clock signal is right side second clock signal CKB-R.

The 2nd (n+1) level impact damper is connected with n+1 level shift register; The source electrode of the Td1 that pulls up transistor of said the 2nd (n+1) level impact damper and the source electrode of switching transistor Td2 couple; Input end as the 2nd (n+1) level impact damper; The said input end input left side first buffered clock signal; The grid of the said Td1 of pulling up transistor is imported n+1 level shifted data Q (n+1); The drain electrode of the said Td1 of pulling up transistor couples the output terminal of said the 2nd (n+1) level impact damper, and the grid of said switching transistor Td2 is imported the antiphase data QB (n+1) of n+1 level shifted data, and the drain electrode of said switching transistor Td2 couples the grid of the first pull-down transistor Td3; The source electrode input left side second buffered clock signal of the said first pull-down transistor Td3; The drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said the 2nd (n+1) level impact damper, and the grid of the said second pull-down transistor Td4 is also imported the said left side second buffered clock signal, and the drain electrode of the drain electrode of the said first pull-down transistor Td3 and the second pull-down transistor Td4 couples the output terminal of said the 2nd (n+1) level impact damper; The source electrode input left side first buffered clock signal of said second pull-down transistor, the output terminal of said the 2nd (n+1) level impact damper is exported the 2nd (n+1) level gate drive signal Gate (2 (n+1)).Wherein, the left side first buffered clock signal is the left side first clock signal C K-L; The left side second buffered clock signal is left side second clock signal CKB-L.

In practical implementation; As long as guarantee the signal that the source electrode of the first pull-down transistor Td3 of each grade impact damper is imported; Different with this grade impact damper input end input signal, that is, select one of other three kinds of clock signals except that the clock signal of this grade impact damper input end input.And those skilled in the art can also know by inference; Each grade shift register can be selected right side first clock signal C K-R or right side second clock signal CKB-R, as long as the first input end of shift register and the signal of the 3rd input end are changed.

Figure 13 is the monopulse working timing figure of gate drive apparatus shown in Figure 12.

Give each input end input corresponding waveform signal shown in figure 13 of gate drive apparatus shown in Figure 12, just can obtain gate drive signals at different levels shown in figure 13.Owing to similar description is arranged, in embodiment one so be not described in detail in this.Figure 14 is the dipulse working timing figure of gate drive apparatus shown in Figure 12.

Give each input end input corresponding waveform signal shown in figure 14 of gate drive apparatus shown in Figure 12, just can obtain gate drive signals at different levels shown in figure 14.Owing to similar description is arranged, in embodiment one so be not described in detail in this.

Certainly, in other embodiments, drive unit also can be used in other the equipment, as other drive unit except that gate drive apparatus, for example is used in the display of CRT as drive unit.

Embodiment five

Figure 15 is the structural representation of the 5th embodiment of LCD of the present invention.

In the present embodiment, display panels 100, data driven unit 200, and element composition and the position relation and embodiment one identical repeating no more of shift unit in the gate drive apparatus 300 and buffering unit.Be with the different of embodiment one: in the present embodiment, said gate drive apparatus 200 comprises two said shift units and two said buffer cells; Wherein first shift unit links to each other with first buffer cell; Second shift unit links to each other with second buffer cell; And the element of said first shift unit and second shift unit is formed and the signal input is identical, and the original paper of first buffer cell and second buffer cell is formed and signal is imported identical.

In the concrete realization of present embodiment, connected mode shown in figure 11 from the identical gate drive signal of left and right sides two side direction pel arrays input, has therefore been dwindled delay, has improved degree of accuracy.

In addition, in other embodiment, the shift register in the gate drive apparatus of said LCD can be other structures, but impact damper can be the structure in the foregoing description.

Embodiment six

The present invention also provides a kind of shift register in addition; Be used for the antiphase data of shifted data and shifted data are shifted respectively; Comprise: switch element; With the antiphase data of said shifted data and shifted data, and the connection of shift clock signal, be used to control the open and close of said shift register; The high level output unit is connected with said switch element with high level, and the signal of exporting according to switch element makes said shift register output high level; The low level output unit is connected with said switch element with low level, and the signal of exporting according to switch element makes said shift register output low level.

Concrete, said shift register comprises plurality of transistors, for example 6, shown in figure 16, wherein, the source electrode of the first transistor T1 is a first input end, input shifted data Q (n-1); The grid of the first transistor T1 is second input end, input shift clock signal; The grid of the drain electrode of the first transistor T1 and the 3rd transistor T 3 couples.The source electrode of transistor seconds T2 is the 3rd input end, the antiphase data QB (n-1) of input shifted data; The grid of transistor seconds T2 is a four-input terminal, input shift clock signal CK; The grid of the drain electrode of transistor seconds T2 and the 4th transistor T 4 couples.The source electrode of the 3rd transistor T 3 and the 4th transistor T 4 couples high level VGH, and the drain electrode of the 3rd transistor T 3 connects first output terminal, and the drain electrode of the 4th transistor T 4 connects second output terminal; The grid of the 5th transistor T 5 couples the drain electrode of transistor seconds T2, and the drain electrode of the 5th transistor T 5 couples the drain electrode of the 3rd transistor T 3, and the source electrode of the 5th transistor T 5 couples low level VGL; The grid of the 6th transistor T 6 couples the drain electrode of the first transistor T1, and the drain electrode of the 6th transistor T 6 couples the drain electrode of the 4th transistor T 4, and the source electrode of the 6th transistor T 6 couples low level VGL.Wherein, the shift clock signal is the first clock signal C K.

The present invention also provides a kind of shift unit, comprises the shift register of two-stage series connection at least, and n level and n+1 level shift register are shown in figure 17, and wherein CKB is the inversion clock signal of clock signal C K.

Figure 18 and Figure 19 are input signal and its corresponding output signal schematic representation of each input end of shifting deposit unit shown in Figure 17.

The present invention also provides a kind of impact damper, comprising: pull-up unit, be connected with the output terminal of buffered clock signal and said impact damper, and make said impact damper output high level according to the buffered clock signal; Drop-down unit, said drop-down unit comprises the first drop-down unit, the second drop-down unit, and control the switch element that the first drop-down unit opens and closes, make said impact damper output low level according to the buffered clock signal.

Concrete, shown in figure 20, said impact damper comprises plurality of transistors, for example 4: the Td1 that pulls up transistor, switching transistor Td2, the first pull-down transistor Td3 and the second pull-down transistor Td4.Concrete chain connected mode is: the source electrode of pull up transistor Td1 and switching transistor Td2 couples; Input end as impact damper; The signal of input is the second buffered clock signal; The grid input shifted data Q (n) that pulls up transistor, the drain electrode of the Td1 that pulls up transistor couples gate drive signal output terminal Gate (n); The grid of switching transistor Td2 is imported the antiphase data QB (n) of n level shifted data, and the drain electrode of switching transistor couples the grid of the first pull-down transistor Td3; The drain electrode of the first pull-down transistor Td3 and the second pull-down transistor Td4 also couples gate drive signal output terminal Gate (n); The source electrode of the first pull-down transistor Td3 is imported the first buffered clock signal; The grid of the second pull-down transistor Td4 is also imported the said first buffered clock signal, and the source electrode of second pull-down transistor is imported the second buffered clock signal.Wherein, the first buffered clock signal is the first clock signal C K, and the second buffered clock signal is second clock signal CKB.

To the shift signal among other embodiment of said impact damper input the present invention and the inversion signal of shift signal, and corresponding clock signals, can obtain the gate drive signal of corresponding situation.

Said first output terminal of shift register is the shifted data output terminal in the above-described embodiments, and second output terminal is the antiphase data output end of shifted data.

The invention also discloses a kind of grid drive method in addition, Figure 21 is the process flow diagram of driving method one embodiment of the present invention.Below in conjunction with Figure 21 this driving method is described.

The driving method of present embodiment comprises step:

A: oppisite phase data from said n-1 level shifted data to n level shift register that import n-1 level shifted data and; According to n level shift clock signal; And the oppisite phase data of said n-1 level shifted data and said n-1 level shifted data, export the oppisite phase data of n level shifted data and said n level shifted data;

B: the oppisite phase data of said n level shifted data and said n level shifted data is inputed to n level impact damper; Said n level impact damper is according to n level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export n level gate drive signal.

Wherein, Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; And said n level shift clock signal high level lasting time is a half in its cycle; The said n level gate drive signal of output is a single pulse signal, and its high level lasting time is the half the of said n level shift clock signal period.

Wherein, When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; And said n level shift clock signal high level lasting time is a half in its cycle; The said n level gate drive signal of output is the dipulse signal, and wherein each high level lasting time is the half the of said n level shift clock signal period.

The invention also discloses another kind of driving method, comprise the steps:

A: n level shift register is imported the oppisite phase data of left side n-1 level shifted data and said left side n-1 level shifted data to the left; According to left side n level shift clock signal; And the oppisite phase data of said left side n-1 level shifted data and said left side n-1 level shifted data, the oppisite phase data of output left side n level shifted data and said left side n level shifted data;

B: the oppisite phase data of said left side n level shifted data and said left side n level shifted data is inputed to left side n level impact damper; Said left side n level impact damper is according to left side n level buffered clock signal; And the oppisite phase data of said left side n level shifted data and said left side n level shifted data, export 2n-1 level gate drive signal;

C: n level shift register is imported the oppisite phase data of right side n-1 level shifted data and said right side n-1 level shifted data to the right; According to right side n level shift clock signal; And the oppisite phase data of said right side n-1 level shifted data and said right side n-1 level shifted data, the oppisite phase data of output right side n level shifted data and said right side n level shifted data;

D: the oppisite phase data of said right side n level shifted data and said right side n level shifted data is inputed to right side n level impact damper; Said right side n level impact damper is according to right side n level buffered clock signal; And the oppisite phase data of said right side n level shifted data and said right side n level shifted data, export 2n level gate drive signal;

E: n+1 level shift register is imported the oppisite phase data of left side n level shifted data and said left side n level shifted data to the left; According to left side n+1 level shift clock signal; And the oppisite phase data of said left side n level shifted data and said left side n level shifted data, the oppisite phase data of output left side n+1 level shifted data and said left side n+1 level shifted data;

F: the oppisite phase data of said left side n+1 level shifted data and said left side n+1 level shifted data is inputed to left side n+1 level impact damper; Said left side n+1 level impact damper is according to left side n+1 level buffered clock signal; And the oppisite phase data of said left side n+1 level shifted data and said left side n+1 level shifted data, export 2n+1 level gate drive signal;

G: n+1 level shift register is imported the oppisite phase data of right side n level shifted data and said right side n level shifted data to the right; According to right side n+1 level shift clock signal; And the oppisite phase data of said right side n level shifted data and said right side n level shifted data, the oppisite phase data of output right side n+1 level shifted data and said right side n+1 level shifted data;

H: the oppisite phase data of said right side n+1 level shifted data and said right side n+1 level shifted data is inputed to right side n+1 level impact damper; Said right side n+1 level impact damper is according to right side n+1 level buffered clock signal; And the oppisite phase data of said right side n+1 level shifted data and said right side n+1 level shifted data, export 2n+2 level gate drive signal;

Wherein, Equate when the high level lasting time and the said left side n level shift clock signal period of said left side n level shifted data; Said left side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n-1 level gate drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said left side n level shift clock signal period.

Wherein, Equate when the high level lasting time and the said right side n level shift clock signal period of said right side n level shifted data; Said right side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n level gate drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said right side n level shift clock signal period.

Wherein, When the high level lasting time of said left side n level shifted data 2 times of said left side n level shift clock signal period; Said left side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n-1 level gate drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said left side n level shift clock signal period.

Wherein, When the high level lasting time of said right side n level shifted data 2 times of said right side n level shift clock signal period; Said right side n level shift clock signal high level lasting time is four of its cycle/for the moment; The said 2n level gate drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said right side n level shift clock signal period.

B: the oppisite phase data of said n level shifted data and said n level shifted data is inputed to 2n-1 level impact damper; Said 2n-1 level impact damper is according to 2n-1 level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export 2n-1 level gate drive signal;

C: the oppisite phase data of said n level shifted data and said n level shifted data is inputed to 2n level impact damper; Said 2n level impact damper is according to 2n level buffered clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export 2n level gate drive signal;

D: oppisite phase data from said n level shifted data to n+1 level shift register that import n level shifted data and; According to n+1 level shift clock signal; And the oppisite phase data of said n level shifted data and said n level shifted data, export the oppisite phase data of n+1 level shifted data and said n+1 level shifted data;

E: the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data is inputed to 2n+1 level impact damper; Said 2n+1 level impact damper is according to 2n+1 level buffered clock signal; And the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data, export 2n+1 level gate drive signal;

F: the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data is inputed to 2n+2 level impact damper; Said 2n+2 level impact damper is according to 2n+2 level buffered clock signal; And the oppisite phase data of said n+1 level shifted data and said n+1 level shifted data, export 2n+2 level gate drive signal;

Wherein, Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; Said n level shift clock signal high level lasting time is four of its cycle/for the moment; The 2n-1 and the 2n level gate drive signal of output are single pulse signal, and its high level lasting time is 1/4th of the said n level shift clock signal period.

Wherein, When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; Said n level shift clock signal high level lasting time is four of its cycle/for the moment; The 2n-1 and the 2n level gate drive signal of output are the dipulse signal, and wherein each high level lasting time is 1/4th of the said n level shift clock signal period.

In the above-described embodiments, n is a natural number.

The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.

Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims

1. a drive unit is characterized in that, comprising:

Buffer cell, said buffer cell comprise two-stage impact damper at least, and said impact damper links to each other with said shift register; Output drive signal and n level shift register connect the said impact damper of n level; Said n level impact damper is exported n level drive signal, and wherein, n is a natural number.

2. drive unit according to claim 1 is characterized in that, said shift register is used for the antiphase data of shifted data and shifted data are shifted respectively, comprising:

3. drive unit according to claim 2 is characterized in that the structure of said switch element is a symmetrical structure, and said symmetrical structure is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

4. drive unit according to claim 3; It is characterized in that; The structure of said high level output unit is a symmetrical structure; Said symmetrical structure is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level, and the output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

5. drive unit according to claim 4; It is characterized in that; The structure of said low level output unit is a symmetrical structure; Said symmetrical structure is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level, and the output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

6. drive unit according to claim 5; It is characterized in that said first switch element is a first transistor, said second switch unit is a transistor seconds; The said first high level output unit is the 3rd transistor; The said second high level output unit is the 4th transistor, and the said first low level output unit is the 5th transistor, and the said second low level output unit is the 6th transistor.

7. drive unit according to claim 6 is characterized in that,

N level shift register in the said shift unit comprises plurality of transistors; Wherein, The source electrode of the first transistor is imported n-1 level shifted data, and the grid of the first transistor is imported n level shift clock signal, and the drain electrode of the first transistor and the 3rd transistorized grid couple; The source electrode of transistor seconds is imported the antiphase data of n-1 level shifted data, and the grid of transistor seconds is imported n level shift clock signal, and the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of n level shift register, and the 4th transistor drain couples second output terminal of n level shift register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, the 5th transistorized source electrode input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

8. drive unit according to claim 7 is characterized in that, described impact damper comprises:

9. drive unit according to claim 8; It is characterized in that; Said pull-up unit is for pulling up transistor; The said first drop-down unit is first pull-down transistor, and the said second drop-down unit is second pull-down transistor, and the switch element that the said control first drop-down unit opens and closes is a switching transistor.

10. drive unit according to claim 8 is characterized in that,

The n level impact damper of described buffer cell comprises plurality of transistors; Wherein, the source electrode that pulls up transistor and the source electrode of switching transistor couple, as the input end of n level impact damper; Said input end is imported the second buffered clock signal; The said grid that pulls up transistor is imported n level shifted data, and the said drain electrode that pulls up transistor couples the output terminal of said n level impact damper, and the grid of said switching transistor is imported the antiphase data of n level shifted data; The drain electrode of said switching transistor couples the first pull-down transistor grid; The source electrode of first pull-down transistor is imported the first buffered clock signal, and the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said n level impact damper, and the grid of said second pull-down transistor is imported the said first buffered clock signal; The source electrode of said second pull-down transistor is imported the second buffered clock signal, and the output terminal of said n level impact damper is exported n level drive signal.

11. drive unit according to claim 1 is characterized in that, n level shift register connects two-stage impact damper at least, and every grade of said impact damper output one-level drive signal.

12. drive unit according to claim 11; It is characterized in that; N level shift register connects 2n level and 2n-1 level impact damper, and said 2n-1 level impact damper is exported 2n-1 level drive signal, and said 2n level impact damper is exported 2n level drive signal.

13. drive unit according to claim 12 is characterized in that, said shift register is used for the antiphase data of shifted data and shifted data are shifted respectively, comprising:

14. drive unit according to claim 13 is characterized in that, the structure of said switch element is a symmetrical structure, and said symmetrical structure is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

15. drive unit according to claim 14; It is characterized in that; The structure of said high level output unit is a symmetrical structure; Said symmetrical structure is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level, and the output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

16. drive unit according to claim 15; It is characterized in that; The structure of said low level output unit is a symmetrical structure; Said symmetrical structure is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level, and the output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

17. drive unit according to claim 16; It is characterized in that said first switch element is a first transistor, said second switch unit is a transistor seconds; The said first high level output unit is the 3rd transistor; The said second high level output unit is the 4th transistor, and the said first low level output unit is the 5th transistor, and the said second low level output unit is the 6th transistor.

18. drive unit according to claim 17 is characterized in that,

N level shift register in the said shift unit comprises plurality of transistors, wherein,

The source electrode of the first transistor is imported n-1 level shifted data, and the grid of the first transistor is imported n level shift clock signal, and the drain electrode of the first transistor and the 3rd transistorized grid couple; The source electrode of transistor seconds is imported the antiphase data of n-1 level shifted data, and the grid of transistor seconds is imported n level shift clock signal, and the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of n level shift register, and the 4th transistor drain couples second output terminal of n level shift register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, the 5th transistorized source electrode input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

19. drive unit according to claim 18 is characterized in that, described impact damper comprises:

20. drive unit according to claim 19; It is characterized in that; Said pull-up unit is for pulling up transistor; The said first drop-down unit is first pull-down transistor, and the said second drop-down unit is second pull-down transistor, and the switch element that the said control first drop-down unit opens and closes is a switching transistor.

21. drive unit according to claim 20 is characterized in that,

The 2n-1 level impact damper of described buffer cell comprises plurality of transistors, wherein,

The 2n level impact damper of described buffer cell comprises plurality of transistors, wherein,

The source electrode that pulls up transistor and the source electrode of switching transistor couple; Input end as 2n level impact damper; The said input end input left side second buffered clock signal; The said grid that pulls up transistor is imported n level shifted data, and the said drain electrode that pulls up transistor couples the output terminal of said impact damper, and the grid of said switching transistor is imported the antiphase data of n level shifted data; The drain electrode of said switching transistor couples the grid of first pull-down transistor; The source electrode input left side first buffered clock signal of said first pull-down transistor, the grid of second pull-down transistor is also imported the said left side first buffered clock signal, and the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said 2n level impact damper; The source electrode input left side second buffered clock signal of said second pull-down transistor, the output terminal of said 2n level impact damper is exported 2n level drive signal.

22. drive unit according to claim 21; It is characterized in that the grid of the first transistor of the grid of said second pull-down transistor of said 2n level impact damper, the source electrode of said first pull-down transistor, said n level shift register and the grid of transistor seconds couple; The grid of the first transistor of the source electrode that pulls up transistor of said 2n level impact damper, the source electrode of second pull-down transistor and n+1 level shift register and the grid of transistor seconds couple.

23. drive unit according to claim 1 is characterized in that,

24. drive unit according to claim 1 is characterized in that, said drive unit comprises two said shift units, is respectively left side shift unit and right side shift unit; Said drive unit comprises two said buffer cells, is respectively left side buffer cell and right side buffer cell; Wherein,

Said left side shift unit links to each other with said left side buffer cell; The left side n level shift register of left side shift unit connects the left side n level impact damper of said left side buffer cell; Said left side n level impact damper is according to left side n level buffered clock signal and left side n level shifted data; And the antiphase data of left side n level shifted data, export 2n-1 level drive signal;

25. drive unit according to claim 24 is characterized in that, left side n level buffered clock signal comprises left side first buffered clock signal and the left side second buffered clock signal; Right side n level buffered clock signal comprises right side first buffered clock signal and the right side second buffered clock signal;

26. drive unit according to claim 1 is characterized in that, said drive unit comprises two said shift units, is respectively left side shift unit and right side shift unit; Said drive unit comprises two said buffer cells, is respectively left side buffer cell and right side buffer cell; Wherein,

Said left side shift unit links to each other with said left side buffer cell, exports n level drive signal;

Said right side shift unit links to each other with said right side buffer cell, exports n level drive signal.

27. drive unit according to claim 26 is characterized in that, the left side n level shift register of said left side shift unit connects the left side n level impact damper of said left side buffer cell, and said left side n level impact damper is exported n level drive signal;

The right side n level shift register of said right side shift unit connects said right side n level impact damper, and said right side n level impact damper is exported n level drive signal.

28. drive unit according to claim 26 is characterized in that,

The left side n level shift register of said left side shift unit connects the left side 2n-1 level impact damper of said left side buffer cell and the left side 2n level impact damper of said left side buffer cell; Said left side 2n level impact damper is exported 2n level drive signal, and said left side 2n-1 level impact damper is exported 2n-1 level drive signal;

29. a shift register is used for the antiphase data of shifted data and shifted data are shifted respectively, comprising:

30. shift register according to claim 29 is characterized in that, the structure of said switch element is a symmetrical structure.

31. shift register according to claim 30 is characterized in that, the symmetrical structure of said switch element is made up of first switch element of symmetry and second switch unit; The first input end of said first switch element is connected with said shifted data, and second input end of said first switch element is connected with said clock signal; The first input end of said second switch unit is connected with the antiphase data of said shifted data, and second input end of said second switch unit is connected with said clock signal.

32. shift register according to claim 31 is characterized in that, the structure of said high level output unit is a symmetrical structure.

33. shift register according to claim 32; It is characterized in that; The symmetrical structure of said high level output unit is made up of the first high level output unit of symmetry and the second high level output unit; The input end of the input end of the said first high level output unit and the said second high level output unit all is connected high level; The output terminal of the said first high level output unit is connected with first output terminal of shift register, and the output terminal of the said second high level output unit is connected with second output terminal of shift register.

34. shift register according to claim 33 is characterized in that, the structure of said low level output unit is a symmetrical structure.

35. shift register according to claim 34; It is characterized in that; The symmetrical structure of said low level output unit is made up of the first low level output unit of symmetry and the second low level output unit; The input end of the input end of the said first low level output unit and the said second low level output unit all is connected low level; The output terminal of the said first low level output unit is connected with first output terminal of shift register, and the output terminal of the said second low level output unit is connected with second output terminal of shift register.

36. shift register according to claim 35; It is characterized in that said first switch element is a first transistor, said second switch unit is a transistor seconds; The said first high level output unit is the 3rd transistor; The said second high level output unit is the 4th transistor, and the said first low level output unit is the 5th transistor, and the said second low level output unit is the 6th transistor.

37. according to each said shift register in the claim 29 to 36, it is characterized in that, the source electrode input shifted data of the first transistor, the grid input shift clock signal of the first transistor, the drain electrode of the first transistor and the 3rd transistorized grid couple; The antiphase data of the source electrode input shifted data of transistor seconds, the grid input shift clock signal of transistor seconds, the drain electrode of transistor seconds and the 4th transistorized grid couple; The 3rd transistor and the 4th transistorized source electrode input high level, the 3rd transistor drain couples first output terminal of shift register, and the 4th transistor drain couples second output terminal of shift register; The 5th transistorized grid couples the drain electrode of transistor seconds, and the 5th transistor drain couples the 3rd transistor drain, and the 5th transistorized source electrode couples input low level; The 6th transistorized grid couples the drain electrode of the first transistor, and the 6th transistor drain couples the 4th transistor drain, the 6th transistorized source electrode input low level.

38. shift unit that comprises any described shift register of claim 29 to 36; It is characterized in that; Comprise the shift register of two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data.

39. an impact damper is characterized in that, links to each other with shift register, output drive signal and n level shift register connect the said impact damper of n level, and said n level impact damper is exported n level drive signal, and wherein, n is a natural number; Said shift register is two-stage series connection at least; The said shift register of n level is exported the antiphase data of n level shifted data and n level shifted data according to the antiphase data of n level shift clock signal, n-1 level shifted data and n-1 level shifted data;

Said impact damper comprises:

40. according to the described impact damper of claim 39; It is characterized in that; Said pull-up unit is for pulling up transistor; The said first drop-down unit is first pull-down transistor, and the said second drop-down unit is second pull-down transistor, and the switch element that the said control first drop-down unit opens and closes is a switching transistor.

41. according to claim 39 or 40 described impact dampers; It is characterized in that the source electrode that pulls up transistor and the source electrode of switching transistor couple, as the input end of impact damper; Said input end is imported the second buffered clock signal; The said grid input shifted data that pulls up transistor, the said drain electrode that pulls up transistor couples the output terminal of said impact damper, the antiphase data of the grid input shifted data of said switching transistor; The drain electrode of said switching transistor couples the first pull-down transistor grid; The source electrode of first pull-down transistor is imported the first buffered clock signal, and the drain electrode of the drain electrode of said first pull-down transistor and second pull-down transistor couples the output terminal of said impact damper, and the grid of said second pull-down transistor is imported the said first buffered clock signal; The source electrode of said second pull-down transistor is imported the second buffered clock signal, the output terminal output drive signal of said impact damper.

42. a driving method that comprises each described drive unit of claim 1-10 is characterized in that, comprises step:

43. according to the described driving method of claim 42; It is characterized in that; Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; And said n level shift clock signal high level lasting time is a half in its cycle, and the said n level drive signal of output is a single pulse signal, and its high level lasting time is the half the of said n level shift clock signal period.

44. according to the described driving method of claim 42; It is characterized in that; When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; And said n level shift clock signal high level lasting time is a half in its cycle, and the said n level drive signal of output is the dipulse signal, and wherein each high level lasting time is the half the of said n level shift clock signal period.

45. a driving method that comprises each described drive unit of claim 24-28 is characterized in that, comprises step:

46. according to the described driving method of claim 45; It is characterized in that; Equate when the high level lasting time and the said left side n level shift clock signal period of said left side n level shifted data; Said left side n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said 2n-1 level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said left side n level shift clock signal period.

47. according to the described driving method of claim 45; It is characterized in that; Equate when the high level lasting time and the said right side n level shift clock signal period of said right side n level shifted data; Said right side n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said 2n level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said right side n level shift clock signal period.

48. according to the described driving method of claim 45; It is characterized in that; When the high level lasting time of said left side n level shifted data 2 times of said left side n level shift clock signal period; Said left side n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said 2n-1 level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said left side n level shift clock signal period.

49. according to the described driving method of claim 45; It is characterized in that; When the high level lasting time of said right side n level shifted data 2 times of said right side n level shift clock signal period; Said right side n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said 2n level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said right side n level shift clock signal period.

50. a driving method that comprises each described drive unit of claim 11-22 is characterized in that, comprises step:

51. according to the described driving method of claim 50; It is characterized in that; Equate when the high level lasting time and the said n level shift clock signal period of said n level shifted data; Said n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said n level drive signal of output is a single pulse signal, and its high level lasting time is 1/4th of the said n level shift clock signal period.

52. according to the described driving method of claim 50; It is characterized in that; When the high level lasting time of said n level shifted data 2 times of said n level shift clock signal period; Said n level shift clock signal high level lasting time is that four of its cycle/for the moment, the said n level drive signal of output is the dipulse signal, and wherein each high level lasting time is 1/4th of the said n level shift clock signal period.

53. LCD that comprises the described drive unit of claim 1; Also comprise display panels and data driven unit, said display panels comprises the pel array with at least 4 pixel cells, and each pixel cell comprises a thin film transistor (TFT); Each source electrode that is listed as said thin film transistor (TFT) is connected to same data line; Said data line links to each other with data driven unit, and the grid of each row thin film transistor (TFT) is connected to same gate line, and said gate line links to each other with drive unit.

54., it is characterized in that n level shift register connects the said impact damper of n level according to the described LCD of claim 53, said n level impact damper is exported n level drive signal.

55. according to the described LCD of claim 53; It is characterized in that; N level shift register connects 2n level and 2n-1 level impact damper, and said 2n-1 level impact damper is exported 2n-1 level drive signal, and said 2n level impact damper is exported 2n level drive signal.

56., it is characterized in that said drive unit comprises two said shift units according to claim 54 or 55 described LCDs, with two buffer cells that are connected with shift unit respectively, said two buffer cells connect the two ends of said gate line respectively.

57. according to claim 54 or 55 described LCDs; It is characterized in that; Said drive unit comprises two said shift units; Two buffer cells that are connected with shift unit respectively, one of them said buffer cell connects the even number line gate line from an end of gate line, and another buffer cell connects the odd-numbered line gate line from the other end of gate line.