CN101840852A - Method for manufacturing ordered semiconductor nanostructures on graphical semiconductor substrate - Google Patents
Method for manufacturing ordered semiconductor nanostructures on graphical semiconductor substrate Download PDFInfo
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- CN101840852A CN101840852A CN 201010140985 CN201010140985A CN101840852A CN 101840852 A CN101840852 A CN 101840852A CN 201010140985 CN201010140985 CN 201010140985 CN 201010140985 A CN201010140985 A CN 201010140985A CN 101840852 A CN101840852 A CN 101840852A
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Abstract
The invention discloses a method for manufacturing ordered semiconductor nanostructures on a graphical semiconductor substrate. The method comprises the following steps of: 1, selecting the semiconductor substrate and manufacturing a bar-shaped graph or a round hole graph on the substrate by a photoetching method; 2, preparing collaurum-containing solution; 3, dipping the substrate on which the bar-shaped graph or the round hole graph is manufactured in the prepared collaurum-containing solution and pulling the substrate out of the solution; 4, gluing the substrate in a gluing machine and cleaning the substrate by using a chemical reagent; and 5, placing the substrate into a chamber of growth equipment to grow a single layer or a plurality of layers of the nanostructures. Due to the adoption of the method for manufacturing the ordered semiconductor nanostructures on the graphical semiconductor substrate, a quantum wire array which has uniform size and ordered arrangement is manufactured, wherein the quantum wire array can be used for manufacturing active layers of luminescent devices and electron devices, preparing semiconductor field effect transistors which have high performance, light emitting devices which have very low energy consumption, various sensors and detectors and the like.
Description
Technical field
The present invention relates to the nanometer semiconductor structure preparing technical field, relate in particular to a kind of method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure.
Background technology
The non-linear optical property that quantum wire semiconductor shows because of its one-dimensional nano structure, Anisotropically conductive performance, dichroism and unique magnetic performance have extremely important application at aspects such as electronics and opto-electronic device, high density magnetic storages.On the other hand, because small scale effects such as quantum size effect tend to transporting with optical property of low-dimension nano material produced material impact, may in light-emitting display device of future generation, light filtration and light cutoff device, use.Therefore potential using value and the important significance for theories of quantum wire semiconductor caused the extensive concern of scientist to the quantum wire technology of preparing.The development of quantum wire semiconductor is significant for the microminiaturization and the ultrahigh speedization of integrated circuit.
Nanometer semiconductor structure is the small crystal structure of nano-scale range, because three (two) dimension quantum limit effects, nanometer semiconductor structure has discrete electron spectrum, thereby has traditional body material and not available special optics of quantum-well materials and electrical properties.The more important thing is that these special photoelectric properties depend on the size and dimension of nanometer semiconductor structure fully, can be by the size of nanometer semiconductor structure and the control of shape be realized manually cutting out the nanometer semiconductor structure photoelectric property.Quantum wire semiconductor is the semiconductor nano material that is subjected to two-dimentional quantum limit effect, and the non-linear optical property, Anisotropically conductive performance, dichroism and the unique magnetic performance that show because of its one-dimensional nano structure have extremely important application at aspects such as electronics and opto-electronic device, high density magnetic storages.On the other hand, because small scale effects such as quantum size effect tend to transporting with optical property of low-dimension nano material produced material impact, may in light-emitting display device of future generation, light filtration and light cutoff device, use.Therefore potential using value and the important significance for theories of quantum wire semiconductor caused the broad research of scientist to the quantum wire technology of preparing.The development of quantum wire semiconductor is significant for the microminiaturization and the ultrahigh speedization of integrated circuit.
In recent years, carried out many-sided research both at home and abroad aspect the growth of quantum wire, the method for preparing quantum wire usually mainly is that gas one liquid one solid method (VLS) directly synthesized semiconductor quantum wire and template self-assembly method are arranged.Wherein the direct synthesized semiconductor quantum wire of gas one liquid, one solid method (VLS) can be realized in molecular beam epitaxy (MBE), organo-metallic compound vapour deposition semiconductor epitaxial equipment commonly used such as (MOCVD), its process generally includes following steps: at first be the deoxidation of Semiconductor substrate and the growth of resilient coating, to obtain smooth clean Surface, then at surface deposition one deck gold film, be high annealing at last to form the Au-Ga drop, the deposition growing material is to obtain quantum wire.This conventional method be owing to can't control the size of Au-Ga drop in annealing process, and the diameter of quantum wire to be size by the Au-Ga drop determined, the therefore quantum wire size big rise and fall of preparation, uniformity is difficult to control.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate, to prepare the quantum linear array that size is even, arrangement is orderly.
(2) technical scheme
For achieving the above object, the invention provides a kind of method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure, this method comprises:
Step 1: select Semiconductor substrate, on substrate, produce bar shaped or circular hole figure by photoetching method;
Step 2: configuration contains the solution of collaurum;
Step 3: the substrate that will produce bar shaped or circular hole figure immerses in the solution that contains collaurum of configuration, and substrate is lifted out from solution;
Step 4: substrate is played glue and clean in adhesive supplier with chemical reagent;
Step 5: substrate is put into the chamber of growth apparatus and the single or multiple lift nanostructure of growing.
In the such scheme, described nanometer semiconductor structure is meant that charge carrier is subjected to the quantum wire of two-dimentional quantum limit.
In the such scheme, the Semiconductor substrate described in the step 1 comprises Semiconductor substrate GaAs, InP or the Si with multiple crystal plane direction; The photoetching method that is adopted is holographic exposure, common mask aligner photoetching or electron beam exposure; Described bar shaped or circular hole figure, the various cycles in comprising from 100nm to the 1200nm scope.
In the such scheme, described in the step 3 substrate being lifted out from solution, is to select different pull rate according to different periodic structures.
In the such scheme, step 4 is described beat that the glue process need determines beat the glue parameter, be respectively oxygen plasma and bombard, bombardment time is 10 minutes, power is 100mW.
In the such scheme, the described cleaning process of step 4 comprises following detailed process: earlier with acetone in the ultrasonic cleaning machine ultrasonic 10 minutes, in the ethanol ultrasonic 5 minutes then, carrying out water-bath then cleans, in the water-bath heating furnace, will in organic solvent, soak the container water-bath heating of sample after the water boiling by the time, pick up counting behind organic solvent boiling, timing is 5 minutes behind every kind of organic solvent boiling, changes a kind of solvent then; The order of the organic solvent that is adopted is: ethanol, acetone, trichloroethylene, trichloroethylene, acetone, ethanol; After the water-bath process finishes, use deionized water rinsing 30 times, N
2Dry up, be placed on and wait for sample on the sample platform.
In the such scheme, the growth single or multiple lift nanostructure described in the step 5 adopts suitable temperature and growth rate in growth course, and this growth temperature and growth rate are decided on different materials and substrate.
In the such scheme, growth single or multiple lift nanostructure described in the step 5 is meant that the composition of quantum wire is a single or multiple lift, each layer growth thickness is increased to hundreds of nanometers from several nanometers as required, and the material between the different layers is different materials or same material.
In the such scheme, the single or multiple lift nanometer semiconductor structure that this method is grown is used for the active layer as opto-electronic device and electronic device, and opto-electronic device and electronic device comprise semiconductor laser, light-emitting diode or semiconductor field effect transistor.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, this method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate provided by the invention is applicable to all kinds of epitaxial growth equipments commonly used at present, as molecular beam epitaxy (MBE), and metal organic chemical vapor deposition method (MOCVD) etc.
2, this method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure provided by the invention, be applicable to multiple solid substrate such as comprising Si, GaAs, InP, and the Semiconductor substrate of different orientation, and the spacing of Au nano particle, density all is regulatable, therefore spacing and the density that can modulate quantum wire.
3, this method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure provided by the invention, it is low to be used to prepare quantum Wiring technology cost, do not need expensive nanoprocessing process equipment can finish the preparation of nano graph substrate, and the crystal mass height of quantum wire, size is even, under certain experiment condition and be expected to realize location to quantum wire.
4, this method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure provided by the invention, be first the PS-PVP reverse micelle to be combined the method that obtains the ordered nano gold grain with patterned substrate, the new method that provides that realizes good uniformity, arranges orderly quantum wire semiconductor is provided.
Description of drawings
Fig. 1 is the process flow diagram that the PS-PVP reverse micelle that provides in the embodiment of the invention prepares the monometallic nano-grain array;
Fig. 2 is the patterned substrate that adopts the preparation of holographic exposure technology in the embodiment of the invention, and atomic force microscope figure orderly based on the arrangement of patterned substrate preparation, the uniform Au nano particle of size.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention adopts the method for amphiphilic block copolymer PS-b-P2VP self assembly to prepare orderly arrangement on Semiconductor substrate, the Au nano particle of size homogeneous, and with this catalyst as quantum wire, preparation size is even, arrange orderly quantum linear array.Utilize the PS-PVP reverse micelle method to prepare the metal nanoparticle array on different solid substrate, its technical process mainly comprises following step: 1. PS-PVP is dissolved in the selective solvent, PS-PVP forms reverse micelle with self assembly; 2. add slaine in micellar solution, slaine will be loaded to the kernel the inside of reverse micelle, form slaine load reverse micelle; 3. dip-coating deposits to slaine load reverse micelle on the solid substrate; 4. plasma treatment is got rid of the PS-PVP parent and the reducing metal nano particle.In the experiment,, usually be to be full of the glove box of high pure nitrogen to carry out from the preparation of micellar solution and micella array in the deposition on the solid substrate, to guarantee certain temperature and humidity for fear of the influence of water in air steam.
Method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate provided by the invention specifically may further comprise the steps:
Step 1: select Semiconductor substrate, on substrate, produce bar shaped or circular hole figure by photoetching method;
Step 2: configuration contains the solution of collaurum;
Step 3: the substrate that will produce bar shaped or circular hole figure immerses in the solution that contains collaurum of configuration, and substrate is lifted out from solution;
Step 4: substrate is played glue and clean in adhesive supplier with chemical reagent;
Step 5: substrate is put into the chamber of growth apparatus and the single or multiple lift nanostructure of growing.
This nanometer semiconductor structure is used to make the active layer of luminescent device and electronic device.On Semiconductor substrate, obtain periodic bar shaped and circular hole two-dimensional array by fabrication techniques such as holographic exposure photoetching, then patterned substrate is immersed in the pre-configured colloidal gold solution, the nm of gold colloid array that under suitable pull rate, just can be arranged in order, through after playing glue, collaurum becomes nanogold particle, carry out epitaxial growth through entering the MBE chamber after the cleaning process, nm of gold has catalytic action in the growth course, thereby obtain orderly nano-wire array, for the development of semiconductor photoelectronic device provides support.Because the good uniformity (diameter deviation is within 3nm) of nanogold particle, and the diameter of nano wire mainly relies on the granular size decision of nm of gold, so the nanometer semiconductor structure order that catalytic growth obtains is good, shape and size are even, controllability is strong, has good optics and electrical properties.This method can be used to make the active layer of luminescent device and electronic device, the semiconductor field effect transistor of processability excellence, the light emitting devices with low-down energy consumption and various types of inductor, detector etc.
Fig. 1 is the process flow diagram that the PS-PVP reverse micelle that provides in the embodiment of the invention prepares the monometallic nano-grain array.Detailed process is for the concentration of diblock copolymer polystyrene-poly vinylpyridine (PS-PVP) by 1mg/mL is dissolved in the toluene in the present embodiment, after waiting for 1 day time, in inverse micellar solution, add HAuCl4 again, stir through 3～5 days do not stop, the slaine molecule of gold will enter and be fixed on the kernel the inside of reverse micelle.After solution prepares, patterned substrate is immersed in the solution, from solution, slowly lift with the pull rate of 2mm/min, obtain to arrange orderly gold colloid particles, use 100mW then in plasma degumming machine, bombardment 10min just can obtain having arranged orderly Au nano particle.
Fig. 2 is the patterned substrate that adopts the preparation of holographic exposure technology in the embodiment of the invention, and atomic force microscope figure orderly based on the arrangement of patterned substrate preparation, the uniform Au nano particle of size.The substrate etching degree of depth is 120nm, and the corrosive liquid of employing is H3PO4: H2O2: H2O=3: 1: 50, corrosion rate was about 1nm/s.Can obtain smooth corrosion surface like this, this is to the important function that is positioned with of Au.
Provided by the invention this on Semiconductor substrate preparation size even, thereby arrange the method that orderly gold nano grain is used for the catalytic growth quantum wire semiconductor, mainly be patterned substrate to be lifted out with certain speed in containing the organic solvent of gold colloid by czochralski method, thereby obtain collaurum nano particle along pattern arrangement, enter the MBE growth room through after a series of processing, deposited semiconductor material is to obtain the quantum linear array that size is even, arrangement is orderly then.The quantum wire semiconductor of this method preparation can be used to make the active layer of luminescent device and electronic device, prepares that threshold current is low, good temp characteristic, the luminescent device with low-down energy consumption and various types of inductor, detector etc.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate is characterized in that this method comprises:
Step 1: select Semiconductor substrate, on substrate, produce bar shaped or circular hole figure by photoetching method;
Step 2: configuration contains the solution of collaurum;
Step 3: the substrate that will produce bar shaped or circular hole figure immerses in the solution that contains collaurum of configuration, and substrate is lifted out from solution;
Step 4: substrate is played glue and clean in adhesive supplier with chemical reagent;
Step 5: substrate is put into the chamber of growth apparatus and the single or multiple lift nanostructure of growing.
2. method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate according to claim 1 is characterized in that described nanometer semiconductor structure is meant that charge carrier is subjected to the quantum wire of two-dimentional quantum limit.
3. method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate according to claim 1 is characterized in that the Semiconductor substrate described in the step 1 comprises Semiconductor substrate GaAs, InP or the Si with multiple crystal plane direction; The photoetching method that is adopted is holographic exposure, common mask aligner photoetching or electron beam exposure; Described bar shaped or circular hole figure, the various cycles in comprising from 100nm to the 1200nm scope.
4. method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate according to claim 1 is characterized in that, described in the step 3 substrate is lifted out from solution, is to select different pull rate according to different periodic structures.
5. method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure according to claim 1, it is characterized in that, step 4 is described beat that the glue process need determines beat the glue parameter, be respectively oxygen plasma and bombard, bombardment time is 10 minutes, and power is 100mW.
6. method of making orderly nanometer semiconductor structure on patterned Semiconductor substrate according to claim 1 is characterized in that the described cleaning process of step 4 comprises following detailed process:
Earlier with acetone in the ultrasonic cleaning machine ultrasonic 10 minutes, in the ethanol ultrasonic 5 minutes then, carrying out water-bath then cleans, in the water-bath heating furnace, will in organic solvent, soak the container water-bath heating of sample after the water boiling by the time, behind organic solvent boiling, pick up counting, timing is 5 minutes behind every kind of organic solvent boiling, changes a kind of solvent then; The order of the organic solvent that is adopted is: ethanol, acetone, trichloroethylene, trichloroethylene, acetone, ethanol; After the water-bath process finishes, use deionized water rinsing 30 times, N
2Dry up, be placed on and wait for sample on the sample platform.
7. method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure according to claim 1, it is characterized in that, growth single or multiple lift nanostructure described in the step 5, adopt suitable temperature and growth rate in growth course, this growth temperature and growth rate are decided on different materials and substrate.
8. method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure according to claim 1, it is characterized in that, growth single or multiple lift nanostructure described in the step 5 is meant that the composition of quantum wire is a single or multiple lift, each layer growth thickness is increased to hundreds of nanometers from several nanometers as required, and the material between the different layers is different materials or same material.
9. method of on patterned Semiconductor substrate, making orderly nanometer semiconductor structure according to claim 1, it is characterized in that, the single or multiple lift nanometer semiconductor structure that this method is grown is used for the active layer as opto-electronic device and electronic device, and opto-electronic device and electronic device comprise semiconductor laser, light-emitting diode or semiconductor field effect transistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593047A (en) * | 2012-02-24 | 2012-07-18 | 温州大学 | Preparation method of conductive film pattern layer based on oil-solubility nano-particle ink |
| CN109309158A (en) * | 2018-08-02 | 2019-02-05 | 京东方科技集团股份有限公司 | Pattern organic film preparation method, the preparation method of array substrate |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050230356A1 (en) * | 2002-04-02 | 2005-10-20 | Nanosys, Inc. | Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices |
| CN1870294A (en) * | 2005-05-23 | 2006-11-29 | 国际商业机器公司 | Semiconductor structure and method of forming same |
| CN1906332A (en) * | 2003-12-18 | 2007-01-31 | 新日本石油株式会社 | Nano-array electrode manufacturing method and photoelectric converter using same |
| CN101331590A (en) * | 2005-12-29 | 2008-12-24 | 纳米***公司 | Methods for oriented growth of nanowires on patterned substrates |
| WO2009021988A1 (en) * | 2007-08-14 | 2009-02-19 | Universite Libre De Bruxelles | Method for depositing nanoparticles on a support |
| CN101458242A (en) * | 2007-12-11 | 2009-06-17 | 郑州轻工业学院 | Nanogold Colloid for responding heavy metal ion and method for making same |
-
2010
- 2010-04-02 CN CN 201010140985 patent/CN101840852A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050230356A1 (en) * | 2002-04-02 | 2005-10-20 | Nanosys, Inc. | Methods of making, positioning and orienting nanostructures, nanostructure arrays and nanostructure devices |
| CN1906332A (en) * | 2003-12-18 | 2007-01-31 | 新日本石油株式会社 | Nano-array electrode manufacturing method and photoelectric converter using same |
| CN1870294A (en) * | 2005-05-23 | 2006-11-29 | 国际商业机器公司 | Semiconductor structure and method of forming same |
| CN101331590A (en) * | 2005-12-29 | 2008-12-24 | 纳米***公司 | Methods for oriented growth of nanowires on patterned substrates |
| WO2009021988A1 (en) * | 2007-08-14 | 2009-02-19 | Universite Libre De Bruxelles | Method for depositing nanoparticles on a support |
| CN101458242A (en) * | 2007-12-11 | 2009-06-17 | 郑州轻工业学院 | Nanogold Colloid for responding heavy metal ion and method for making same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593047A (en) * | 2012-02-24 | 2012-07-18 | 温州大学 | Preparation method of conductive film pattern layer based on oil-solubility nano-particle ink |
| CN109309158A (en) * | 2018-08-02 | 2019-02-05 | 京东方科技集团股份有限公司 | Pattern organic film preparation method, the preparation method of array substrate |
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Open date: 20100922 |