CN101840242B - CMOS low power consumption voltage current offset start-up circuit - Google Patents
CMOS low power consumption voltage current offset start-up circuit Download PDFInfo
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- CN101840242B CN101840242B CN2010101871567A CN201010187156A CN101840242B CN 101840242 B CN101840242 B CN 101840242B CN 2010101871567 A CN2010101871567 A CN 2010101871567A CN 201010187156 A CN201010187156 A CN 201010187156A CN 101840242 B CN101840242 B CN 101840242B
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Abstract
The invention discloses a CMOS low power consumption voltage current offset start-up circuit, comprising a resistor (R0), PMOS tubes (M1, M3, M7, M9, M11) and NMOS tubes (M2, M4-6, M8, M10, M12). The invention has simple and practical circuit structure and controls the power consumption of the circuit in a simple and convenient manner so that the start-up circuit of the integrated circuit achieves the zero-consumption effect, and the power consumption of the integrated circuit is greatly reduced. The CMOS low power consumption voltage current offset start-up circuit is applied widely in start-up of reference and offset circuit of the integrated circuit.
Description
Technical field
The present invention relates to a kind of hardware circuit, particularly a kind of CMOS low power consumption voltage current offset start-up circuit.
Background technology
The tradition biasing circuit is one of key factor of decision-making circuit system stability and reliably working, and the metal-oxide-semiconductor in the biasing circuit lost efficacy, and can cause entire circuit thrashing, therefore must improve the reliability of voltage and current biasing circuit.Because overall voltage or overall current offset technology are generally adopted in chip design, when biasing branch road cisco unity malfunction, must provide needed bias voltage of entire circuit or electric current, cause system crash.The biasing circuit transient state starts the inefficacy that may exist, and is to cause normally one of the key factor of steady operation of system.
Should make start-up circuit can satisfy 3 requirements during the parameter of design start-up circuit: at first can pour into electric current, realize start function to biasing circuit; Secondly, biasing circuit must can turn-off getting in touch of start-up circuit and biasing circuit after starting, and promptly start-up circuit only works at system's powered on moment, after stablizing to the circuit operate as normal without any influence; At last, behind the circuit start, start-up circuit should keep very low power consumption, does not perhaps have power consumption.
When power supply when the branch road on ground is the low impedance path, form stable electric current in the branch road.When formed electric current after converting stable voltage on each class component, can provide biasing for system.The low impedance path mainly comprises passive resistance, active MOS or BJT diode saturation resistance, active linear resistance under the large-signal control or the like.There is not the startup problem usually in the equivalence low impedance path, but its bias current is linear change with voltage is approximate, causes under the high pressure system power dissipation remarkable.In addition, quiescent biasing changes in a big way, brings adverse effect can for the steady operation of circuit.For the bias structure of low-power consumption high performance analog circuit, Monotone Type and peak value type are two kinds of most widely used typical nonlinear biasing circuits.As depicted in figs. 1 and 2, owing to there is the saturated sectional pressure element of Vds, thereby there is not the low impedance path in wherein any branch road, solved the shortcoming of low-resistance biasing branch road, but the difficulty of but having brought transient state to start.
Transient state starts principle
The reason that non-linear biasing circuit need start is that its stable operating point generally all has two: a desired quiescent point that reaches when being circuit design, another then is zero point.The function of start-up circuit is exactly the forced disturbance by the external world, forces circuit to leave zero point, utilizes the FEEDBACK CONTROL of self then, arrives the stable operating point of design automatically.Among Fig. 1, should inject starting current from M2222 diode grid leak, even the electric current that injects is very little, as long as can start the counterclockwise positive current feedback loop of M2222 → M1111 → M3333 → M4444 → M2222 as shown in Figure 1, just can force the working point little by little to leave zero point, approach the A point.If it is excessive to start the electric current I of injecting 2, perhaps inject and cause the I2 overshoot by the startup of above-mentioned reason, exceed the A point range, then the clockwise Current Negative Three-Point Capacitance loop of M2222 → M4444 → M3333 → M1111 → M2222 begins to work, and forces the working point finally to get back to the A point and reaches stable.
In the peak value type biasing circuit in Fig. 3 and 4, the direction of current feedback is fixed, the counterclockwise transmit ring of M111 → M222 → M444 → M333 → M111, therefore the character of feedback no longer is to realize by changing the loop direction, but realize by the peak value character of self current source.Because the peak point of NMOS current source appears at before the A point among the figure, be injected to positive feedback for a short time less than what A was ordered in the drawings, and be higher than that A orders be injected to negative feedback greatly.Therefore, the startup of this biasing circuit is quite reliable, as long as little injection starting current is enough, system just can autostable at the A point.Equally, when initial injection current was excessive, system also can maintain stable working point A automatically.
After conventional start-up circuit is stable, can there be certain power consumption,, after start-up circuit is stable, can has a very big power consumption so in the SOC design system if a lot of offset start-up circuits is arranged.
Summary of the invention
In order to solve above-mentioned technical matters, the purpose of this invention is to provide a kind of CMOS low power consumption voltage current offset start-up circuit that can eliminate the quiescent dissipation after start-up circuit is stablized.
The technical solution adopted for the present invention to solve the technical problems is:
The CMOS low power consumption voltage current offset start-up circuit, comprise first resistance, the one P field effect transistor, the 2nd P field effect transistor, the 3rd P field effect transistor, the 4th P field effect transistor, the 5th P field effect transistor, the one N field effect transistor, the 2nd N field effect transistor, the 3rd N field effect transistor, the 4th N field effect transistor, the 5th N field effect transistor, the 6th N field effect transistor, the 7th N field effect transistor, a described P field effect transistor and a N field effect transistor are formed phase inverter, power vd D respectively with the 2nd P field effect transistor, the 3rd P field effect transistor, the 4th P field effect transistor, the source electrode of the 5th P field effect transistor connects, the 5th P field effect transistor, the grid of the 2nd P field effect transistor and the 3rd N field effect transistor all is connected with the input end of phase inverter, the drain electrode of the 5th P field effect transistor respectively with the grid and the drain electrode of the 3rd P field effect transistor, the grid of the 4th P field effect transistor, the drain electrode of the 3rd N field effect transistor, the drain electrode of the 5th N field effect transistor connects, the drain electrode of described the 4th P field effect transistor respectively with the drain and gate of the 6th N field effect transistor, the drain electrode of the 7th N field effect transistor, the grid of the 5th N field effect transistor, the grid of the 2nd N field effect transistor connects, the grid of the 7th N field effect transistor is connected with the output terminal of phase inverter, the source electrode of described the 5th N field effect transistor is connected with ground VSS by first resistance, the 6th N field effect transistor, the 7th N field effect transistor, the 4th N field effect transistor, the source electrode of the 2nd N field effect transistor is connected with ground VSS, the drain electrode of the 4th N field effect transistor links to each other with the source electrode of the 3rd N field effect transistor, the grid of the 4th N field effect transistor respectively with the drain electrode of the 2nd P field effect transistor, the drain electrode of the 2nd N field effect transistor connects.
Be further used as preferred embodiment, the grid of described the 4th N field effect transistor is connected with power vd D through first electric capacity, and the grid of described the 4th N field effect transistor is connected with ground VSS through second electric capacity.
The invention has the beneficial effects as follows: circuit structure of the present invention is simple and practical, with the power consumption of easy mode control circuit, makes the start-up circuit of integrated circuit reach the effect of zero-power, thereby reduces power consumption of integrated circuit greatly.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples.
Fig. 1 is a Nonlinear Monotone type current source circuit;
Fig. 2 is the start-up course sequential chart of Nonlinear Monotone type current source circuit;
The linear peak value type of Fig. 3 right and wrong current source circuit;
The start-up course sequential chart of the linear peak value type of Fig. 4 right and wrong current source circuit;
Fig. 5 is the start-up circuit with the biasing circuit of power supply signal control;
Fig. 6 is with the start-up circuit that rises control on power supply control and the supply voltage slope.
Embodiment
With reference to Fig. 5, the CMOS low power consumption voltage current offset start-up circuit, comprise the first resistance R O, the one P field effect transistor M1, the 2nd P field effect transistor M3, the 3rd P field effect transistor M7, the 4th P field effect transistor M9, the 5th P field effect transistor M11, the one N field effect transistor M2, the 2nd N field effect transistor M4, the 3rd N field effect transistor M5, the 4th N field effect transistor M6, the 5th N field effect transistor M8, the 6th N field effect transistor M10, the 7th N field effect transistor M12, a described P field effect transistor M1 and a N field effect transistor M2 form phase inverter, power vd D respectively with the 2nd P field effect transistor M3, the 3rd P field effect transistor M7, the 4th P field effect transistor M9, the source electrode of the 5th P field effect transistor M11 connects, the 5th P field effect transistor M11, the grid of the 2nd P field effect transistor M3, the grid of the 3rd N field effect transistor M5 all is connected with the input end of phase inverter, the drain electrode of the 5th P field effect transistor M11 respectively with grid and the drain electrode of the 3rd P field effect transistor M7, the grid of the 4th P field effect transistor M9, the drain electrode of the 3rd N field effect transistor M5, the drain electrode of the 5th N field effect transistor M8 connects, the drain electrode of described the 4th P field effect transistor M9 respectively with the drain and gate of the 6th N field effect transistor M10, the drain electrode of the 7th N field effect transistor M12, the grid of the 5th N field effect transistor M8, the grid of the 2nd N field effect transistor M4 connects, the grid of the 7th N field effect transistor M12 is connected with the output terminal of phase inverter, the source electrode of described the 5th N field effect transistor M8 is connected with ground VSS by the first resistance R O, the 6th N field effect transistor M10, the 7th N field effect transistor M12, the 4th N field effect transistor M6, the source electrode of the 2nd N field effect transistor M4 is connected with ground VSS, the drain electrode of the 4th N field effect transistor M6 links to each other with the source electrode of the 3rd N field effect transistor M5, the drain electrode of the grid of the 4th N field effect transistor M6 and the 2nd P field effect transistor M3, the drain electrode of the 2nd N field effect transistor M4 connects.
Start-up circuit has comprised the 2nd P field effect transistor M3 among Fig. 5, the 2nd N field effect transistor M4, the 3rd N field effect transistor M5 and the 4th N field effect transistor M6, as PWR (power down) when signal is low level, the 3rd N field effect transistor M5 turn-offs, the 2nd P field effect transistor M3 conducting node A voltage rises to VDD, such the 4th N field effect transistor M6 conducting, but because PWR is a low level, the 3rd N field effect transistor M5 disconnects, starting current Istart is zero like this, Pbias and Nbias node just are respectively VDD and VSS like this, circuit will not have electric current to be passed through, and the 2nd N field effect transistor M4 turn-offs.When PWR was high level, the 2nd P field effect transistor M3 disconnected, the 3rd N field effect transistor M5 conducting, because Nbias still is a low level, the 2nd N field effect transistor M4 still is in off state, and the voltage of node A remains on VDD, and the 4th N field effect transistor M6 still keeps conducting state.Present the 3rd N field effect transistor M5, the 4th N field effect transistor M6 conducting, starting current Istart will flow out from Pbias, like this, Pbias voltage reduces to the VSS direction from VDD, electric current be will have like this and the 3rd P field effect transistor M7 and the 4th P field effect transistor M9 flow through, the Nbias charging, voltage raises to the VDD direction from VSS, and the 5th N field effect transistor M8 and the 6th N field effect transistor M10 have electric current to flow through, when Nbias is bigger than the threshold voltage of the 2nd N field effect transistor M4, the 2nd N field effect transistor M4 conducting, the A point voltage drops to zero, and such the 4th N field effect transistor M6 has just turn-offed, and starting current Istart has also turn-offed.The startup of whole like this biasing circuit has just been finished.
Be further used as preferred embodiment, be connected with power vd D through first capacitor C with reference to the grid of described the 4th N field effect transistor M6 of Fig. 6, the grid of described the 4th N field effect transistor M6 is connected with ground VSS through the second capacitor C p.
With reference to the start-up circuit of Fig. 6 with liter control on power supply Control of Voltage and the supply voltage slope.When PWR was low level, Pbias and Nbias were respectively VDD and VSS, and the 3rd N field effect transistor M5 disconnects, and Istart is zero.When PWR is high level, the 3rd N field effect transistor M5 conducting, Pbias and Nbias are respectively VDD and VSS, the 2nd P field effect transistor M3 disconnects, if VDD rises on the slope, the B point voltage can raise with VDD, because will keep the voltage difference at the first capacitor C two ends constant, the second capacitor C p is the stray capacitance that B is ordered, and has:
VB＝VDD×C/(C+Cp)
Relative first capacitor C of the second capacitor C p is very little generally speaking, with the threshold voltage of B point voltage greater than the 4th N field effect transistor M6, the 4th N field effect transistor M6 conducting, the Istart electric current flows out circuit, biasing circuit begins to start, Pbias voltage descends, and Nbias voltage rises, when the threshold voltage of Nbias voltage ratio the 2nd N field effect transistor M4 is big, the 2nd N field effect transistor M4 conducting, the B point voltage can drop to VSS, the start-up circuit power cut-off, and the electric current that flows through start-up circuit is zero.
More than be that preferable enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of spirit of the present invention, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.
Claims (2)
1.CMOS low power consumption voltage current offset start-up circuit, it is characterized in that: comprise first resistance (RO), the one P field effect transistor (M1), the 2nd P field effect transistor (M3), the 3rd P field effect transistor (M7), the 4th P field effect transistor (M9), the 5th P field effect transistor (M11), the one N field effect transistor (M2), the 2nd N field effect transistor (M4), the 3rd N field effect transistor (M5), the 4th N field effect transistor (M6), the 5th N field effect transistor (M8), the 6th N field effect transistor (M10), the 7th N field effect transistor (M12), a described P field effect transistor (M1) is formed phase inverter with a N field effect transistor (M2), power vd D respectively with the 2nd P field effect transistor (M3), the 3rd P field effect transistor (M7), the 4th P field effect transistor (M9), the source electrode of the 5th P field effect transistor (M11) connects, the 5th P field effect transistor (M11), the grid of the 2nd P field effect transistor (M3) and the 3rd N field effect transistor (M5) all is connected with the input end of phase inverter, the drain electrode of the 5th P field effect transistor (M11) respectively with the grid and the drain electrode of the 3rd P field effect transistor (M7), the grid of the 4th P field effect transistor (M9), the drain electrode of the 3rd N field effect transistor (M5), the drain electrode of the 5th N field effect transistor (M8) connects, the drain electrode of described the 4th P field effect transistor (M9) respectively with the drain and gate of the 6th N field effect transistor (M10), the drain electrode of the 7th N field effect transistor (M12), the grid of the 5th N field effect transistor (M8), the grid of the 2nd N field effect transistor (M4) connects, the grid of the 7th N field effect transistor (M12) is connected with the output terminal of phase inverter, the source electrode of described the 5th N field effect transistor (M8) is connected with ground VSS by first resistance (RO), the 6th N field effect transistor (M10), the 7th N field effect transistor (M12), the 4th N field effect transistor (M6), the source electrode of the 2nd N field effect transistor (M4) is connected with ground VSS, the drain electrode of the 4th N field effect transistor (M6) links to each other with the source electrode of the 3rd N field effect transistor (M5), the grid of the 4th N field effect transistor (M6) respectively with the drain electrode of the 2nd P field effect transistor (M3), the drain electrode of the 2nd N field effect transistor (M4) connects.
2. CMOS low power consumption voltage current offset start-up circuit according to claim 1, it is characterized in that: the grid of described the 4th N field effect transistor (M6) is connected with power vd D through first electric capacity (C), and the grid of described the 4th N field effect transistor (M6) is connected with ground VSS through second electric capacity (Cp).
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101871567A CN101840242B (en) | 2010-05-21 | 2010-05-21 | CMOS low power consumption voltage current offset start-up circuit |
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| CN2010101871567A CN101840242B (en) | 2010-05-21 | 2010-05-21 | CMOS low power consumption voltage current offset start-up circuit |
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| CN101840242B true CN101840242B (en) | 2011-12-14 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103049026B (en) * | 2011-10-12 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Current biasing circuit |
| CN102520756B (en) * | 2011-12-28 | 2013-09-25 | 南京邮电大学 | Bias current generating circuit |
| CN104777760B (en) * | 2014-01-13 | 2017-12-19 | 上海华虹集成电路有限责任公司 | Super low-power consumption MCU safe starting method and circuit |
| CN108008756B (en) * | 2017-12-28 | 2023-08-29 | 珠海博雅科技股份有限公司 | Reference voltage source and voltage stabilizing circuit |
| CN111381625B (en) * | 2020-03-12 | 2022-05-20 | 上海华虹宏力半导体制造有限公司 | Reference source circuit |
| CN111552342A (en) * | 2020-05-21 | 2020-08-18 | 东南大学 | Low-power-consumption reference voltage and reference current generating circuit |
| CN114690823B (en) * | 2020-12-25 | 2024-06-18 | 圣邦微电子（北京）股份有限公司 | Output stage circuit of power supply monitoring chip |
| CN113359542B (en) * | 2021-05-21 | 2024-02-09 | 深圳拓邦股份有限公司 | Low-power consumption control circuit and electric appliance |
| CN113885639B (en) * | 2021-09-28 | 2023-05-05 | 深圳市爱协生科技股份有限公司 | Reference circuit, integrated circuit, and electronic device |
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