CN101836282B - 具有较低接触电阻的mos结构及其制造方法 - Google Patents

具有较低接触电阻的mos结构及其制造方法 Download PDF

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CN101836282B
CN101836282B CN2008801076621A CN200880107662A CN101836282B CN 101836282 B CN101836282 B CN 101836282B CN 2008801076621 A CN2008801076621 A CN 2008801076621A CN 200880107662 A CN200880107662 A CN 200880107662A CN 101836282 B CN101836282 B CN 101836282B
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S·巴拉苏布拉马尼安
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Abstract

本发明提供具有较低接触电阻的MOS结构(100、200)与制造此MOS结构的方法。在一个方法中，提供半导体衬底(106)且在该半导体衬底上制造栅极堆栈(146)。在该半导体衬底内形成对准该栅极堆栈的杂质掺杂区(116)。制造延伸自该杂质掺杂区的相邻触点鳍(186)且在该触点鳍上形成金属硅化物层(126)。对至少一个该触点鳍上的该金属硅化物层的至少一部分制造触点(122)。

Description

具有较低接触电阻的MOS结构及其制造方法
技术领域
本发明一般系关于MOS结构及其制法，且尤系关于具有较低接触电阻的MOS结构及其制法。
背景技术
现今多数集成电路(IC)系使用复数个互连的场效晶体管(field effecttransistors，简称FET)来实现，该场效晶体管也称做金属氧化半导体场效晶体管(MOSFET或MOS晶体管)。MOS晶体管系包括覆盖形成在半导体衬底上的如控制电极的栅极电极(gate electrode)，以及形成在该半导体衬底内电流可流动于其间的间隔分开的源极(source)与汲极区(drain region)。施加至该栅极电极的控制电压系控制经过该半导体衬底中在该源极与汲极之间且在该栅极电极下的电流的流动。
藉由典型形成在两个MOS晶体管的栅极电极之间的源极/汲极区上的导电触点(conductive contact)来存取MOS晶体管。通常藉由在该源极/汲极区上沉积绝缘层并在该绝缘层中蚀刻接触开口来形成该导电触点。典型为氮化钛(titanium nitride)和/或其它金属与合金的薄阻障层系沉积在该触点开口中，然后该开口利用化学蒸气所沉积的钨层填充。
在单一IC芯片上加入更多电路系为持续的趋势。为了加入所增加的电路数量，在该电路中的每个个别装置的尺寸与在装置组件之间的尺寸和间隔必须减小。然而，在持续缩小整合之半导体装置中的其中一个限制因素是触点对已掺杂区域(doped region)(例如MOS晶体管的源极与汲极区)的电阻。当装置尺寸减小时，该触点的宽度减小。当该触点的宽度减小时，该触点的电阻变成愈来愈大。接着，随着该触点的电阻增加，该装置的驱动电流减少，因此不利地影响装置的效能。
因此，期望提供具有较低接触电阻的MOS结构。此外，期望提供用以制造具有较低接触电阻的MOS结构的方法。再者，从以下本发明的实施方式和所附加的申请专利范围，并配合所附加的图式与本发明的先前技术，将更清楚地了解本发明之其它令人满意的特征和特性。
发明内容
依照本发明的例示实施例，本发明提供一种制造MOS结构的方法。该方法包括提供半导体衬底与在该半导体衬底上制造栅极堆栈(gate stack)。在对准该栅极堆栈的该半导体衬底内形成杂质掺杂(impurity-doped)区。制造从该杂质掺杂区延伸的相邻触点鳍(contact fin)且在该触点鳍上形成金属硅化物层。在至少一个该触点鳍上对该金属硅化物层之至少一部分形成触点。
依照本发明的另一例示实施例，本发明提供一种制造MOS结构的方法。该方法包括提供半导体衬底与在该半导体衬底上制造栅极堆栈的步骤。使用该栅极堆栈作为掩膜，在设置在该栅极堆栈附近的半导体材料中注入杂质掺杂物。该半导体材料具有第一表面。在该半导体材料中蚀刻沟槽，俾使该半导体材料在该沟槽内具有沟槽表面。在该半导体材料的该第一表面上与该沟槽表面上形成金属硅化物层。对在该第一表面上的该金属硅化物层之至少一部分与在该沟槽表面上的该金属硅化物层之至少一部分形成触点。
依照本发明的例示实施例，本发明提供一种MOS结构。该MOS结构包括半导体衬底、形成在该半导体衬底上的栅极堆栈、以及设置在该半导体衬底内与与该栅极堆栈自行对准(self-aligned)的杂质掺杂区。两个相邻的触点鳍系设置在该杂质掺杂区上且金属硅化物层覆盖在该两个相邻的触点鳍上。导电触点在该两个相邻的触点鳍的至少其中一个的至少一个侧壁上系延伸至该金属硅化物层之至少一部分。该导电触点系经由该两个相邻的触点鳍的至少其中一个与该栅极堆栈电性连接。
依照本发明的另一例示实施例，本发明提供一种MOS结构。该MOS结构包括半导体衬底、形成在该半导体衬底上的栅极堆栈、以及设置在该栅极堆栈附近的杂质掺杂的半导体材料。该杂质掺杂的半导体材料具有第一表面。在该杂质掺杂的半导体材料内至少部分地设置沟槽。该杂质掺杂的半导体材料系在该沟槽内具有沟槽表面。金属硅化物层系设置在该第一表面上和该沟槽表面上，且导电触点系延伸至在该第一表面上的该金属硅化物层之至少一部分与在该沟槽表面上的该金属硅化物层之至少一部分。
附图说明
本发明在上文中结合下列附图来描述，其中，相似的组件符号代表相似的组件，且其中：
图1至图20系图示依照本发明的例示实施例的用以制造MOS结构的方法的剖视图；
图21至图25系图示依照本发明的另一例示实施例的用以制造MOS结构的方法的剖视图；
图26系图示依照本发明的又一例示实施例的用以制造MOS结构的方法的剖视图；
图27系图示依照本发明的另一例示实施例的用以制造MOS结构的方法的剖视图；以及
图28系为具有两个MOS晶体管以及与该两个MOS晶体管电性连接的导电触点的传统MOS结构的剖视图。
具体实施方式
下列的实施方式在本质上仅作为例示用，而并不是为了限制本发明或本发明之应用与用途。此外，并不打算受上述先前技术或下列实施方式中所提出的任何理论所限制。
图16系为依照本发明的例示实施例的MOS结构100的剖视图。MOS结构100系图标具有第一MOS晶体管102和第二MOS晶体管104。虽然术语「MOS晶体管」严格来说指的是具有金属栅极电极和氧化物栅极绝缘体的装置，但该术语在本文全文中将用来代表包含导电栅极电极(不论是金属或其它导电材料)的任何半导体装置，该导电栅极电极系置于栅极绝缘体(不论氧化物或其它绝缘体)之上，该栅极绝缘体系依次置于半导体衬底之上。MOS晶体管102和104可为PMOS晶体管或NMOS晶体管。虽然半导体装置100系只图标有两个MOS晶体管，但要了解的是，半导体装置100可具有任何数量的NMOS晶体管和/或PMOS晶体管。熟知此技艺之人士将了解，装置100可依需要而包含大量此种晶体管以实现想要的电路功能。
MOS晶体管102和104系制造在半导体衬底106上，该半导体衬底106可以是如图示的基体硅晶圆(bulk silicon wafer)或是薄的绝缘衬底上覆硅(silicon layer on an insulating，简称SOI)。该半导体衬底106之至少一部分108系掺杂有用于制造NMOS晶体管的P型导电性决定(conductivity-determining)杂质或掺杂有用于制造PMOS晶体管的N型导电性决定杂质。部分108可例如藉由例如硼(boron)或砷(arsenic)之掺杂物离子(dopant ion)的注入与后续的热退火(thermal annealing)来进行杂质掺杂。
每个MOS晶体管102和104包含形成在该半导体衬底106的表面112处的栅极绝缘体110。栅极电极114覆盖在该栅极绝缘体110上。该栅极电极114可由多晶硅或例如金属的其它导电材料来形成。源极和汲极延伸部116与较深的源极和汲极区118系设置在硅衬底106内且由设置在该硅衬底106内的该栅极电极114下的通道区120所分隔。
MOS结构100也包括形成在介电层124内的导电触点122，该介电层124覆盖MOS晶体管102和104。该导电触点122系设置在金属硅化物层126上且与该金属硅化物层126电性连接，该金属硅化物层126系至少部分设置在该金属硅化物层126和该触点122之间增加界面的特征上。在本实施例中，该特征包括两个相邻的独立的触点鳍186。触点鳍186系设置在衬底106的表面112上且从表面112延伸或突伸一段由双箭头136所指出的高度。图28系为具有形成在半导体衬底106的表面112上的金属硅化物层126的传统MOS结构的剖视图。暂时参照图16和图28，虽然以双箭头134来图示的触点122的宽度系可小些，但是触点鳍186和设置于其上的金属硅化物层126所提供具有触点122的界面130(图16)，其会大于衬底106的该部分之表面112的界面132(图28)，其中金属硅化物层126并不具有触点鳍186置于其上。具体来说，该界面132具有相等于该触点的宽W(134)乘以垂直长度L(未图示)的面积，也就是LxW(134)。相对地，在本发明的一个实施例中，该界面130系相等于该鳍186的宽度W(134)与4倍该高度H(136)的总和乘以长度L，也就是Lx(W(134)+4H(136))。该界面的该表面积的增加导致在该导电触点122和该源极/汲极区118之间的接触电阻降低，且因此增加装置的效能。
依照本发明的例示实施例，图1至图16系图示用以形成例如图16的MOS结构100的MOS结构的方法的剖视图。制造MOS组件的许多步骤是习知的，因此为了简洁，许多传统步骤在此将只简短地提到或将完全省略且不提供习知的制程细节。
参照图1，该方法起初在半导体衬底106上形成栅极绝缘体材料140。该半导体衬底系较佳为硅衬底，其中，在此使用的该术语「硅衬底」系包含典型使用在半导体工业中相当纯的硅材料以及混合有例如锗(germanium)、碳(carbon)等等的其它元素的硅。或者，该半导体衬底可为锗、砷化镓(gallium arsenide)、或其它半导体材料。为了方便但不以为限，该半导体衬底在下文中将称作硅衬底。该硅衬底可以是基体硅晶圆、或可为薄的绝缘层上覆硅(通常习知为绝缘体上覆硅(silicon-on-insulator)或SOI)，其依次由承载晶圆(carrier wafer)来支撑。该硅衬底的至少一表面108系藉由例如分别用以制造P-信道(PMOS)晶体管和N-通道(NMOS)晶体管的N型井区(well region)和P型井区来进行杂质掺杂。
在传统处理中，该栅极绝缘材料层140可为热生长的二氧化硅层，或者(如图示)可以是例如氧化硅、氮化硅等等的沉积绝缘体。沉积绝缘体可例如藉由化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、或电浆加强化学气相沈积(PECVD)来予以沉积。栅极绝缘体层140较佳具有约1至10nm的厚度，但实际厚度可依据所要实现的电路中的晶体管的应用来决定。
栅极电极材料层142系形成覆盖在该栅极绝缘材料140上。依据本发明的一个实施例，该栅极电极材料系为多晶硅。该多晶硅层系较佳沉积为未掺杂的多晶硅且后续藉由离子注入来进行杂质掺杂。该多晶硅系可藉由LPCVD中硅烷(silane)的氢还原(hydrogen reduction)来予以沉积。例如氮化硅或氮氧化硅的硬掩膜材料层(layer of hard maskmaterial)144可沉积在多晶硅的表面上。该硬掩膜材料也可藉由LPCVD来沉积至约50nm的厚度。或者，能了解到可在该多晶硅的表面上沉积光阻(photoresist)来取代该硬掩膜材料。
该硬掩膜层144系以光微影(photolithographically)的方式图案化，然后蚀刻下面的栅极电极材料层142与该栅极绝缘材料层140以形成栅极堆栈146，每个该栅极堆栈146具有栅极绝缘体110和栅极电极114，如图2所示。该多晶硅系可藉由例如使用Cl-或HBr/O2化学物质的反应式离子蚀刻(reactive ion etching，简称RIE)来蚀刻成想要的图案，而该硬掩膜与栅极绝缘材料系可藉由例如使用CHF3、CF4、或SF6化学物质的RIE来蚀刻。藉由使该栅极电极114在氧化环境中受到高温而在栅极堆栈146的侧壁150附近形成再氧化侧壁间隔体(reoxidationsidewall spacer)148。该再氧化侧壁间隔体148具有例如约3至4nm的厚度。在形成该再氧化间隔体148的过程中，也将氧化在表面112处之衬底106的外露部分138。
在形成该再氧化侧壁间隔体148后，介电材料的覆盖层(blanketlayer)152系沉积覆盖于MOS结构100上，如图3所示。该介电材料层系可包括例如二氧化硅。如上所述系非等向性(anisotropically)地蚀刻该介电材料层152以形成第二间隔体154，其通常视作相邻于该再氧化侧壁间隔体148的补偿间隔体(offset spacer)，如图4所示。衬底106的氧化部分138也可在此时被去除。该补偿间隔体具有例如约10至约20nm的厚度。该再氧化间隔体148和该补偿间隔体154系连同该栅极堆栈146一起来使用作为用以形成源极和汲极延伸部116的离子注入掩膜。藉由使用该栅极堆栈146与该间隔体148和154作为离子注入掩膜，该源极和汲极延伸部系与该栅极堆栈和该间隔体自行对准。该源极和汲极延伸部系藉由以已知方式适当地杂质掺杂硅衬底106来形成，例如藉由掺杂物离子的离子注入，如箭头156所示，以及后续的热退火。对于N通道MOS晶体管，该源极和汲极延伸部116系较佳以注入砷离子来形成，但也可使用磷离子。对于P通道MOS晶体管，该源极和汲极延伸部116系较佳以注入硼离子来形成。
参照图5，例如氮化硅或氮氧化硅的介电材料的覆盖层158系沉积覆盖在MOS结构100上。该介电材料层158之后被非等向性蚀刻，例如藉由使用CHF3、CF4、或SF6化学物质的RIE，以形成相邻于补偿间隔体154所设置的额外间隔体160，如图6所示。虽然栅极堆栈146系图标有再氧化侧壁间隔体148、补偿间隔体154、和额外间隔体160，但要了解的是，栅极堆栈146可具有含有任何组成之任何数量的间隔体，而该组成系适合所需之电路应用或设计。
参照图7，较佳为二氧化硅层的覆盖介电材料层164系沉积覆盖在MOS结构100上。该介电材料层164系沉积成约20至50nm的厚度。敷设并图案化光阻层166以掩膜栅极堆栈146并外露介电材料层164之一部分168，该部分168系设置在半导体衬底106的表面112上并且覆盖源极和汲极延伸部116上。该介电材料层164的该外露部分168之后藉由使用CHF3、CF4、或SF6化学物质的RIE蚀刻来去除以外露半导体衬底106的表面112，如图8所示。该光阻接着可以传统方法去除。
依照本发明的例示实施例，本方法接着在该外露硅表面112上外延生长硅层170，如图9所示。该外延硅层170可藉由在HCL存在下硅烷(SiH4)或二氯硅烷(dichlorosilane)(SiH2Cl2)的还原来生成。氯(chlorine)源的存在会促进生长的选择性本质，也就是，该外延硅相对于生长在该二氧化硅164上是优先生长在该外露硅表面112上。该外延硅层170可包括相当纯的硅材料或可包括混合例如锗、碳等等其它元素的硅。该外延硅层170系可生长至特定装置设计或应用所需的任何厚度。在例示的实施例中，该外延硅层170系生长至约10至约50nm的范围的厚度。
参照图10，在一个例示实施例中，在硅层170的外延生长之后，该栅极堆栈146、该再氧化侧壁间隔体148、该补偿间隔体154、额外间隔体160、和介电材料层164系使用作为离子注入掩膜以形成在硅衬底106中的源极和汲极区118，因而形成MOS晶体管102和104。该源极和汲极区系以已知方式而适当地杂质掺杂硅衬底106来形成，例如藉由掺杂物离子的离子注入，如箭头162所示，以及后续的热退火。对于N通道MOS晶体管，该源极和汲极区118系较佳藉由注入砷离子来形成，但也可使用磷离子。对于P通道MOS晶体管，该源极和汲极区118系较佳藉由注入硼离子来形成。在形成该源极和汲极区118的过程中，外延硅层170系也藉由掺杂物离子162的注入以进行杂质掺杂。
将了解的是，虽然上述方法系图示为该源极和汲极延伸部116系在该外延硅层170的生长之前形成，而该源极和汲极区118系在该外延硅层170的生长之后形成，但是该延伸部和该区两者皆可在该外延硅层的生长之后形成，例如当有足够低的热预算时，如图17至图20所示。依据本发明的例示实施例，在如图2所示形成该再氧化侧壁间隔体148之后，例如二氧化硅的介电材料的覆盖层(未图示)系沉积覆盖在MOS结构100上。在该介电材料层上系形成并图案化光阻(未图示)，然后蚀刻该介电材料层，如上所述，以形成相邻该再氧化侧壁间隔体148并外露在栅极堆栈146之间的衬底106的可弃式(disposable)间隔层190，如图17所示。该可弃式间隔层190具有实质上相等于该补偿间隔体154和相邻额外间隔体160的厚度总和的厚度。该外露半导体衬底106之后例如藉由使用HBr/O2和Cl化学物质的RIE来蚀刻以形成沟槽192于其中。在一个例示实施例中，该沟槽具有约30至约50nm的深度。
在形成该沟槽192之后，在沟槽192内外延生长硅层194，如图18所示。该外延硅层194可使用如上所述例如用以生长该外延硅层170的制程来生长。该外延硅层194可包括相当纯的硅材料或可包括混合例如锗、碳、与相似物(例如引入应力至该半导体衬底106内者)的其它元素的硅。该外延硅层194系可生长至特定装置设计或应用所需的任何厚度。在例示实施例中，该外延硅层194系可生长至例如约40至约70nm的厚度。藉由例如使用CHF3、CF4、或SF6化学物质的RIE来蚀刻、或在例如稀释HF的湿式蚀刻液以去除可弃式间隔层190来外露部分之衬底106。参照图19，可如上述地形成补偿间隔体154。在形成补偿间隔体154之后，连同该栅极堆栈146一起使用该再氧化间隔体148和该补偿间隔体154作为用以形成在外延硅层194内的源极和汲极延伸部116和衬底106的外露部分的离子注入掩膜。藉由使用该栅极堆栈146与该间隔体148和154作为离子注入掩膜，该源极和汲极延伸部系与该栅极堆栈和该间隔体自行对准。该源极和汲极延伸部可藉由上述的制程来形成，例如藉由掺杂物离子156的离子注入。
参照图20，在形成该源极和汲极延伸部116之后，可如上述地制造额外间隔体160以填充去除间隔体190所造成的间隙。要注意的是，因为可弃式间隔层190系使用来防止外延硅生长在栅极电极114上，所以在此实施例中不需要介电层164。该栅极堆栈146、该再氧化侧壁间隔体148、该补偿间隔体154、和额外间隔体160系使用作为离子注入掩膜以在外延硅层194内和硅衬底106中形成深的源极和汲极区118，因而形成MOS晶体管102和104。可如上述地例如藉由掺杂物162的离子注入来制造该源极和汲极区。要了解的是，该源极和汲极延伸部与区系也可形成在本方法的各种其它步骤之前或之后。例如，该源极和汲极延伸部与区两者皆可在该外延硅层的生长之前形成，但在该外延硅层生长后再注入掺杂物离子可能比较好。
不管该源极和汲极区与延伸部是何时形成，依据本发明的例示实施例，本方法接着在MOS结构100上沉积较佳为二氧化硅层的介电材料层172，如图11所示。该介电材料层172系沉积至例如约20至约50nm的厚度。敷设并图案化光阻层(未图示)且介电材料层172的该外露部分之后藉由例如使用CHF3、CF4、或SF6化学物质的RIE蚀刻来去除以在外延硅层170上形成柱体174，如图12所示。之后可用传统方法去除该光阻。具有不同于柱体174的蚀刻特性的另一介电材料层176系沉积覆盖在MOS结构100上。例如，当柱体174由氧化硅形成时，层176系可包括氮化硅。该介电材料层176系沉积至例如约40至约80nm的厚度。
该介电材料层176之后经过非等向性地蚀刻，例如使用CHF3、CF4、或SF6化学物质的RIE，以形成设置在柱体174附近和栅极堆栈146附近的间隔体178，如图13所示。之后蚀刻该柱体174，留下孤立的(free-standing)间隔体178在外延硅层170上，如图14所示。在蚀刻柱体174的过程中也可蚀刻外露的介电层164之至少一部分。
参照图15，利用间隔体178作为蚀刻掩膜来蚀刻外延硅层170之外露部分以形成设置在衬底106的表面112上的鳍128。鳍128包含两个触点鳍186，该两个触点鳍186各为设置在栅极堆栈146之间的个别独立的鳍。该外延硅层170藉由例如使用HBr/O2和Cl化学物质的反应式离子蚀刻来蚀刻。如果没有如上述参照图10地形成，则源极和汲极区118之后可藉由适当地杂质掺杂硅衬底106来形成，如上所述。在形成该源极和汲极区118的过程中，也掺杂鳍128。于MOS结构100上沉积硅化物形成金属(silicide-forming metal)的覆盖层180。例如藉由RTA以加热该硅化物形成金属层180来鳍128上和在衬底106的表面112上形成金属硅化物层126，如图16所示。该硅化物形成金属可为例如钴(cobalt)、镍、铼(rhenium)、或钯(palladium)、或上述金属的合金。可沉积该硅化物形成金属，例如藉由溅镀至约5至50nm的厚度且较佳为约1nm的厚度。没有与外露硅接触的任何硅化物形成金属，例如沉积在介电层164上的该硅化物形成金属，其在该RTA过程中不会反应以形成硅化物，并且之后可藉由H2O2/H2SO4或HNO3/HCL溶液的湿式蚀刻来去除。在形成该金属硅化物层之后，在该MOS晶体管102和104与鳍128上沉积介电材料层124。依据本发明的例示实施例，本方法接着图案化并蚀刻该介电材料层124以形成延伸通过介电材料层124并外露在触点鳍186上和在衬底106的表面112上该金属硅化物层126的至少一部分的触点开口182。该介电材料层可在图案化前藉由CMP制程进行平坦化。在一个例示实施例中，设置在一个鳍186的一个侧壁184上的至少该部分的该金属硅化物层126是外露的。在本发明的另一例示实施例中，设置在两个触点鳍186的两个侧壁184上的至少该部分的该金属硅化物层126是外露的。在接触开口182中形成导电触点122，俾使该源极和汲极区可适当地电性连接至该集成电路中的其它装置以实现所想要的电路功能。在本发明的例示实施例中，导电触点122系藉由在触点开口180内沉积例如TiN(未图示)的薄第一阻障层与例如钛的薄第二阻障层(未图示)，接着沉积例如W的导电栓(conductive plug)而形成。该阻障层系用来防止在形成该导电栓过程中所使用的六氟钨(tungsten hexafluoride)WF6扩散进入该介电材料层124中以及用来强化该导电栓对该接触开口壁的黏着力。要了解的是，可使用其它层以形成导电触点122。例如，在形成该阻障层之前可沉积钽(tantalum)层。在本发明的例示实施例中，该触点122的宽度134足够大且该触点122相对于该触点鳍186来放置，俾使触点122与至少一个该触点鳍186的至少一个该侧壁184上的该金属硅化物层126物理接触。因此，界面130系大于宽度134，也就是，大于界面132(图28的)，该界面132系位于触点122与金属硅化物层126所位在而不具触点鳍186的衬底106的该部分表面112之间。因此，如上述地，在触点122和该金属硅化物126之间所增加的界面系导致接触电阻的减少，然后造成装置效能的增加。
图21至图25系图示依据本发明的另一例示实施例的用以制造MOS结构200的方法的剖视图。图示在图21至图25的该方法相似于图示在图1至图16的该方法之处系在于其也形成增加在该触点和该源极和汲极区之间的该界面的表面积的特征。然而，相对于鳍，在图示在图21至图25的方法过程中所形成的特征系为沟槽。
因此，本方法一开始是图示在图1至图10的步骤，且在掺杂外延硅层170后，例如氧化硅或较佳为氮化硅的介电材料共形层(conformallayer)202系沉积覆盖在MOS结构200上，如图21所示。介电材料层202可沉积至例如约15至约50nm的厚度。如上述地经过非等向性蚀刻层202以形成栅极堆栈146附近的可弃式间隔体204，如图22所示。
参照图23，把可弃式间隔体204和栅极堆栈146当作蚀刻掩膜来蚀刻外延硅层170以形成沟槽206。在本发明的一个例示实施例中，沟槽206终止在外延硅层170内。之后可藉由例如使用湿式清洁步骤或使用对于该外延硅层170和该硅衬底106是高选择性的非等向性蚀刻来去除可弃式间隔体204。硅化物形成金属的覆盖层180系沉积覆盖在MOS结构200上，如图24所示。例如藉由RTA以加热该硅化物形成金属层180来在外延硅层170上和沟槽206内形成金属硅化物层126，如图25所示。
在形成该金属硅化物层后，介电材料层124系沉积覆盖在MOS结构200上。图案化与蚀刻该介电材料层124以形成延伸通过介电材料层124并外露在外延硅层170上的该金属硅化物层126的触点开口182。导电触点122之后形成在触点开口182中，如上所述。在本发明的例示实施例中，该触点122系够宽，且相对于MOS晶体管102和104而放置，俾使触点122的至少一个侧壁212系终止在金属硅化外延硅层170的顶表面208处，而不是沟槽206内的沟槽表面210上。因此，在该导电触点122和该金属硅化物层126之间的该界面130系大于图28的该界面132至少该侧壁212中由双箭头214指出的高度。因此，增加的界面导致接触电阻的减少，且因此增加了装置效能。在本发明的较佳实施例中，该触点122系够宽且相对于MOS晶体管102和104而放置，俾使触点122的两个侧壁212都终止在金属硅化外延硅层170的顶表面208处，而不是沟槽206内的沟槽表面210上。
在本发明的另一例示实施例中，如图26所示，沟槽206延伸通过外延硅层170并终止在源极/汲极区118内。因此，由于该沟槽的深度增加，在该触点122和该金属硅化物126之间的该界面系甚至更大。在本发明的又另一例示实施例中，如图27所示，外延硅层170不存在且沟槽206从衬底106的表面112延伸且终止在源极/汲极区118内。因此，消除了外延生长硅层170的步骤，因此增加了制造装置的速度。
因此，本发明提供具有较低接触电阻的MOS结构。该MOS结构包括允许该界面的表面积增加的特征，该界面系位于导电触点和金属硅化物层之间且电性耦合至MOS装置的源极和汲极区。因为该接触电阻系大部分起因于在该触点和该金属硅化物层的该界面的该阻障层材料(例如，因为TiN/Ti阻障层组合的电阻系远大于钨触点的电阻)，增加该界面面积系导致接触电阻的有效降低。
虽然已在本发明的前面实施方式提出至少一个例示实施例，但应该了解到还存在有许多变化形式。也应该了解的是，该例示实施例系只是范例，并不是要以任何方式来限制本发明的范围、应用性、或组构。反而是，前面的实施方式将提供熟知此技艺之人士用以实现本发明的例示实施例的方便的准则，要了解的是，可在没有偏离所附申请专利范围与他们的法律相等物的本发明的范畴下，针对在例示实施例中所述之组件的功能与配置作不同改变。

Claims (3)

1.一种制造MOS结构(100)的方法，该方法包括下列步骤：
提供半导体衬底(106)；
在该半导体衬底上，制造栅极堆栈(146)；
在该半导体衬底内，形成对准该栅极堆栈的杂质掺杂区(116)；
外延生长含硅材料(170)覆盖在该半导体衬底(106)上；
蚀刻该外延生长含硅材料，以在该半导体衬底上形成两个相邻触点鳍(186)，其中，蚀刻该外延生长含硅材料(170)的步骤包括下列步骤：
在该外延生长含硅材料上，沉积第一介电材料层(172)；
蚀刻该第一介电材料层，以在该外延生长含硅材料上形成柱体(174)；
在该外延生长含硅材料和该柱体上，沉积第二介电材料层(176)；
蚀刻该第二介电材料层，以形成该柱体附近的间隔体(178)；去除该柱体；以及
使用该间隔体作为蚀刻掩膜，以蚀刻该外延生长含硅材料；
在该触点鳍上，形成金属硅化物层(126)；以及
对至少一个该触点鳍上的该金属硅化物层的至少一部分制造触点(122)。
2.如权利要求1所述的方法，其中，制造触点(122)的步骤包括制造该触点，使得该触点的宽度(134)足够大，且该触点相对于该相邻触点鳍(186)而放置，以使该触点在至少一个该触点鳍的至少一个侧壁上与该金属硅化物层(126)物理接触。
3.如权利要求1所述的方法，其中，制造触点(122)的步骤包括制造该触点，使得该触点的宽度(134)足够大且该触点相对于该相邻触点鳍(186)而放置，以使该触点和该金属硅化物层(126)之间的界面(130)大于该触点的宽度(134)。
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KR20100059882A (ko) 2010-06-04
CN101836282A (zh) 2010-09-15
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JP2010537425A (ja) 2010-12-02

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