CN101834182A

CN101834182A - Grid coupling NMOS (Negative-channel Metal-Oxide Semiconductor) tube modulated by dynamic grid resistance

Info

Publication number: CN101834182A
Application number: CN 201010130843
Authority: CN
Inventors: 宋波; 韩雁; 董树荣; 马飞; 黄大海; 李明亮; 苗萌
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2010-03-23
Filing date: 2010-03-23
Publication date: 2010-09-15
Anticipated expiration: 2030-03-23
Also published as: CN101834182B

Abstract

The invention discloses a grid coupling NMOS (Negative-channel Metal-Oxide Semiconductor) tube modulated by a dynamic grid resistance, which is used for the ESD (Electro-Static Discharge) protection of a core circuit. The invention adopts the structure that a drain electrode is connected to the input terminal of the core circuit, a source electrode and a substrate are grounded directly, and a grid electrode is connected in parallel with a resistance through a GCNMOS tube of which the resistance is grounded; the drain electrode is connected to the grid electrode of the GCNMOS tube, the source electrode and the substrate are grounded, and the grid electrode is connected to the NMOS tube of a VDD power cord of the core circuit. By adding a small NMOS to the grid, the invention adopts VDD as the control signal of the NMOS, which enhances the robustness of components by opening multi-finger GGNMOS evenly and solves the problem of poor protection when the GCNMOS structure can not be used for input terminals with higher signal frequency. Therefore, the simple and effective ESD protection proposal can be widely used in many fields.

Description

A kind of gate coupled NMOS pipe of dynamic gate resistance modulation

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of gate coupled NMOS pipe of dynamic gate resistance modulation.

Background technology

Electrostatic Discharge is under the situation of an integrated circuit suspension joint, and a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, the about 100ns consuming time of whole process; And gathered electric charge in inside because friction waits in the integrated circuit, the charge discharging resisting of inside is to the process on ground when certain pin ground connection of integrated circuit.The about about 1.5ns consuming time of this process.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very essential with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic discharge protection circuit to release.

The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.

Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode; controllable silicon (silicon controlled rectifier SCR); GGNMOS (Grounded Gate NMOS; the metal-oxide-semiconductor of grounded-grid), wherein the metal-oxide-semiconductor of grounded-grid (GGNMOS) is widely adopted.The protection circuit of this device as shown in Figure 1, I/O end (I/O) is received in the drain electrode 12 of GGNMOS, grid 13, source electrode 14 and substrate 11 all receive ground.For improving the resistance ESD ability of GGNMOS, the general many interdigital structures that adopt as shown in Figure 2.But this how interdigital GGNMOS structure is because middle interdigital volume resistance maximum prior to other interdigital unlatchings, causes each interdigital can not evenly unlatching of GGNMOS.Cause the decline of the antistatic capacity of integrated circuit like this.

Be directed to this, a kind of effective solution is exactly to raise gate voltage by the gate coupled voltage technology that the RC circuit is realized to make the even conducting of device.In order to reduce electric capacity, can remove the capacitor C in the RC circuit, grid parasitic capacitance with NMOS pipe M1 substitutes, on grid, meet a big resistance R g (resistance is generally 10k Ω～50k Ω) to ground, realize the coupling of gate voltage, be also referred to as gate voltage coupling NMOS pipe (GCNMOS) as shown in Figure 3.Because the simple quilt of this method adopts widely.

But this structure is when the signal frequency of protection input is higher; be that the rising edge time phase difference of pulse of rising edge time of signal and ESD is when little; just might when normally importing, trigger input signal the ESD safeguard structure; thereby cause false triggering to influence the operate as normal of chip, make the application of this simple and effective protectiving scheme be subjected to serious restriction.

Summary of the invention

The invention provides a kind of gate coupled NMOS pipe circuit of dynamic gate resistance modulation, solved when frequency input signal is higher, the problem of false triggering can appear in existing gate coupled NMOS pipe.

A kind of gate coupled NMOS pipe of dynamic gate resistance modulation is used for the ESD protection of core circuit, comprising:

One GCNMOS pipe, drain electrode connects the input of core circuit, the direct ground connection of source electrode and substrate, grid is by a grounding through resistance;

One NMOS pipe, in parallel with resistance, drain electrode connects the grid of GCNMOS pipe, source electrode and substrate ground connection, grid connects the VDD power line of core circuit.

Preferably, described resistance sizes is 10～50k Ω.

Compare with existing GCNMOS; the present invention is by adding a little NMOS on grid; with the control signal of VDD as this NMOS; can make how interdigital GGNMOS evenly open; improve the robustness of device, solved the protection problem that the GCNMOS structure can not be used for the input of higher signal frequencies simultaneously.Make that the accommodation of this simple and effective ESD protectiving scheme is effectively expanded.

Description of drawings

Fig. 1 is existing GGNMOS circuit theory schematic diagram;

Fig. 2 is the realization domain of existing how interdigital GGNMOS;

Fig. 3 is the circuit theory diagrams of existing gate coupled NMOS (GCNMOS);

Fig. 4 is the circuit theory diagrams of gate coupled NMOS of the present invention.

Embodiment

As shown in Figure 4, a kind of gate coupled NMOS pipe of dynamic gate resistance modulation is used for the ESD protection of core circuit, comprising:

One GCNMOS manages M1, and drain electrode connects the input of core circuit, source electrode and the direct ground connection of substrate ground connection, and grid is by resistance R g ground connection, and the resistance of resistance R g is generally 10～50k Ω.

One NMOS manages M2, and g is in parallel with resistance R, and drain electrode connects the grid of GCNMOS pipe M1, source electrode and substrate ground connection, and grid connects the VDD power line of core circuit.

The operation principle of foregoing circuit is as follows:

Under normal operation, vdd terminal is a high potential, and this moment, NMOS pipe M2 opened conducting, and the resistance when NMOS pipe M2 opens is very little, and after the bigger resistance R g of resistance value was in parallel, the resistance value Rg (eq) on the GCNMOS pipe M1 grid was about the conduction resistance value of NMOS pipe M1.

When the electrostatic signal of danger was come in from input Input, the input Input of core circuit was to the path that does not have other between the VDD, and VDD is floating dummy status.Because VDD is to the effect of the coupling capacitance on GND ground, VDD can be coupled to ground, thereby NMOS pipe M2 grid is an electronegative potential, NMOS pipe M2 is in off state, its resistance value is very big, is about the M Ω order of magnitude, much larger than the resistance of resistance R g, after resistance R g was in parallel, the resistance value Rg (eq) on the GGNMOS pipe M1 grid approximated the resistance of resistance R g.

Rg under the ESD situation (eq) is bigger, and corresponding RC constant value is bigger, makes the device ESD electric current of fully opening and effectively release, the safety of protection internal circuit.And in normal working conditions, Rg (eq) is less, and corresponding RC time constant value is less, and the input signal of rising edge can not make protective device generation false triggering faster, thereby does not disturb the operate as normal of internal circuit.Make foregoing circuit can be adapted to the esd protection under the frequency input signal condition with higher.

Claims

1. the gate coupled NMOS pipe of a dynamic gate resistance modulation is used for the ESD protection of core circuit, it is characterized in that, comprising:

One GCNMOS manages (M1), and drain electrode connects the input of core circuit, the direct ground connection of source electrode and substrate, and grid is by a resistance (Rg) ground connection;

One NMOS manages (M2), and (Rg) is in parallel with resistance, and drain electrode connects the grid of GCNMOS pipe (M1), source electrode and substrate ground connection, and grid connects the VDD power line of core circuit.

2. gate coupled NMOS pipe circuit according to claim 1, it is characterized in that: described resistance sizes is 10～50k Ω.