CN101826506B - Packaging substrate and chip packaging construct - Google Patents
Packaging substrate and chip packaging construct Download PDFInfo
- Publication number
- CN101826506B CN101826506B CN2009101281285A CN200910128128A CN101826506B CN 101826506 B CN101826506 B CN 101826506B CN 2009101281285 A CN2009101281285 A CN 2009101281285A CN 200910128128 A CN200910128128 A CN 200910128128A CN 101826506 B CN101826506 B CN 101826506B
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- wire
- lead
- packaging
- base plate
- line segment
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 title abstract description 4
- 238000010276 construction Methods 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 20
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 5
- 238000005530 etching Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Abstract
The invention provides a packaging substrate for carrying a chip. The packaging substrate comprises a flexible dielectric layer and a conductive layer, wherein the conductive layer is arranged on the flexible dielectric layer and electrically connected with the chip and comprises a first lead wire and a second lead wire; the second lead wire is adjacent to the first lead wire and has a plane region; and the plane region comprises an adjacent region adjacent to the first lead wire, and the adjacent region is provided with at least one groove so that the adjacent region forms at least one sub-lead wire.
Description
Technical field
The invention relates to a kind of base plate for packaging and chip encapsulation construction, and especially, the invention relates to a kind of setting that can go up groove by lead-in wire, reducing goes between, and the base plate for packaging and the chip encapsulation construction of fracture take place when base plate for packaging bending and deflection.
Background technology
Along with the development and the consumer demand of information electronic product, the design that the electronic product escape is passing progressively tends to frivolous, miniaturization and deflection direction and develops.The pliability base plate for packaging has better flexural property compared to rigid substrate, and can supply the demand of higher pin number (pin count) joint and more flexible line configuring design is provided.Therefore, the pliability base plate for packaging is widely used, and its range of application comprises mobile phone, notebook, digital camera, e-book and LCD etc.
See also Fig. 1, Fig. 1 is the schematic diagram that illustrates pliability base plate for packaging 1 in the prior art.As shown in the figure, existing pliability base plate for packaging 1 comprises pliability dielectric layer 10 and conductive layer 12, and in order to carries chips 2.Conductive layer 12 comprises many first lead-in wires 120 and second lead-in wire 122.Generally speaking, first lead-in wire, 120 and second lead-in wire 122 can be electrically connected chip 2, and as the usefulness of signal transmission, ground connection or power delivery, and second lead-in wire 122 can further comprise plane area 1220.
Plane area 1220 belongs to the metal flat layer, and partly has bigger area than the line segment of first lead-in wire, 120 or second lead-in wire 122.Because metal is good conductor of heat, so plane area 1220 can effectively help the heat that dissipates, and in addition, the setting of plane area 1220 also can be used to fill up does not have the white space of laying lead-in wire in the conductive layer, with the intensity of reinforcement base plate for packaging.
Yet, because the width of plane area 1220 is big than the line segment part of first lead-in wire, 120 and second lead-in wire 122, therefore its stress distribution can be unequal when pliability base plate for packaging 1 is repeated to bend deflection, the intersection that causes contiguous wire widths to change, the i.e. phenomenon that relatively easily ruptures or be out of shape near the position of intersection on the line segment part intersection of the plane area 1220 and second lead-in wire 122 and first lead-in wire 120.In other words, even if existing pliability base plate for packaging 1 under normal operating position, still easily having damage may, and then make the electronic installation can't regular event.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of base plate for packaging, on the plane area of contiguous lead-in wire on the base plate for packaging, groove is set, by groove distributed plane district suffered stress when the deflection is set, and then reduce to go between the phenomenon of fracture take place when base plate for packaging bending deflection.
A kind of base plate for packaging is provided according to an aspect of the present invention, is in order to carries chips.Base plate for packaging comprises pliability dielectric layer and conductive layer.Conductive layer is arranged on the pliability dielectric layer and can be electrically connected chip.Conductive layer further comprises first lead-in wire and second lead-in wire.Second lead-in wire adjacent first goes between and has a plane area, and plane area then further comprises contiguous first lead-in wire of a proximity.At least one groove is set on the proximity makes proximity form at least one son lead-in wire.
Base plate for packaging according to a further aspect of the invention can comprise pliability dielectric layer and conductive layer, and wherein conductive layer is arranged on the pliability dielectric layer and can be electrically connected chip.Conductive layer can comprise a lead-in wire, the line segment district that lead-in wire then can have plane area and be connected with plane area.Plane area can comprise the contiguous line segment of proximity district, at least one groove then can further be set on the proximity make proximity form at least one son lead-in wire.
Provide a kind of chip encapsulation construction according to another aspect of the invention, comprise base plate for packaging and be carried on chip on the base plate for packaging, wherein, base plate for packaging can further comprise pliability dielectric layer and conductive layer.Conductive layer is arranged on the pliability dielectric layer, and further comprises first lead-in wire and second lead-in wire.Second lead-in wire is adjacent first lead-in wire and has plane area.Plane area comprises contiguous first lead-in wire of proximity, and at least one groove is set on the proximity makes proximity form at least one son lead-in wire.
A kind of chip encapsulation construction is provided according to a further aspect of the present invention, comprises base plate for packaging and be carried on chip on the base plate for packaging, wherein, base plate for packaging can further comprise pliability dielectric layer and conductive layer.Conductive layer is arranged on the pliability dielectric layer, and further comprises a lead-in wire.Have plane area and line segment district on the lead-in wire, plane area then comprises the contiguous line segment of proximity district.At least one groove is set on the proximity makes proximity form at least one son lead-in wire.
Comprehensively above-mentioned, base plate for packaging provided by the present invention and chip encapsulation construction, the zone that the line segment district of groove contiguous lead-in wire on the plane area of lead-in wire or adjacent legs can be set is suffered stress when crooked with average dispersion base plate for packaging deflection, and then reduce lead-in wire generation phenomenon of rupture, to promote number of times and the life-span that base plate for packaging is bent deflection.In addition, when etching work procedure formed lead-in wire and groove, the setting of groove also can form more consistent flow channel and flow comparatively smoothly for etching liquid, and then reduced the situation of specific region over etching.
Description of drawings
Can be about the advantages and spirit of the present invention by being further understood, wherein below in conjunction with the detailed description of accompanying drawing to preferred embodiment of the present invention:
Fig. 1 is the schematic diagram of pliability base plate for packaging in the prior art.
Fig. 2 is the schematic diagram according to the chip encapsulation construction of a specific embodiment of the present invention.
Fig. 3 is the schematic diagram according to the chip encapsulation construction of a specific embodiment of the present invention.
Embodiment
See also Fig. 2, Fig. 2 is the schematic diagram according to the chip encapsulation construction 7 of a specific embodiment of the present invention.As shown in the figure, chip encapsulation construction 7 of the present invention comprises base plate for packaging 3 and chip 4, and wherein, base plate for packaging 3 is in order to carries chips 4.In practice was used, base plate for packaging 3 can be looked actual demand a plurality of chips 4 are set.In addition, be to decide in the position of practice chips 4 according to user or designer's demand, be not limited to the cited specific embodiment of this specification.
Base plate for packaging 3 comprises pliability dielectric layer 30 and conductive layer 32.Conductive layer 32 is arranged on the pliability dielectric layer 30, and in order to be electrically connected to chip 4.Note that Fig. 2 is the part schematic diagram of pliability dielectric layer 30 and conductive layer 32, in practice, conductive layer 32 can cover whole pliability dielectric layer 30.Conductive layer 32 comprises first lead-in wire, 320 and second lead-in wire 322.First lead-in wire 320 has the first live width W1.In practice, be designed to many first lead-in wires 320 and second lead-in wire 322 on the base plate for packaging 3 usually, be used for transmitting signal, ground connection or power delivery, with (for example: communication bridge printed circuit board (PCB)) as chip and exterior electrical components.
Second lead-in wire, 322 adjacent first lead-in wire, 320, the second lead-in wires 322 have plane area 3220.In the practice, have a plurality of plane areas 3220 on the base plate for packaging 3, and plane area 3220 has the larger area metal level than first lead-in wire 320, normally be used for filling up and do not have the white space of laying lead-in wire in the conductive layer 32, intensity with reinforcement base plate for packaging 3, also can assist chip 4 heat radiation,, take place overheated and the phenomenon of fault to avoid chip 4 when the normal running.Plane area 3220 comprises contiguous first lead-in wire 320 of proximity N, and proximity N is provided with at least one groove 3222 and proximity N gone up form at least one son lead-in wire 3224, and wherein, son lead-in wire 3224 has the second live width W
2In practice, proximity N there is no fixed shape or size, need look the zone decision of physical plane district 3220 contiguous first lead-in wires 320, selects groove number and distribution again.Preferable, the second live width W
2Can be between 0.5 times the first live width W
1The first live width W with 10 times
1Between (0.5 W
1≤ W
2≤ 10 W
1), but the present invention is not as limit.
In addition, second lead-in wire 322 can have the line segment district in addition, and the line segment district is connected to plane area 3220, and the width in line segment district has notable difference less than width and both width of plane area 3220.One end in line segment district can be electrically connected to chip 4, makes 322 effects with signal transmission, ground connection or power delivery of second lead-in wire.Second lead-in wire 322 also can only comprise plane area 3220 and not be electrically connected chip, is a dummy pattern.In other words, on the same base plate for packaging 3, can occur second lead-in wire 322 of different shape simultaneously, and second lead-in wire 322 not necessarily needs to comprise the line segment district, need decide on actual design.
In this specific embodiment, parallel first lead-in wire 320 bearing of trends in the long limit of groove 3222 and extend to form cubic type slotted eye along parallel direction.Because suffered stress when the setting of groove 3222 can on average disperse base plate for packaging 3 bending deflections, the phenomenon of fracture or distortion takes place with plane area 3220 contiguous second lead-in wires 322 places that avoid first lead-in wire 320, therefore the shape of groove 3222 is not carried with present embodiment and being exceeded.
In practical application, it is to produce by etching mode that the proximity N of second lead-in wire 322 goes up formed at least one groove 3222.Can be about to first lead-in wire, 320, second lead-in wire 322 and groove 3220 forms in the lump by same etching work procedure at the operation initial stage, use reducing production costs and enhancing productivity.In addition, the setting of groove 3222 also can help etching liquid to flow comparatively smoothly when etching work procedure, and then reduces the situation of lead-in wire over etching.
See also Fig. 3, Fig. 3 is the schematic diagram according to the chip encapsulation construction 9 of a specific embodiment of the present invention.As shown in Figure 3, chip encapsulation construction 9 comprises base plate for packaging 5 and chip 6, and wherein, base plate for packaging 5 is in order to carries chips 6, and the quantity of chip 6 do not exceed with one, need use on actual design and decide.In addition, be to decide in the position of practice chips 6 according to user or designer's demand, be not limited to the cited specific embodiment of this specification.
Base plate for packaging 5 comprises pliability dielectric layer 50 and conductive layer 52.Conductive layer 52 is arranged on the pliability dielectric layer 50 and in order to being electrically connected chip 6, and conductive layer 52 comprises lead-in wire 520.Note that Fig. 3 is the part schematic diagram of pliability dielectric layer 50 and conductive layer 52, in practice, conductive layer 52 can cover whole pliability dielectric layer 50.Lead-in wire 520 has plane area 5200 and line segment district 5202.Line segment district 5202 connects plane areas 5200, and the width in line segment district 5202 has notable difference less than width and both width of plane area 5200.Plane area 5200 comprises the contiguous line segment of proximity N district 5202, and wherein, line segment district 5202 has the 3rd live width W
3Proximity N is provided with at least one groove 5204 makes this proximity N form at least one son lead-in wire 5206, and son lead-in wire 5206 has the 4th live width W
4In this embodiment, proximity N size and shape need be decided on practical application, again according to area size decision groove 5204 quantity and distribution.Preferable, the 4th live width W
4Can be between 0.5 times the 3rd live width W
3The 3rd live width W with 10 times
3Between (0.5 W
3≤ W
4≤ 10 W
3), but the present invention is not as limit.
In this specific embodiment, parallel line segment district 5202 bearing of trends in the long limit of groove 5204 and extend to form cubic type slotted eye along parallel direction.The width that the setting of groove 5204 can make proximity N is the width in convergence line segment district 5202 (the 3rd live width W comparatively
3), and then make lead-in wire 520 suffered stress when base plate for packaging 5 bending deflections more consistent, with avoid going between 520 in adjacent plane district 5200 and the intersection in line segment district 5202 phenomenon of fracture or distortion takes place.In addition, the shape of groove 5204 is a principle with the stand out distance that can reduce between line segment district 5202 and proximity N, is not carried with present embodiment and exceeding.
In practical application, the proximity N of lead-in wire 520 goes up formed groove 5204 and can produce by etching mode.In addition, groove 5204 can form by same etching work procedure in the lump with plane area 5200 and line segment district 5202, uses reducing production costs and enhancing productivity.
Comprehensively above-mentioned, base plate for packaging provided by the invention and chip encapsulation construction, by the line segment district place of groove in contiguous adjacent legs of the plane area of lead-in wire or lead-in wire is set, suffered stress during with average dispersion base plate for packaging deflection, and then prevent that lead-in wire from rupturing, to promote number of times and the life-span that base plate for packaging is bent deflection.In addition, the setting of groove also can help etching liquid to flow comparatively smoothly when etching work procedure, and then reduces the situation of lead-in wire over etching.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (14)
1. base plate for packaging, in order to carry a chip, this base plate for packaging comprises:
One pliability dielectric layer; And
One conductive layer is arranged on this pliability dielectric layer and is electrically connected this chip, and this conductive layer comprises:
One first lead-in wire; And
One second lead-in wire, adjacent this first lead-in wire, this second lead-in wire has a plane area, and this plane area has bigger area than this first lead-in wire, this plane area comprises contiguous this first lead-in wire of a proximity, and this proximity is provided with at least one groove and makes this proximity form at least one son lead-in wire.
2. base plate for packaging according to claim 1 is characterized in that, this first lead-in wire has one first live width, and this at least one son lead-in wire has one second live width, and this second live width is between 0.5 times of this first live width and 10 times of these first live widths.
3. base plate for packaging according to claim 1 is characterized in that, this at least one groove is the square slotted eye of parallel this first lead-in wire bearing of trend in long limit.
4. base plate for packaging according to claim 1 is characterized in that, this second lead-in wire has a line segment district in addition, and this line segment district connects this plane area.
5. base plate for packaging, in order to carry a chip, this base plate for packaging comprises:
One pliability dielectric layer; And
One conductive layer is arranged on this pliability dielectric layer and is electrically connected this chip, and this conductive layer comprises:
One lead-in wire, have a plane area and a line segment district, this line segment district connects this plane area, and the width in this line segment district is less than the width of this plane area, this plane area comprises contiguous this line segment district of a proximity, and this proximity is provided with at least one groove makes this proximity form at least one son lead-in wire.
6. base plate for packaging according to claim 5 is characterized in that, this line segment district has one first live width, and this at least one son lead-in wire has one second live width, and this second live width is between 0.5 times of this first live width and 10 times of these first live widths.
7. base plate for packaging according to claim 5 is characterized in that, this at least one groove is the square slotted eye of parallel this line segment district bearing of trend in long limit.
8. chip encapsulation construction comprises:
One base plate for packaging comprises:
One pliability dielectric layer; And
One conductive layer, be arranged on this pliability dielectric layer, this conductive layer further comprises one first lead-in wire and one second lead-in wire, adjacent this first lead-in wire of this second lead-in wire also has a plane area, this plane area has bigger area than this first lead-in wire, this plane area comprises contiguous this first lead-in wire of a proximity, and this proximity is provided with at least one groove and makes this proximity form at least one son lead-in wire; And
One chip is carried on this base plate for packaging, and is electrically connected this conductive layer.
9. chip encapsulation construction according to claim 8 is characterized in that, this first lead-in wire has one first live width, and this at least one son lead-in wire has one second live width, and this second live width is between 0.5 times of this first live width and 10 times of these first live widths.
10. chip encapsulation construction according to claim 8 is characterized in that, this at least one groove is the square slotted eye of parallel this first lead-in wire bearing of trend in long limit.
11. chip encapsulation construction according to claim 8 is characterized in that, this second lead-in wire has a line segment district in addition, and this line segment district connects this plane area.
12. a chip encapsulation construction comprises:
One base plate for packaging comprises:
One pliability dielectric layer; And
One conductive layer, be arranged on this pliability dielectric layer, this conductive layer further comprises a lead-in wire, this lead-in wire has a plane area and a line segment district, the width in this line segment district is less than the width of this plane area, this line segment district connects this plane area, and this plane area comprises contiguous this line segment district of a proximity, and this proximity is provided with at least one groove makes this proximity form at least one son lead-in wire; And
One chip is carried on this base plate for packaging, and is electrically connected this conductive layer.
13. chip encapsulation construction according to claim 12 is characterized in that, this line segment district has one first live width, and this at least one son lead-in wire has one second live width, and this second live width is between 0.5 times of this first live width and 10 times of these first live widths.
14. chip encapsulation construction according to claim 12 is characterized in that, this at least one groove is the square slotted eye of parallel this line segment district bearing of trend in long limit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101281285A CN101826506B (en) | 2009-03-05 | 2009-03-05 | Packaging substrate and chip packaging construct |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101281285A CN101826506B (en) | 2009-03-05 | 2009-03-05 | Packaging substrate and chip packaging construct |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101826506A CN101826506A (en) | 2010-09-08 |
| CN101826506B true CN101826506B (en) | 2011-09-21 |
Family
ID=42690336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101281285A Expired - Fee Related CN101826506B (en) | 2009-03-05 | 2009-03-05 | Packaging substrate and chip packaging construct |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101826506B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170758B (en) * | 2017-05-25 | 2020-08-14 | 京东方科技集团股份有限公司 | Flexible display substrate, manufacturing method thereof and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6984785B1 (en) * | 2003-10-27 | 2006-01-10 | Asat Ltd. | Thermally enhanced cavity-down integrated circuit package |
| CN1885513A (en) * | 2005-06-20 | 2006-12-27 | 南茂科技股份有限公司 | Tape for tape carrier package |
-
2009
- 2009-03-05 CN CN2009101281285A patent/CN101826506B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6984785B1 (en) * | 2003-10-27 | 2006-01-10 | Asat Ltd. | Thermally enhanced cavity-down integrated circuit package |
| CN1885513A (en) * | 2005-06-20 | 2006-12-27 | 南茂科技股份有限公司 | Tape for tape carrier package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101826506A (en) | 2010-09-08 |
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Granted publication date: 20110921 Termination date: 20200305 |