CN101826305B - Drive device and amplifier device with low power consumption and display device - Google Patents
Drive device and amplifier device with low power consumption and display device Download PDFInfo
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- CN101826305B CN101826305B CN200910004637A CN200910004637A CN101826305B CN 101826305 B CN101826305 B CN 101826305B CN 200910004637 A CN200910004637 A CN 200910004637A CN 200910004637 A CN200910004637 A CN 200910004637A CN 101826305 B CN101826305 B CN 101826305B
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Abstract
The invention discloses a drive device and an amplifier device with low power consumption and a display device. An output buffer circuit of the drive circuit is used for a display. The amplifier device comprises a first amplifier circuit and a second amplifier circuit, wherein the first amplifier circuit comprise a first input stage which is coupled between a higher power supply and a lower power supply as well as a first output stage which is coupled between the higher power supply and a first intermediate power supply; the first intermediate power supply is higher than the lower power supply; the second amplifier circuit comprises a second input stage which is coupled between the higher power supply and the lower power supply as well as a second input stage which is coupled between a second intermediate power supply and the lower power supply, wherein the second intermediate power supply is lower than the higher power supply.
Description
Technical field
Embodiment described herein relates to a kind of display equipment, relates in particular to a kind of output buffer of drive assembly, a kind of amplifier installation, and a kind of display equipment that uses this output buffer.
Background technology
Generally speaking, under the exploitation of accurate, light and handy, low-power and high-quality display equipment, for low-power consume, two-forty, high-res, and LCD (the LiquidCrystal Display of big output area; LCD) need for equipment is cumulative with day.Lcd driver is generally by source electrode driver, gate drivers, controller, and reference power source constitutes.For reaching the demand, these source electrode drivers are being played the part of the role who is even more important, and these source electrode drivers comprise register, data latches, digital to analog converter (Digital-to-Analog Converter; And output buffer DAC).In the middle of, these output buffers have determined speed, resolution, the voltage range of source electrode driver, and power dissipation.Because single chip built-in has in a large number the output buffer of (typical case last reaches hundreds of), so each output buffer must only occupy less chip area, and its power consumption also must be enough low simultaneously.
Fig. 1 is the synoptic diagram of a conventional source driver device.In Fig. 1, a conventional source driver device 100 comprises an output buffer 102 and and switches circuit 104.
This first amplifier circuit 110 is coupled between a higher power vd DA and the low power supply VSSA.The typical case is last; This first amplifier circuit 110 comprises an input stage (not shown); For example be one differential right, first export signal SO1 in order to receive this first input signal SI1 with this, and also comprise an output stage (not shown); In order to this first output signal SO1 to be provided, wherein this input stage and output stage all are coupled in this higher power vd DA and should hang down between the power supply VSSA.Similarly, this second amplifier circuit 120 is coupled in this higher power vd DA and should hangs down between the power supply VSSA.Comprise an input stage (not shown) on this second amplifier circuit 120 typical cases; For example be one differential right; In order to receive this second input signal SI2 and this second output signal SO2; And also comprise an output stage (not shown), in order to this second output signal SO2 to be provided, wherein this input stage and output stage all are coupled in this higher power vd DA and should hang down between the power supply VSSA.Therefore, this first and second amplifier circuit 110 and 120 both all can on the output driving scope between VSSA and the VDDA, drive this display pannel.
Suppose down long-time,<i
Charge1>=<i
Discharge1>, wherein<i
Charge1>With<i
Discharge1>Represent mean charging current and average discharge current respectively, then the average power consumption of the output stage of first amplifier circuit 110 can be expressed as:
<P>＝<i
charge1>×(VDDA-V
O1)+<i
discharge1>×(V
O1-VSSA)＝<i
charge1>×(VDDA-VSSA)
V wherein
O1Represent the voltage of the first output signal SO1.
Also suppose down long-time,<i
Charge2>=<i
Discharge2>, wherein<i
Charge2>With<i
Discharge2>Represent mean charging current and average discharge current respectively, then the average power consumption of the output stage of second amplifier circuit 120 can be expressed as:
<P>＝<i
charge2>×(VDDA-V
O2)+<i
discharge2>×(V
O2-VSSA)＝<i
charge2>×(VDDA-VSSA)
V wherein
O2Represent the voltage of the second output signal SO2.
Generally speaking; The restrictive condition of being considered during design source drive apparatus 100 can comprise: source electrode driver for the driving force of huge load on the display pannel, source drive apparatus 100 dynamically with steady state power consumption, source electrode driver 100 designs complexity with manufacturing, with and/or other characteristics of the structure/operation of buffer circuit.Yet above-mentioned source drive apparatus 100 can't satisfy above all design limit condition, especially power consumptions ideally.
Summary of the invention
Describe at this and a kind ofly to have the buffer circuits of the drive assembly of low power consumption, a kind of amplifier installation, and a kind of display equipment of this buffer circuits of application.
According to one side, a kind of output buffer of drive assembly, it is used for a display; Comprise first amplifier circuit, it comprises one first input stage, and it is coupled between a higher power supply and the low power supply; And comprise one first output stage, and it is coupled between this higher power supply and one first intermediate power supplies, and wherein this first intermediate power supplies is higher than this low power supply; And comprise second amplifier circuit, and it comprises one second input stage, and it is coupled in this higher power supply and should hangs down between the power supply; And comprise one second output stage, and it is coupling in one second intermediate power supplies and should hangs down between the power supply, and wherein this second intermediate power supplies is lower than this higher power supply.
According on the other hand; A kind of amplifier installation comprises an input stage, and it is coupled between first and second power supply, and an output stage; It is coupled between the 3rd and the 4th power supply, wherein is different from one of at least arbitrary power supply in the middle of this first and second power supply in the middle of the 3rd and the 4th power supply.
Above-mentioned and other characteristics, aspect, and embodiment describes in following embodiment.
Description of drawings
According to various characteristics of the present invention, function and embodiment, all can be from above-mentioned detailed description, and reach preferable understanding with reference to accompanying drawing simultaneously, these accompanying drawings comprise:
Fig. 1 is according to the calcspar of the display equipment of an embodiment.
Fig. 2 is a sequential chart, an embodiment of the waveform of the representation signal of the display equipment 100 of its displayed map 1.
Fig. 3 is another example source drive apparatus according to another embodiment.
Fig. 4 is the schematic block diagrams that shows according to the example display device of an embodiment.
[main element symbol description]
100～source drive apparatus, 102～output buffer
104～commutation circuit, 110～the first amplifier circuits
120～the second amplifier circuits, 200～source drive apparatus
202～output buffer, 204～commutation circuit
210～the first amplifier circuits, 212～the first input stages
214～the first output stages, 220～the second amplifier circuits
222～the second input stages, 224～the second output stages
300～source drive apparatus, 302～output buffer
310～the first amplifier circuits, 320～the second amplifier circuits
IN (-), IN1 (-), the defeated IN (+) of IN2 (-)～anti-phase, IN1 (+), IN2 (+)～noninverting ingress input node
FIRST_IN～first source electrode line input P11, P13, P21～higher power supply node
P12, P22, P24～low power supply node P14, P23～intermediate power supplies node
R11, R12, R21, R22～resistance SCTRL～control signal
SECOND_IN～second source electrode line is failed SI1～first input signal and is gone into
SI2～second input signal the SO1～first output the signal
SO2～second output signal SW1～first switch
SW2～second switch VCA1～first intermediate power supplies
VCA2～second intermediate power supplies the VDDA～higher power supply
VSSA～low power supply
Embodiment
Fig. 2 is the synoptic diagram according to the example source drive apparatus of an embodiment.In Fig. 2, one source pole drive assembly 200 can dispose and drive a display pannel (not shown), and can comprise an output buffer 202 and a switching circuit 204.
Output buffer 202 can comprise first amplifier installation 210 and second amplifier installation 220.This first amplifier installation 210 can dispose and receive the first input signal SI1 that is exported by a D/A converter (not shown); And at one first output node O1 the first output signal SO1 is provided, drives this display pannel to go up in the first output driving scope (i.e. the voltage range of the first output signal SO1).Similarly; This second amplifier installation 220 can dispose and receive the second input signal SI2 that is exported by this D/A converter; And at one second output node O2 the second output signal SO2 is provided, drives this display pannel to go up in the second output driving scope (i.e. the voltage range of the second output signal SO2).Under preferable situation, this first output driving scope occupies the part than the top of a whole output driving scope, and this second output driving scope occupies the part than the below of this integral body output driving scope.Under better situation, this first and second output driving scope occupies the first half and the Lower Half of a whole output driving scope respectively.
In Fig. 2; Commutation circuit 204 can be coupled in first and second amplifier circuit 210 and 220 and this display pannel between, and configurable control this first and second amplifier circuit 210 and 220 and this display pannel on source electrode line between coupling.For example, this commutation circuit 204 can be put into practice becomes a multiplexer, and this multiplexer comprises first switch SW 1 and second switch SW2, and this first and second switch SW 1 and SW2 receive the control of a control signal SCTRL.As control signal SCTRL during corresponding to first level; This first switch SW 1 can be coupled to first source electrode line input FIRST IN on this display pannel; And as control signal SCTRL during corresponding to second level, this first switch SW 1 can be coupled to second source electrode line input SECOND IN on this display pannel.Otherwise; As control signal SCTRL during corresponding to first level; This second switch SW2 can be coupled to second source electrode line input SECOND IN on this display pannel; And as control signal SCTRL during corresponding to second level, this second switch SW2 can be coupled to first source electrode line input FIRST IN on this display pannel.Because control signal SCTRL switches between first and second level; First and second amplifier circuit 210 and 220 can be coupled to source electrode line inputs different between this first and second source electrode line input FIRST IN and the SECOND IN in turn, to drive different source electrode lines.
This first output stage 214 can comprise a higher power supply node P13, and it can be coupled to this higher power vd DA, and comprises an intermediate power supplies node P14, and it can be coupled to one first intermediate power supplies VCA1.The level of this first intermediate power supplies VCA1 can be higher than the level of this low power supply.For example, this first intermediate power supplies VCA1 can be between VSSA and VDDA, and preferable situation is to equal (VDDA+VSSA)/2.
In addition, first input stage 212 can comprise a noninverting input node IN1 (+), and it can be coupled to this first input signal SI1, and comprises anti-phase input node IN1 (-), and it can be coupled to this first output node O1.At this, for example, this first amplifier circuit 210 can be configured to have unity gain (Unity Gain).
First input stage, 212 configurable next voltage levels according to this noninverting input node IN1 (+) and anti-phase input node IN1 (-) are operated.In addition, first input stage 212, it is coupled in this higher power vd DA and should hangs down between the power supply VSSA, can be configured to operate in an opereating specification, and this opereating specification can and should be limited to by low power supply VSSA by this higher power vd DA.For example, this first input stage 212 can comprise an amplifying circuit, is a kind of differential right differential amplifier that comprises for example.For the situation of amplifier that first amplifier circuit 210 is construed as unity gain, can the input transistors optimization of first input stage 212 be operated in the first above-mentioned output driving scope.For example, this is differential to can comprising the differential input transistor of N type, and these N type differential input transistors can be operated on first an output driving scope than upper section that occupy whole driving scope.
This charge path can be practiced as a current source, and this current source can provide one to flow to the electric current of the first output node O1 from higher power supply node P13, so that this first output node O1 is charged.And this discharge path can be practiced as an electric current groove (Current Sink), and this electric current groove can make electric current flow into this intermediate power supplies node P14 from this first output node O1, so that this first output node O1 is discharged.
For example; When the level of the first input signal SI1 that is positioned at noninverting input node IN1 (+) is higher than the first output signal SO1 that is coupled to anti-phase input node IN1 (-); The charge path meeting conducting of first output stage 214; And the output load on the display pannel is charged, use the level of drawing high the first output signal SO1.Otherwise; When the level of the first input signal SI1 that is positioned at noninverting input node IN1 (+) is lower than the first output signal SO1 that is coupled to anti-phase input node IN1 (-); The discharge path meeting conducting of first output stage 214; And the output load on the display pannel is discharged, use the level that drags down the first output signal SO1.
This second output stage 224 can comprise a higher power supply node P23, and it can be coupled to one second intermediate power supplies VCA2, and comprises an intermediate power supplies node P24, and it can be coupled to this low power supply VSSA.The level of this second intermediate power supplies VCA2 can be lower than the level of this higher power supply.For example, this second intermediate power supplies VCA2 can be between VSSA and VDDA, and preferable situation is to equal (VDDA+VSSA)/2.At this, for example, this output stage 212 and 224 can be shared the multiple power source of an and low power supply equidistance higher with this.
Second input stage, 222 configurable next voltage levels according to this noninverting input node IN2 (+) and anti-phase input node IN2 (-) are operated.In addition, second input stage 222, it is coupled in this higher power vd DA and should hangs down between the power supply VSSA, can be configured to operate in an opereating specification, and this opereating specification can and should be limited to by low power supply VSSA by this higher power vd DA.For example, this second input stage 222 can comprise an amplifying circuit, is a kind of differential right differential amplifier that comprises for example.For the situation of amplifier that second amplifier circuit 220 is construed as unity gain, can the input transistors optimization of second input stage 222 be operated in the second above-mentioned output driving scope.For example, this is differential to can comprising the differential input transistor of P type, and these P type differential input transistors can be operated on second an output driving scope than the lower part that occupy whole driving scope.
This charge path can be practiced as a current source, and this current source can provide one to flow to the electric current of the second output node O2 from middle power supply node P23, so that this second output node O2 is charged.And this discharge path can be practiced as an electric current groove (Current Sink), and this electric current groove can make electric current flow into and should hang down power supply node P24 from this second output node O2, so that this second output node O2 is discharged.
For example; When the level of the second input signal SI2 that is positioned at noninverting input node IN2 (+) is higher than the second output signal SO2 that is coupled to anti-phase input node IN2 (-); The charge path meeting conducting of second output stage 224; And the output load on the display pannel is charged, use the level of drawing high the second output signal SO2.Otherwise; When the level of the second input signal SI2 that is positioned at noninverting input node IN2 (+) is lower than the second output signal SO2 that is coupled to anti-phase input node IN2 (-); The discharge path meeting conducting of second output stage 224; And the output load on the display pannel is discharged, use the level that drags down the second output signal SO2.
Benefit from the above-mentioned power supply arrangement of being done for this first output stage 214; This first amplifier circuit 210 can to drive scope (being confined between VCCA and the VDDA) than the output of first amplifier circuit 110 (Fig. 1) also little because of it exports driving scope (being confined between VCA1 and the VDDA), and on dynamic power consumption, reduce to some extent.More clearly say it, first amplifier circuit 110 and 210 both input stages all operate on the opereating specification that is confined between VDDA and the VSSA, thereby can have identical power consumption.On the other hand, first output stage 214 of first amplifier circuit 210 can have identical dynamic power consumption for charging process, but then has lower power dissipation for discharge process.Generally speaking, first amplifier circuit, 210 less total power consumptions capable of using are operated.
In Fig. 2; First input stage 212 has accounted for minor role in the general power consume of first amplifier circuit 210; Reason is that first output stage 212 is to operate with a steady-state current; And compare for the operating current of first output stage 214 that must possess enough driving forces for this display pannel, this steady-state current can be much lower.Because first output stage 214 of contribution is the main status that has accounted for the general power consume of first amplifier circuit 210 to some extent on dynamic power consumption reduces, therefore the consume of first amplifier circuit, 210 general powers can have sizable ratio to be saved.
For example,, and suppose down long-time with the situation of VCA1=(VDDA+VSSA)/2,<i
Charge1>=<i
Discharge1>, wherein<i
Charge1>With<i
Discharge1>Represent mean charging current and average discharge current respectively, then the average power consumption of first output stage 214 in first amplifier circuit 210 is:
<P>＝<i
charge1>×(VDDA-V
O1)+<i
discharge1>×(V
O1-VCA1)＝<i
charge1>×(VDDA-VCA1)
＝<i
charge1>×(VDDA-VSSA)/2.
As a result, compared to the output stage (in Fig. 1) of first amplifier circuit 110, first output stage 214 can have only half the power consumption.
Similarly; Benefit from the above-mentioned power supply arrangement of being done for this second output stage 224; This second amplifier circuit 220 can to drive scope (being confined between VCCA and the VDDA) than the output of second amplifier circuit 120 (Fig. 1) also little because of it exports driving scope (being confined between VSSA and the VCA2), and on dynamic power consumption, reduce to some extent.More clearly say it, second amplifier circuit 120 and 220 both input stages all operate on the opereating specification that is confined between VDDA and the VSSA, thereby can have identical power consumption.On the other hand, second output stage 224 of second amplifier circuit 220 can have identical dynamic power consumption for discharge process, but then has lower power dissipation for charging process.Generally speaking, second amplifier circuit, 220 less total power consumptions capable of using are operated.
In Fig. 2; Second input stage 222 has accounted for minor role in the general power consume of second amplifier circuit 220; Reason is that second input stage 222 is to operate with a steady-state current; And compare for the operating current of second output stage 224 that must possess enough driving forces for this display pannel, this steady-state current can be much lower.Because second output stage 224 of contribution is the main status that has accounted for the general power consume of second amplifier circuit 220 to some extent on dynamic power consumption reduces, therefore the consume of second amplifier circuit, 220 general powers can have sizable ratio to be saved.
For example,, and suppose down long-time with the situation of VCA2=(VDDA+VSSA)/2,<i
Charge2>=<i
Discharge2>, wherein<i
Charge2>With<i
Discharge2>Represent mean charging current and average discharge current respectively, then the average power consumption of second output stage 224 in second amplifier circuit 220 is:
<P>＝<i
charge2>×(VCA2-V
O2)+<i
discharge2>×(V
O2-VSSA)＝<i
charge2>×(VDDA-VCA2)
＝<i
charge2>×(VDDA-VSSA)/2.
As a result, compared to the output stage (in Fig. 1) of second amplifier circuit 120, second output stage 224 can have only half the power consumption.
In summary, because first output stage 214 has and above-mentionedly is coupled to the first intermediate power supplies VCA1 but not is coupled to the discharge path of low power supply VSSA, therefore the consume of the dynamic power of first amplifier circuit, 210 discharge processes can save effectively.In addition, because second output stage 224 has and above-mentionedly is coupled to the second intermediate power supplies VCA2 but not is coupled to the charge path of higher power vd DA, therefore the consume of the dynamic power of second amplifier circuit, 220 charging processes can save effectively.Generally speaking, the total power consumption of source drive apparatus 200 can reduce compared to conventional source driver device 100 effectively.
Though above-mentioned first and second amplifier circuit 210 and 220 is shown as the unity gain amplifier circuit, yet other kinds configuration is possible.Unique requirement can be that one of them amplifier circuit comprises an input stage and an output stage that is coupled between VCA1 (greater than VSSA) and the VDDA that is coupled in VSSA and VDDA, and the another one amplifier comprises an input stage and an output stage that is coupled between VSSA and the VCA2 (being lower than VDDA) that is coupled in VSSA and VDDA.Therefore, all different amplifier circuit are inverting amplifier circuits for example, all can use.
Fig. 3 is another example source drive apparatus according to another embodiment.In Fig. 3, one source pole drive assembly 300 can be configured to comprise an output buffer 302, and it comprises first amplifier circuit 310 and second amplifier circuit 320, and one switches circuit 204.At this; Source drive apparatus 300 can be similar in fact with source drive apparatus 200 (Fig. 2 in), and difference only is first and second amplifier circuit 310 and 320 configurable one-tenth inverting amplifier circuits but not unity gain amplifier circuit 210 and 220 (in Fig. 2).Like is to utilize identical reference number and symbol to indicate with node in Fig. 2 and Fig. 3.
(in Fig. 2) is similar in fact with first and second amplifier circuit 210 and 220; First amplifier circuit 310 can dispose provides the first output signal SO1; With on first an output driving scope of limiting to, drive a display pannel, and second amplifier circuit 320 can dispose the second output signal SO2 is provided by VCA1 and VDDA; With on second an output driving scope of limiting to, drive this display pannel by VSSA and VCA2.
Second amplifier circuit 320 can comprise two resistance R 21 and R22, and an amplifier circuit 220.Resistance R 21 can be coupling between the anti-phase input node IN2 (-) of one second input signal SI2 and this first amplifier circuit 220.Resistance R 22 can be coupled between the output node O2 of this anti-phase input node IN2 (-) and this second amplifier circuit 220.Therefore, second amplifier circuit 320 can have one depend on resistance R 21 and R22 gain.
Because first and second amplifier circuit 320 and 330 keeps first and second amplifier circuit 210 and 220 (in Fig. 2) respectively, so the power consumption of source drive apparatus 300 (in Fig. 3) can reduce because of similar reason.
Fig. 4 is the schematic block diagrams that shows according to the example display device of an embodiment.In Fig. 4, a display equipment 400 can adopt above-mentioned source drive apparatus 200 or 300, and can comprise an one source pole driver 410 and a display pannel 420.Display pannel 420 can comprise many source electrode lines, in the middle of comprise source electrode line SL1 and SL2, and many gate lines, i.e. GL1 to GLn, wherein n is a nonzero integer.These source electrode driver 410 configurable these source electrode lines that drive on this display pannel 420, and above-mentioned source drive apparatus 200 capable of using (Fig. 2 in) or this source drive apparatus 300 (in Fig. 3) are put into practice.Clearly say it, source electrode driver 410 can comprise an output buffer circuit 420, and it can be put into practice becomes above-mentioned output buffer 202 (in Fig. 2) or output buffer 302, and comprises above-mentioned commutation circuit 204 (in Fig. 2 or Fig. 3).
Though the source drive apparatus 200 and 300 of the above-mentioned exemplary embodiment of foundation is described as and is used for driving a display pannel, yet source drive apparatus 200 and 300 also can be used as all different application.
Though the present invention with preferred embodiment openly as above; Right its is not that those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (20)
1. the output buffer of a drive assembly is used for a display, comprising:
First amplifier circuit, it comprises:
One first input stage, it is coupled between one first power supply and the second source, and wherein this first power supply is higher than this second source; And
One first output stage, it is coupled between this first power supply and one first intermediate power supplies, and this first intermediate power supplies is higher than this second source; And
Second amplifier circuit, it comprises:
One second input stage, it is coupled between this first power supply and this second source; And
One second output stage, it is coupling between one second intermediate power supplies and this second source, and this second intermediate power supplies is lower than this first power supply.
2. the output buffer of drive assembly as claimed in claim 1, wherein this first and second input stage is configured to receive respectively first and second input signal.
3. the output buffer of drive assembly as claimed in claim 2, wherein this first and second output stage is configured to provide respectively one in the second output signal of the first output signal on the first output driving scope and on the second output driving scope.
4. the output buffer of drive assembly as claimed in claim 3, wherein this first output driving scope is limited to by this first intermediate power supplies and this first power supply, and this second is exported driving scope and limited to by this second source and this second intermediate power supplies.
5. the output buffer of drive assembly as claimed in claim 1, wherein this first and second intermediate power supplies is this first power supply and its difference and the multiple power source that equates with the difference of second source thereof.
6. the output buffer of drive assembly as claimed in claim 1, wherein this first and second output stage drives the different source electrode lines of a display pannel in turn.
7. the output buffer of drive assembly as claimed in claim 1, wherein this first output stage comprises:
One output node is to provide one first output signal; And
One discharge path, it is arranged to this first intermediate power supplies from this output node.
8. the output buffer of drive assembly as claimed in claim 1, wherein this second output stage comprises:
One output node is to provide one second output signal; And
One charge path, it is arranged to this output node from this second intermediate power supplies.
9. the output buffer of drive assembly as claimed in claim 1; Wherein this first output stage provides first an output signal in the first of a whole output driving scope; And this second output stage provides second an output signal on the second portion of this integral body output driving scope, and the voltage of first is higher than the voltage of second portion.
10. the output buffer of drive assembly as claimed in claim 1; Wherein this output buffer also is coupled to one and switches circuit, and this commutation circuit is configured to control the coupling between many source electrode lines of this first and second amplifier circuit and a display pannel of this output buffer.
11. an amplifier installation comprises:
One input stage, it is coupled between first and second power supply, and wherein this first power supply is higher than this second source; And
One output stage, it is coupled between the 3rd and the 4th power supply,
Wherein the 3rd power supply is higher than this second source, and/or the 4th power supply is lower than this first power supply.
12. like the amplifier installation of claim 11, wherein this input stage is configured to receive an input signal, and this output stage is configured to provide an output signal on an output driving scope.
13., wherein should output driving scope limit to by the 3rd and the 4th power supply like the amplifier installation of claim 12.
14., be this first power supply and its difference and the multiple power source that equates with the difference of second source thereof one of in the middle of the 3rd and the 4th power supply wherein like the amplifier installation of claim 11.
15. like the amplifier installation of claim 11, wherein this amplifier installation is configured to drive at least one source electrode line on the display pannel.
16. a display equipment comprises:
One display pannel, it has many source electrode lines; And
The one source pole driver, it has an output buffer, and this output buffer comprises:
One first amplifier circuit, it comprises:
One first input stage, it is coupled between one first power supply and the second source, and wherein this first power supply is higher than this second source; And
One first output stage, it is coupled between this first power supply and one first intermediate power supplies, and this first intermediate power supplies is higher than this second source; And
One second amplifier circuit, it comprises:
One second input stage, it is coupled between this first power supply and this second source; And
One second output stage, it is coupling between one second intermediate power supplies and this second source, and this second intermediate power supplies is lower than this first power supply.
17. like the display equipment of claim 16, wherein
This first and second input stage is configured to receive respectively first and second input signal, and
This first and second output stage is configured to provide respectively one at the second output signal of the first output signal on the first output driving scope and on the second output driving scope.
18. like the display equipment of claim 17, wherein this first output driving scope is limited to by this first intermediate power supplies and this first power supply, and this second output driving scope is limited to by this second source and this second intermediate power supplies.
19. like the display equipment of claim 16, wherein this first and second intermediate power supplies is this first power supply and its difference and the multiple power source that equates with the difference of second source thereof.
20. like the display equipment of claim 16, wherein this source electrode driver comprises that also one switches circuit, it is configured to control the coupling between these many source electrode lines of this first and second amplifier circuit and this display pannel.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW298868U (en) * | 1996-03-27 | 1997-02-21 | wen-long Li | Improved structure for forming mold of cooking pot |
| CN1804688A (en) * | 2006-01-20 | 2006-07-19 | 西安西北工业大学科技产业集团公司 | Output buffer circuit for drive voltage in liquid crystal display drive control chip |
| JP2009042428A (en) * | 2007-08-08 | 2009-02-26 | Nec Electronics Corp | Amplifier circuit and display device |
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| Publication number | Publication date |
|---|---|
| CN101826305A (en) | 2010-09-08 |
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