CN101819998B - High voltage low power consumption SOI LDMOS transistor having strained silicon structure - Google Patents
High voltage low power consumption SOI LDMOS transistor having strained silicon structure Download PDFInfo
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- CN101819998B CN101819998B CN2010101591706A CN201010159170A CN101819998B CN 101819998 B CN101819998 B CN 101819998B CN 2010101591706 A CN2010101591706 A CN 2010101591706A CN 201010159170 A CN201010159170 A CN 201010159170A CN 101819998 B CN101819998 B CN 101819998B
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Abstract
The invention provides a high voltage low power consumption SOI LDMOS transistor having strained silicon structure, which comprises a source region (9), a body region (8), a drain region (5), a super-junction structure middle n column (3), a super-junction structure middle p column (4), a source electrode (10), a drain electrode (12), a grid electrode (11) and an embedded dielectric layer (6), wherein the super-junction structure middle p column (4) is silicon material lattice-unmatched monocrystal material, which is a material capable of leading silicon to generate strain, like Ge or SiGe, and the super-junction structure middle n column (3) is n-type transverse tensile strain silicon which is parallel to the source electrode and the drain electrode and generated on the basis of the super-junction structure middle p column (4). According to the invention, the requirement of reducing drain-source on-resistance is taken into consideration on the premise of maintaining the pressure resistance of devices. The transistor according to the invention is compatible with conventional SOI LDMOS transistor technology, has quite strong practicability and is easier for meeting the application requirement of power electronic system.
Description
Technical field
What the present invention relates to is a kind of electronic device, mainly is a kind of transistor.Specifically a kind of silicon-on-insulator (SOI) transverse diffusion metal oxide semiconductor field effect transistor (LDMOSFET).
Background technology
In recent years, Electric Machine Control, electric ballast, power provider switch module and other correlation technique are promoting smart-power IC (SPIC) fast development.In SPIC, important function in the performance of LDMOS device.The design of LDMOS device, the factor of overriding concern are puncture voltage (BV) and conducting resistance (R
On) trade-off problem.In the recent period, a kind of new device that is called super knot (Super Junction) because its relative traditional devices has greatly improved aspect puncture voltage and conducting resistance compromise by extensive concern.The idea of super knot is based on device in off position the time, doped n, the p post charge compensation fully of alternately laying equal stress in the drift region.When supposing that the very narrow and inner separately impurity of n, p post in the super knot is identical, under very little voltage, n, p post just are in spent condition, and this moment, n, p post demonstrate the attribute of lamina propria, and the electric field energy in the drift region accesses approximate consistent the distribution, so puncture voltage has obtained the raising than the people.
Yet the electric charge of the p type substrate that comprises in the ldmos transistor has participated in the charge compensation in the super-junction structure, and therefore, the puncture voltage of device is a greater impact, and causes super-junction structure not used on a large scale in lateral power.Super junction LDMOS (Patent No.US 6,768,180 B2) is implanted in propositions such as Salama on soi structure, limited in the super knot charge interaction in the electric charge and substrate effectively.
Summary of the invention
The object of the present invention is to provide a kind of high voltage low power consumption SOI ldmos transistor of conducting resistance of reduction SOI ldmos transistor that can be bigger with strained silicon structure.
The object of the present invention is achieved like this:
Comprise in source region 9, tagma 8, drain region 5, the super-junction structure p post 4, source electrode 10, drain electrode 12, gate electrode 11, embedding dielectric layer 6 in n post 3, the super-junction structure, p post 4 is and the unmatched monocrystal material of silicon materials lattice in the described super-junction structure, described monocrystal material is to make silicon can generate the material of strain as Ge or SiGe, and n post 3 is parallel to the horizontal tensile strain silicon of source-drain electrode in the described super-junction structure for the n type that generates on p post 4 bases in super-junction structure.
1, p post 4 is a pectinate texture in source-drain electrode direction cross section in the super-junction structure.
2, n post 3, the stacked arrangement of 4 one-tenth levels of p post in the super-junction structure.
3, n post 3, p post 4 are arranged along paper direction layered laminate in the super-junction structure.
Can also comprise p type buried regions 13 in the composition of the high voltage low power consumption SOI ldmos transistor with strained silicon structure of the present invention.Described p type buried regions 13 is and the unmatched monocrystal material of silicon materials lattice, described monocrystal material is that Ge or SiGe make silicon can generate the material of strain, and p post 4 is for generating on p type buried regions 13 bases in n post 3 and the super-junction structure in the super-junction structure, and n, the p type of arranging along paper direction layered laminate is parallel to the horizontal tensile strain silicon of source-drain electrode.
In addition, the three-dimensional dimension of the strained silicon n post 3 in the above-mentioned super knot, p post 4 or p type buried regions 13 and impurities concentration distribution can specifically be set according to the requirement of the concrete on state characteristic of device, breakdown characteristics.
High voltage low power consumption SOI ldmos transistor with strained silicon structure of the present invention, can be by the three-dimensional dimension and the impurities concentration distribution of n post 3, p post 4 or p type buried regions 13 in the super knot of optimal design, make n post 3 transversely generate tensile strain silicon being parallel to source-drain electrode, improve the electronic carrier mobility in 3 districts widely, thereby reduce the conduction resistance value of device.Reach under the prerequisite of not sacrificing device withstand voltage, take into account the requirement that reduces leakage-source conducting resistance simultaneously.The present invention and conventional SOI ldmos transistor process compatible have very strong exploitativeness, the easier application requirements that satisfies power electronic system.
Description of drawings
Fig. 1 is a kind of existing super knot SOI ldmos transistor three-dimensional structure schematic diagram;
Fig. 2 is the high voltage low power consumption SOI ldmos transistor three-dimensional structure schematic diagram with strained silicon structure of first execution mode of the present invention;
Fig. 3 is the high voltage low power consumption SOI ldmos transistor three-dimensional structure schematic diagram with strained silicon structure of second execution mode of the present invention;
Fig. 4 is the high voltage low power consumption SOI ldmos transistor three-dimensional structure schematic diagram with strained silicon structure of the 3rd execution mode of the present invention;
Fig. 5 is the high voltage low power consumption SOI ldmos transistor three-dimensional structure schematic diagram with strained silicon structure of the 4th execution mode of the present invention.
Embodiment
For example the present invention is done description in more detail below in conjunction with accompanying drawing:
With reference to Fig. 2, SOI ldmos transistor of the present invention.Comprise in source region 9, tagma 8, the super knot that p post 4, drain region 5, source electrode 10, drain electrode 12, gate electrode 11, embedding dielectric layer 6 (are SiO in n post 3, the super knot
2Or Al
2O
3Deng insulating medium layer).It is characterized in that p post 4 is and the unmatched monocrystal material of silicon materials lattice (as Ge, SiGe etc. make silicon can generate the material of strain), and n post 3 is parallel to the horizontal tensile strain silicon of source-drain electrode for the n type that generates on p post 4 bases.P post 4 is a pectinate texture in source-drain electrode direction cross section in the super-junction structure.According to the requirement of the concrete on state characteristic of device, breakdown characteristics, determine super knot n post 3 and super knot p post 4 impurity concentrations relation: N among Fig. 2
3=N
4, it is W that super knot n post 3 closes with super knot p post 4 width
3＞W
4Super knot n post 3 and super knot p post 4 spatial volumes relation: V
3=V
4
With reference to Fig. 3, SOI ldmos transistor of the present invention.Comprise in source region 9, tagma 8, the super knot that p post 4, drain region 5, source electrode 10, drain electrode 12, gate electrode 11, embedding dielectric layer 6 (are SiO in n post 3, the super knot
2Or Al
2O
3Deng insulating medium layer).It is characterized in that p post 4 is and the unmatched monocrystal material of silicon materials lattice (as Ge, SiGe etc. make silicon can generate the material of strain), and n post 3 is parallel to the horizontal tensile strain silicon of source-drain electrode for the n type that generates on p post 4 bases.N post 3, the stacked arrangement of 4 one-tenth levels of p post in the super-junction structure.According to the requirement of the concrete on state characteristic of device, breakdown characteristics, determine super knot n post 3 and super knot p post 4 impurity concentrations relation: N among Fig. 3
3=N
4, super knot n post 3 and super knot p post 4 width relation: W
3=W
4, super knot n post 3 and super knot p post 4 thickness relationship: H
3=H
4
With reference to Fig. 4, SOI ldmos transistor of the present invention.Comprise in source region 9, tagma 8, the super knot that p post 4, drain region 5, source electrode 10, drain electrode 12, gate electrode 11, embedding dielectric layer 6 (are SiO in n post 3, the super knot
2Or Al
2O
3Deng insulating medium layer).It is characterized in that p post 4 is and the unmatched monocrystal material of silicon materials lattice (as Ge, SiGe etc. make silicon can generate the material of strain), and n post 3 is parallel to the horizontal tensile strain silicon of source-drain electrode for the n type that generates on p post 4 bases.N post 3, p post 4 are arranged along paper direction layered laminate in the super-junction structure.According to the requirement of the concrete on state characteristic of device, breakdown characteristics, determine super knot n post 3 and super knot p post 4 impurity concentrations relation: N among Fig. 4
3=N
4, super knot n post 3 and super knot p post 4 width relation: W
3=W
4, super knot n post 3 and super knot p post 4 thickness relationship: H
3=H
4
With reference to Fig. 5, SOI ldmos transistor of the present invention.Comprise in source region 9, tagma 8, the super knot that p post 4, drain region 5, p type buried regions 13, source electrode 10, drain electrode 12, gate electrode 11, embedding dielectric layer 6 (are SiO in n post 3, the super knot
2Or Al
2O
3Deng insulating medium layer).It is characterized in that p type buried regions 13 for and the unmatched monocrystal material of silicon materials lattice (as Ge, SiGe etc. make silicon can generate the material of strain), and n post 3 and p post 4 are parallel to the horizontal tensile strain silicon of source-drain electrode for n, the p type that generates on p type buried regions 13 bases.According to the requirement of the concrete on state characteristic of device, breakdown characteristics, determine super knot n post 3, super knot p post 4 and p type buried regions 13 impurity concentrations relation: N among Fig. 5
3=N
4=N
13, it is W that super knot n post 3 closes with super knot p post 4 width
3＞W
4Super knot n post 3, super knot p post 4 and p type buried regions 13 spatial volumes relation: V
3=V
4+ V
13
Above-mentioned for the present invention especially exemplified by embodiment, be not in order to limit the present invention.Super-junction structure with strained silicon provided by the invention is equally applicable to lateral direction power semiconductor device and their variants such as SOI high-voltage diode, SOI LIGBT, SOI thyristor and JFET.Do not breaking away from the spirit and scope of the invention, can do a little adjustment and optimization, protection scope of the present invention is as the criterion with claim.
Claims (2)
1. high voltage low power consumption SOI ldmos transistor with strained silicon structure, comprise source region (9), tagma (8), drain region (5), n post (3) in the super-junction structure, p post (4) in the super-junction structure, source electrode (10), drain electrode (12), gate electrode (11), embedding dielectric layer (6), it is characterized in that: p post (4) is and the unmatched monocrystal material of silicon materials lattice in the described super-junction structure, described monocrystal material is that Ge or SiGe make silicon can generate the material of strain, n post (3) is the horizontal tensile strain silicon that generates on p post (4) basis in super-junction structure in the described super-junction structure, and n post (3) and p post (4) length direction all are parallel to orientation; P post (4) is a pectinate texture in source-drain electrode direction cross section in the super-junction structure, the impurity concentration N of n post (3) in the super-junction structure
3Impurity concentration N with p post (4) in the super-junction structure
4The pass be N
3=N
4The width W of n post (3) in the super-junction structure
3Width W with p post (4) in the super-junction structure
4The pass be W
3＞W
4The spatial volume V of n post (3) in the super-junction structure
3Spatial volume V with p post (4) in the super-junction structure
4The pass be V
3=V
4
2. high voltage low power consumption SOI ldmos transistor with strained silicon structure, comprise source region (9), tagma (8), drain region (5), n post (3) in the super-junction structure, p post (4) in the super-junction structure, source electrode (10), drain electrode (12), gate electrode (11), embedding dielectric layer (6), it is characterized in that: p post (4) is and the unmatched monocrystal material of silicon materials lattice in the described super-junction structure, described monocrystal material is that Ge or SiGe make silicon can generate the material of strain, n post (3) is the horizontal tensile strain silicon that generates on p post (4) basis in super-junction structure in the described super-junction structure, n post (3), p post (4) and p type buried regions (13) length direction all are parallel to orientation; Described p type buried regions (13) is and the unmatched monocrystal material of silicon materials lattice, described monocrystal material is that Ge or SiGe make silicon can generate the material of strain, and in the super-junction structure in n post (3) and the super-junction structure p post (4) be on p type buried regions (13) basis, generate, the n that arranges along the channel width dimension layered laminate, the horizontal tensile strain silicon of p type; The impurity concentration N of n post (3) in the super-junction structure
3Impurity concentration N with p post (4) in the super-junction structure
4And the impurity concentration N of p type buried regions (13)
13The pass be N
3=N
4=N
13The width W of n post (3) in the super-junction structure
3Width W with p post (4) in the super-junction structure
4The pass be W
3＞W
4The spatial volume V of n post (3) in the super-junction structure
3Spatial volume V with p post (4) in the super-junction structure
4And the spatial volume V of p type buried regions (13)
13The pass be V
3=V
4+ V
13
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339866B (en) * | 2011-10-14 | 2013-06-05 | 东南大学 | Terminal structure of longitudinal double-diffusion MOSFET (metal-oxide-semiconductor field effect transistor) |
| CN103325816B (en) * | 2012-03-19 | 2017-07-18 | 联华电子股份有限公司 | High-voltage semiconductor element |
| CN103489915B (en) * | 2013-09-16 | 2016-05-11 | 电子科技大学 | A kind of laterally high pressure Superjunction power semiconductor device |
| CN104810398B (en) * | 2014-01-29 | 2018-06-22 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
| CN104979382A (en) * | 2014-04-02 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN105097914B (en) * | 2014-05-04 | 2018-02-06 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacture method |
| CN104157690B (en) * | 2014-08-14 | 2017-05-10 | 电子科技大学 | Strain NLDMOS device with groove structure and manufacturing method thereof |
| CN104821335B (en) * | 2015-03-13 | 2018-03-02 | 西安华羿微电子股份有限公司 | The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of n type buried layer cover type half |
| CN104716190B (en) * | 2015-03-13 | 2017-09-29 | 西安后羿半导体科技有限公司 | The super-junction laterally double-diffusion metal-oxide-semiconductor field effect transistor of p type buried layer cover type half |
| CN106847884A (en) * | 2017-02-28 | 2017-06-13 | 电子科技大学 | The SOI LIGBT device architectures of low turn-off power loss |
| CN106876456A (en) * | 2017-02-28 | 2017-06-20 | 电子科技大学 | Low turn-off power loss double gate SOI LIGBT device architectures |
| CN107359195B (en) * | 2017-07-31 | 2020-12-29 | 电子科技大学 | High-voltage-resistance transverse super junction device |
| CN113782591A (en) * | 2021-09-10 | 2021-12-10 | 南京邮电大学 | Medium-enhanced transverse super-junction power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6768180B2 (en) * | 2002-04-04 | 2004-07-27 | C. Andre T. Salama | Superjunction LDMOST using an insulator substrate for power integrated circuits |
| EP1516369A1 (en) * | 2002-06-26 | 2005-03-23 | Cambridge Semiconductor Limited | Lateral semiconductor device |
| US6828628B2 (en) * | 2003-03-05 | 2004-12-07 | Agere Systems, Inc. | Diffused MOS devices with strained silicon portions and methods for forming same |
| US7023050B2 (en) * | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
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Non-Patent Citations (1)
| Title |
|---|
| Fujihira,T. et al..Simulated Superior Performances of Semiconductor Superjunction Devices.《power semiconductor devices and ICs,1998.ISPSD 98.Proceedings of the 10th international symposium on》.1998,423－426. * |
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