CN101814505A - Multi-layer floating gate nonvolatile memory structure and production method thereof - Google Patents
Multi-layer floating gate nonvolatile memory structure and production method thereof Download PDFInfo
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- CN101814505A CN101814505A CN200910078554A CN200910078554A CN101814505A CN 101814505 A CN101814505 A CN 101814505A CN 200910078554 A CN200910078554 A CN 200910078554A CN 200910078554 A CN200910078554 A CN 200910078554A CN 101814505 A CN101814505 A CN 101814505A
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Abstract
The invention discloses a multi-layer floating gate nonvolatile memory structure and a production method thereof, wherein the multi-layer floating gate nonvolatile memory structure comprises a silicon substrate, a silicon dioxide layer, a silicon nanocrystals / high temperature oxide multilayer structure, a polysilicon layer, a silicon dioxide layer, grid and source / drain region formed by sculpturing on the silicon substrate, and a side wall formed by sculpturing on the silicon dioxide layer. The invention solves the defects because the traditional Flash technology node can downsized, utilizes the multi-layer floating gate to storage charge to enhance a storage window, so that the reliability of the floating grid for storing charge can be increased and the retention performance of a floating device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly a kind of with silicon nanocrystal as multi-layer floating gate nonvolatile memory structure of storage medium and preparation method thereof.
Background technology
Since the D.Kahng of Bell Laboratory in 1967 and S.M.Sze have proposed the nonvolatile semiconductor memory of floating gate structure, the floating boom semiconductor memory of the MOSFET structure of piling up based on grid just on capacity, cost and the power consumption with occupy great advantage replaced before the long-term magnetic memory that uses.
On this basis, Toshiba Corp has successfully proposed the notion of Flash memory in 1984, the Flash memory is the main flow device on the nonvolatile semiconductor memory market at present, but along with the microelectric technique node is constantly pushed ahead, the technology live width will further reduce, traditional flash device based on floating gate structure meets with serious technological difficulties, main cause is because the lasting attenuate of tunneling medium layer, leaky is serious all the more, but seriously limited the downsizing of Flash device, the density refractory that causes floating-gate memory spare is to promote.
The solution that solves this type of problem at present has two kinds.A kind of revolution formula scheme is exactly the storage medium that adopts different fully storage mechanism and structure, as RRAM, and FeRAM, PCRAM etc.; Another modified model scheme is exactly on the basis of existing nonvolatile floating grid memory, adopts new floating boom storage medium, and is as Nitride, nanocrystalline etc.For preceding a kind of scheme, owing to adopt two ends formula storage organization, memory cell takies area of chip and can significantly reduce, density can further improve, but in the middle of this scheme, that have and compatibility traditional cmos process are not very high, need to increase extra processing step, the storage mechanism that has is still waiting further research, also is not very ripe at present therefore.And, adopt silicon nitride for second kind of scheme, nonmetal nanocrystalline, almost compatible fully with traditional cmos process, even do not need to increase extra Lithographic template, there is boundless application prospect in the nonvolatile floating grid memory field for below the present 65nm.
But in second kind of scheme, also exist the problem of charge storage deficiency for the silicon nanocrystal floating-gate memory, and adopt sandwich construction can improve nanocrystalline charge storage, also can be used for the multidigit storage in addition.Making at present nanocrystalline method has multiplely, but it is the simplest to be based on the manufacture method of LPCVD, can form in a step, with low cost, and uniformity is higher, can be used for large-scale production and application.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention be to provide a kind of with silicon nanocrystal as multi-layer floating gate nonvolatile memory structure of storage medium and preparation method thereof, but to solve the deficiency that traditional flash technology node downsizing problem exists, utilize the multi-layer floating gate store charge to increase memory window, the reliability of floating boom stored charge is increased, improve the retention performance of floating-gate device.
(2) technical scheme
For achieving the above object, the invention provides a kind of multi-layer floating gate nonvolatile memory structure, this structure comprises silicon substrate, silicon dioxide layer, silicon nanocrystal/high-temperature oxide sandwich construction, polysilicon layer, silicon dioxide layer and etching forms on silicon substrate grid and source/drain region from the bottom to top successively, and the side wall that etching forms on silicon dioxide layer.
In the such scheme, described silicon nanocrystal/high-temperature oxide sandwich construction is alternately added up successively by silicon nanocrystal and high-temperature oxide and forms, orlop is a silicon nanocrystal, and the superiors are high-temperature oxide, and the thickness of the superiors' high-temperature oxide is greater than the thickness of intermediate layer high-temperature oxide.
In the such scheme, the thickness of described the superiors high-temperature oxide is 7～15nm, and the thickness of intermediate layer high-temperature oxide is 1～2nm.
In the such scheme, the thickness of described silicon dioxide layer is 3～4nm, and the thickness of described polysilicon layer is 150～300nm, and the thickness of described silicon dioxide layer is 400～600nm.
For achieving the above object, the present invention also provides a kind of manufacture method of multi-layer floating gate nonvolatile memory structure, and this method comprises:
Step 1: the layer of silicon dioxide of on silicon substrate, growing;
Step 2: the silicon substrate to the silicon dioxide of having grown carries out preliminary treatment, then at silica surface deposit one deck silicon nanocrystal;
Step 3: deposit one deck high-temperature oxide on silicon nanocrystal;
Step 4: the high-temperature oxide to deposit carries out preliminary treatment, again deposit one deck silicon nanocrystal;
Step 5: repeated execution of steps 3 and step 4, deposit silicon is nanocrystalline/the high-temperature oxide sandwich construction;
Step 6: deposit one deck polysilicon, and then a step etch into silicon substrate and form grid and source/drain region;
Step 7: adopt the high density plasma deposition layer of silicon dioxide, anisotropic etching goes out side wall again;
Step 8: make source/drain region, extraction electrode at last again.
In the such scheme, growth layer of silicon dioxide employing thermal oxidation process realization on silicon substrate described in the step 1, silicon substrate to the silicon dioxide of having grown described in the step 2 carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, adopt the LPCVD method to realize at silica surface deposit one deck silicon nanocrystal, deposit silicon nanocrystalline gases used be silane.
In the such scheme, deposit one deck high-temperature oxide employing LPCVD method realization on silicon nanocrystal described in the step 3, the thickness of high-temperature oxide is 1～2nm.
In the such scheme, the high-temperature oxide to deposit described in the step 4 carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, and deposit one deck silicon nanocrystal adopts the LPCVD method to realize.
In the such scheme, deposit silicon described in the step 5 is nanocrystalline/process of high-temperature oxide sandwich construction in, adopt LPCVD method deposit one deck high-temperature oxide at last, this high-temperature oxide thickness is 7～15nm.
In the such scheme, the thickness of the polysilicon of deposit described in the step 6 is 150～300nm, and the thickness of the silicon dioxide of deposit described in the step 7 is 400～600nm.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, can obtain having the multi-layer floating gate structure that high charge storage capacity is deposited, can increase memory window.
2, utilize the present invention, can obtain having highdensity silicon nanocrystal, further increase memory window.
3, utilize the present invention, can obtain a kind of silicon nanocrystal of discrete storage medium, improve the retention performance of floating gate charge storage.
4, utilize the present invention, can obtain the silicon nanocrystal that LPCVD makes, this method and traditional cmos process are compatible fully, can improve the rate of finished products that device is made, and are applicable to large-scale production.
Description of drawings
Fig. 1 is the structural representation of multi-layer floating gate nonvolatile memory structure provided by the invention;
Fig. 2 is the method flow diagram of making multi-layer floating gate nonvolatile memory structure provided by the invention;
Fig. 3-1 is to Fig. 3-the 10th, the process chart of the making multi-layer floating gate nonvolatile memory structure that provides according to the embodiment of the invention; Wherein, 1-metal; The 2-polysilicon; 3-high-temperature oxide (HTO); The 4-silicon nanocrystal; 5-Spacer (side wall); The 6-heat growth silicon dioxide; The 7-silicon substrate.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention adopts silicon nanocrystal as the multi-layer floating gate structure in the middle of the nonvolatile memory of storage medium, can improve the ability of floating gate layer stored charge, thereby can increase memory window.
As shown in Figure 1, Fig. 1 is the structural representation of multi-layer floating gate nonvolatile memory structure provided by the invention, this structure comprises silicon substrate, silicon dioxide layer, silicon nanocrystal/high-temperature oxide sandwich construction, polysilicon layer, silicon dioxide layer and etching forms on silicon substrate grid and source/drain region from the bottom to top successively, and the side wall that etching forms on silicon dioxide layer.
Silicon nanocrystal/high-temperature oxide sandwich construction is alternately added up successively by silicon nanocrystal and high-temperature oxide and forms, and orlop is a silicon nanocrystal, and the superiors are high-temperature oxide, and the thickness of the superiors' high-temperature oxide is greater than the thickness of intermediate layer high-temperature oxide.The thickness of the superiors' high-temperature oxide is 7～15nm, and the thickness of intermediate layer high-temperature oxide is 1～2nm.The thickness of silicon dioxide layer is 3～4nm, and the thickness of polysilicon layer is 150～300nm, and the thickness of silicon dioxide layer is 400～600nm.
As shown in Figure 2, Fig. 2 is the method flow diagram of making multi-layer floating gate nonvolatile memory structure provided by the invention, and this method may further comprise the steps:
Step 1: the layer of silicon dioxide of on silicon substrate, growing; Described growth layer of silicon dioxide employing thermal oxidation process realization on silicon substrate.
Step 2: the silicon substrate to the silicon dioxide of having grown carries out preliminary treatment, then at silica surface deposit one deck silicon nanocrystal; Described silicon substrate to the silicon dioxide of having grown carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, adopts the LPCVD method to realize at silica surface deposit one deck silicon nanocrystal, deposit silicon nanocrystalline gases used be silane.
Step 3: deposit one deck high-temperature oxide on silicon nanocrystal; Described deposit one deck high-temperature oxide employing LPCVD method realization on silicon nanocrystal, the thickness of high-temperature oxide is 1～2nm.
Step 4: the high-temperature oxide to deposit carries out preliminary treatment, again deposit one deck silicon nanocrystal; Described high-temperature oxide to deposit carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, and deposit one deck silicon nanocrystal adopts the LPCVD method to realize.
Step 5: repeated execution of steps 3 and step 4, deposit silicon is nanocrystalline/the high-temperature oxide sandwich construction; Described deposit silicon is nanocrystalline/process of high-temperature oxide sandwich construction in, adopt LPCVD method deposit one deck high-temperature oxide at last, this high-temperature oxide thickness is 7～15nm.
Step 6: deposit one deck polysilicon, and then a step etch into silicon substrate and form grid and source/drain region; The thickness of the polysilicon of described deposit is 150～300nm.
Step 7: adopt the high density plasma deposition layer of silicon dioxide, anisotropic etching goes out side wall again; The thickness of the silicon dioxide of described deposit is 400～600nm.
Step 8: make source/drain region, extraction electrode at last again.
Fig. 3-1 is to Fig. 3-the 10th, the process chart of the making multi-layer floating gate nonvolatile memory structure that provides according to the embodiment of the invention, concrete processing step is as follows: elder generation's thermal oxidation layer of silicon dioxide (Fig. 3-1) on silicon substrate, hydrofluoric acid with dilution carries out preliminary treatment again, then at the silica surface LPCVD highdensity silicon nanocrystal of method deposit one deck (Fig. 3-2), use LPCVD method deposit one deck HTO (Fig. 3-3) again, thickness range is 1～2nm, hydrofluoric acid with dilution carries out preliminary treatment then, use LPCVD method deposit one deck high-density silicon nano-crystalline (Fig. 3-4) again, the TO/ of deposit multi-layer H so repeatedly silicon nanocrystal (Fig. 3-5), use LPCVD method deposit one deck HTO at last, thickness is 7～15nm (Fig. 3-6), polysilicon about deposit one deck 150～300nm (Fig. 3-7) again, and then one the step etch into silicon substrate and form grid and source/drain region (Fig. 3-8), the silicon dioxide of HDP (high-density plasma) deposit one deck 400～600nm then, anisotropic etching goes out side wall (spacer) (Fig. 3-9) again, make source/drain region at last again, extraction electrode (Fig. 3-10).
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. multi-layer floating gate nonvolatile memory structure, it is characterized in that, this structure comprises silicon substrate, silicon dioxide layer, silicon nanocrystal/high-temperature oxide sandwich construction, polysilicon layer, silicon dioxide layer and etching forms on silicon substrate grid and source/drain region from the bottom to top successively, and the side wall that etching forms on silicon dioxide layer.
2. multi-layer floating gate nonvolatile memory structure according to claim 1, it is characterized in that, described silicon nanocrystal/high-temperature oxide sandwich construction is alternately added up successively by silicon nanocrystal and high-temperature oxide and forms, orlop is a silicon nanocrystal, the superiors are high-temperature oxide, and the thickness of the superiors' high-temperature oxide is greater than the thickness of intermediate layer high-temperature oxide.
3. multi-layer floating gate nonvolatile memory structure according to claim 2 is characterized in that, the thickness of described the superiors high-temperature oxide is 7～15nm, and the thickness of intermediate layer high-temperature oxide is 1～2nm.
4. multi-layer floating gate nonvolatile memory structure according to claim 1 is characterized in that, the thickness of described silicon dioxide layer is 3～4nm, and the thickness of described polysilicon layer is 150～300nm, and the thickness of described silicon dioxide layer is 400～600nm.
5. the manufacture method of a multi-layer floating gate nonvolatile memory structure is characterized in that, this method comprises:
Step 1: the layer of silicon dioxide of on silicon substrate, growing;
Step 2: the silicon substrate to the silicon dioxide of having grown carries out preliminary treatment, then at silica surface deposit one deck silicon nanocrystal;
Step 3: deposit one deck high-temperature oxide on silicon nanocrystal;
Step 4: the high-temperature oxide to deposit carries out preliminary treatment, again deposit one deck silicon nanocrystal;
Step 5: repeated execution of steps 3 and step 4, deposit silicon is nanocrystalline/the high-temperature oxide sandwich construction;
Step 6: deposit one deck polysilicon, and then a step etch into silicon substrate and form grid and source/drain region;
Step 7: adopt the high density plasma deposition layer of silicon dioxide, anisotropic etching goes out side wall again;
Step 8: make source/drain region, extraction electrode at last again.
6. the manufacture method of multi-layer floating gate nonvolatile memory structure according to claim 5, it is characterized in that, growth layer of silicon dioxide employing thermal oxidation process realization on silicon substrate described in the step 1, silicon substrate to the silicon dioxide of having grown described in the step 2 carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, adopt the LPCVD method to realize at silica surface deposit one deck silicon nanocrystal, deposit silicon nanocrystalline gases used be silane.
7. the manufacture method of multi-layer floating gate nonvolatile memory structure according to claim 5 is characterized in that, deposit one deck high-temperature oxide employing LPCVD method realization on silicon nanocrystal described in the step 3, and the thickness of high-temperature oxide is 1～2nm.
8. the manufacture method of multi-layer floating gate nonvolatile memory structure according to claim 5, it is characterized in that, high-temperature oxide to deposit described in the step 4 carries out the hydrofluoric acid that dilution is adopted in preliminary treatment, and deposit one deck silicon nanocrystal adopts the LPCVD method to realize.
9. the manufacture method of multi-layer floating gate nonvolatile memory structure according to claim 5, it is characterized in that, deposit silicon described in the step 5 is nanocrystalline/process of high-temperature oxide sandwich construction in, adopt LPCVD method deposit one deck high-temperature oxide at last, this high-temperature oxide thickness is 7～15nm.
10. the manufacture method of multi-layer floating gate nonvolatile memory structure according to claim 5 is characterized in that, the thickness of the polysilicon of deposit described in the step 6 is 150～300nm, and the thickness of the silicon dioxide of deposit described in the step 7 is 400～600nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105449002A (en) * | 2014-08-18 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Improved double-doped floating gate transistor |
| CN107204285A (en) * | 2017-07-07 | 2017-09-26 | 睿力集成电路有限公司 | The grid conducting layer of film, its forming method and its formation |
| CN110634875A (en) * | 2019-09-24 | 2019-12-31 | 上海华力微电子有限公司 | Memory cell, NAND flash memory architecture and forming method thereof |
| CN110777366A (en) * | 2019-10-15 | 2020-02-11 | 宁波大学 | Nanocrystalline silicon oxide film and photoresist-like silicon oxide material prepared from same |
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2009
- 2009-02-25 CN CN200910078554A patent/CN101814505A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105449002A (en) * | 2014-08-18 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Improved double-doped floating gate transistor |
| CN105449002B (en) * | 2014-08-18 | 2018-10-12 | 中芯国际集成电路制造(上海)有限公司 | Improved codope floating transistor |
| CN107204285A (en) * | 2017-07-07 | 2017-09-26 | 睿力集成电路有限公司 | The grid conducting layer of film, its forming method and its formation |
| CN107204285B (en) * | 2017-07-07 | 2018-03-30 | 睿力集成电路有限公司 | The grid conducting layer of film, its forming method and its formation |
| CN110634875A (en) * | 2019-09-24 | 2019-12-31 | 上海华力微电子有限公司 | Memory cell, NAND flash memory architecture and forming method thereof |
| CN110777366A (en) * | 2019-10-15 | 2020-02-11 | 宁波大学 | Nanocrystalline silicon oxide film and photoresist-like silicon oxide material prepared from same |
| CN110777366B (en) * | 2019-10-15 | 2021-11-23 | 宁波大学 | Nanocrystalline silicon oxide film and photoresist-like silicon oxide material prepared from same |
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Open date: 20100825 |