CN101814460A - Active element array substrate and manufacturing method thereof - Google Patents
Active element array substrate and manufacturing method thereof Download PDFInfo
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- CN101814460A CN101814460A CN201010161952A CN201010161952A CN101814460A CN 101814460 A CN101814460 A CN 101814460A CN 201010161952 A CN201010161952 A CN 201010161952A CN 201010161952 A CN201010161952 A CN 201010161952A CN 101814460 A CN101814460 A CN 101814460A
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Abstract
The embodiment of the invention provides an active element array substrate and a manufacturing method thereof. The active element array substrate is provided with at least one pattern conducting layer; the pattern conducting layer comprises a copper layer; the section of the copper layer in the normal direction parallel to the copper layer consisting of a first trapezoid and a second trapezoid overlapped on the trapezoid; and the angle difference between the base angle of the first trapezoid and the base angle of the second trapezoid is an acute angle between 5 and 30 degrees. Due to the embodiment of the invention, better electrical efficiency can be provided, and the line broken ratio can be effectively improved.
Description
Technical field
The present invention is about a kind of active component array base board (Active Device Array Substrate), especially in regard to a kind of active component array base board with copper conductive layer.
Background technology
Along with Thin Film Transistor-LCD (TFT-LCD) panel size is more done bigger, what follow is the low inadequately resistance capacitance that produces of plain conductor resistance (RC) late effect, thereby, cause signal in the process of transmission, to produce distortion distortion, and influence presenting of panel image quality.Utilize the low individual layer copper metal of resistance to form plain conductor, can effectively reduce the RC late effect.Yet, when having made the copper metal, can on the copper metallic surface, form cupric oxide, because the cupric oxide on copper top layer is different with the etched speed of copper, the problem of broken string takes place in the etching manufacturing process easily.
Summary of the invention
The invention provides a kind of active component array base board, this active component array base board has preferable electrical property efficiency.
The invention provides a kind of manufacture method of initiative element array, can effectively improve the broken string ratio by this manufacture method of initiative element array.
The present invention proposes a kind of active component array base board, this active component array base board has at least one patterned conductive layer, patterned conductive layer comprises the copper layer, the copper layer the section of the normal direction of parallel copper layer be by first trapezoidal be stacked in first second on trapezoidal and trapezoidally constitute, the first trapezoidal base angle and the second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle.
In one embodiment of this invention, the angle difference at the above-mentioned first trapezoidal base angle and the second trapezoidal base angle for example is between 7 ° to 13 °.
In one embodiment of this invention, the angle difference at the above-mentioned first trapezoidal base angle and the second trapezoidal base angle for example is 10 °.
In one embodiment of this invention, above-mentioned patterned conductive layer also comprises barrier layer, and copper is layered on the barrier layer.
In one embodiment of this invention, the material of above-mentioned barrier layer is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.
In one embodiment of this invention, the first above-mentioned trapezoidal height for example is greater than the second trapezoidal height.
In one embodiment of this invention, the first above-mentioned trapezoidal height for example is between 1500 dust to 5000 dusts, and the second trapezoidal height for example is between 50 dust to 1500 dusts.
In one embodiment of this invention, above-mentioned patterned conductive layer is a plurality of grids that constitute a plurality of active members.
In one embodiment of this invention, above-mentioned patterned conductive layer is a plurality of source electrodes and/or the drain electrode that constitutes a plurality of active members.
The present invention proposes a kind of manufacture method of initiative element array, comprises the following steps.At first, deposit the first bronze medal layer on substrate with first deposition rate.Then, deposit the second bronze medal layer on the first bronze medal layer with second deposition rate, wherein first deposition rate is greater than second deposition rate.Then, the patterning first bronze medal layer and the second bronze medal layer.
In one embodiment of this invention, behind the above-mentioned patterning first bronze medal layer and the second bronze medal layer, the first bronze medal layer for example is first trapezoidal at first section of the normal direction of the parallel first bronze medal layer, the second bronze medal layer for example is second trapezoidal at second section of the normal direction of the parallel first bronze medal layer, and the first trapezoidal base angle and the second trapezoidal base angle are that angle difference for example is the acute angle between 5 ° to 30 °.
In one embodiment of this invention, the above-mentioned deposition first bronze medal layer and the method for the second bronze medal layer comprise sputtering method.
In one embodiment of this invention, the first above-mentioned deposition rate is more than the twice of second deposition rate.
In one embodiment of this invention, before the above-mentioned deposition first bronze medal layer, also comprise deposit barrier layers on substrate, and the first bronze medal layer is to be deposited on the barrier layer.
The beneficial effect of the embodiment of the invention is, in the active component array base board proposed by the invention, because the first trapezoidal base angle in the section of copper layer and the second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle, so have preferable surface structure, therefore can avoid the generation of fault of construction effectively, and then improve electrical property efficiency.
In addition, in manufacture method of initiative element array proposed by the invention, because first deposition rate greater than second deposition rate, so the second bronze medal layer has preferable atomic arrangement, less film defects reaches lower oxidation rate, therefore can be improved the broken string ratio effectively.
Description of drawings
Figure 1A to Fig. 1 G is the manufacturing process profile according to the active component array base board of one embodiment of the invention.
Fig. 2 be patterned conductive layer 122 among Fig. 1 E along the profile of another profile direction, wherein the profile direction of the profile direction of Fig. 2 and Fig. 1 E is orthogonal.
[main element symbol description]
100: substrate
102,102a, 116,116a: barrier layer
104,104a, 106,106a, 118,118a, 120,120a: copper layer
108,122: patterned conductive layer
110: dielectric layer
112: channel layer
114,114a: ohmic contact layer
124: thin-film transistor
126: protective layer
128: opening
130: pixel electrode
N: normal direction
T1, T2, T3, T4: trapezoidal
θ 1, θ 2, θ 3, θ 4: angle
Embodiment
Figure 1A to Fig. 1 G is the manufacturing process profile according to the active component array base board of one embodiment of the invention.Fig. 2 be patterned conductive layer 122 among Fig. 1 E along the profile of another profile direction, wherein the profile direction of the profile direction of Fig. 2 and Fig. 1 E is orthogonal.
At first, please provide substrate 100 earlier with reference to Figure 1A.The material of substrate 100 for example is the combination of transparent material, opaque material, pliability material or above-mentioned material.
Then, optionally on substrate 100, form barrier layer 102.The material of barrier layer 102 for example is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.The formation method of barrier layer 102 for example is a physical vaporous deposition.
Then, with the first deposition rate copper layer 104 on barrier layer 102.The formation method of copper layer 104 for example is a sputtering method.
Next, on copper layer 104, wherein first deposition rate is greater than second deposition rate with the second deposition rate copper layer 106, and first deposition rate for example is more than the twice of second deposition rate.The formation method of copper layer 106 for example is a sputtering method.
Afterwards, please refer to Figure 1B, patterned copper layer 106, copper layer 104 and barrier layer 102, and on substrate 100, form in order to the patterned conductive layer 108 as grid.Patterned conductive layer 108 comprises copper layer 106, copper layer 104 and barrier layer 102 is carried out the patterning manufacturing process and copper layer 106a, the copper layer 104a and the barrier layer 102a that form.
In addition, copper layer 104a for example is trapezoidal T1 at the section of the normal direction N of parallel copper layer 104a, copper layer 106a for example is trapezoidal T2 at the section of the normal direction N of parallel copper layer 104a, and the base angle θ 1 of trapezoidal T1 and the base angle θ of trapezoidal T2 2 are that angle difference for example is the acute angle between 5 ° to 30 °.In one embodiment, the base angle θ 1 of trapezoidal T1 for example is between 7 ° to 13 ° with the angle difference of the base angle θ 2 of trapezoidal T2, for example 10 °.Wherein, base angle θ 1 for example is less than base angle θ 2.Base angle θ 1 for example is less than 70 °, and base angle θ 2 for example is less than 80 °.
In addition, the height of trapezoidal T1 for example is the height greater than trapezoidal T2.Wherein, the height of trapezoidal T1 for example is between 1500 dust to 5000 dusts, and the height of trapezoidal T2 for example is between 50 dust to 1500 dusts.
Be noted that so-called in this embodiment trapezoidal being meant " (substantially) substantially " is trapezoidal situation, that is so long as approximate trapezoid in appearance, promptly belong to alleged trapezoidal of this case.In addition, in this embodiment, trapezoidal base angle is prior art alleged " inclination angle (taper angle) ".
Then, please refer to Fig. 1 C, on substrate 100, form dielectric layer 110, with overlay pattern conductive layer 108.The formation method of dielectric layer 110 for example is that (chemical vapordeposition CVD) or other suitable film deposition techniques, but is not limited thereto by chemical vapour deposition technique.Dielectric layer 110 can be single layer structure or sandwich construction, and its material for example is inorganic material, other dielectric material or above-mentioned combination.The material of the dielectric layer 110 of present embodiment is to be that example describes with dielectric materials such as silica, silicon nitride or silicon oxynitrides.
Next, the channel layer 112 and the ohmic contact layer 114 of setting are piled up in formation on the dielectric layer above the patterned conductive layer 108 110.Channel layer 112 for example is the different semiconductor layer of doping content with ohmic contact layer 114.Channel layer 112 for example is to use suitable sedimentation and patterning method to form with the formation method of ohmic contact layer 114, does not repeat them here.
Afterwards, please refer to Fig. 1 D, optionally on substrate 100, form the barrier layer 116 that covers dielectric layer 110 and ohmic contact layer 114.The material of barrier layer 116 for example is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.The formation method of barrier layer 116 for example is a physical vaporous deposition.
Then, with the 3rd deposition rate copper layer 118 on barrier layer 116.The formation method of copper layer 118 for example is a sputtering method.
Next, on copper layer 118, wherein the 3rd deposition rate is greater than the 4th deposition rate with the 4th deposition rate copper layer 120, and the 3rd deposition rate for example is more than the twice of the 4th deposition rate.The formation method of copper layer 120 for example is a sputtering method.
Afterwards, please refer to Fig. 1 E, patterned copper layer 120, copper layer 118 and barrier layer 116, and above the channel layer 112 of patterned conductive layer 108 both sides, form patterned conductive layer 122 respectively as source electrode and drain electrode, and removable part ohmic contact layer 114 after forming patterned multilayer conductive layer 122 is to form ohmic contact layer 114a.Patterned conductive layer 122 comprises copper layer 120, copper layer 118 and barrier layer 116 is carried out the patterning manufacturing process and copper layer 120a, the copper layer 118a and the barrier layer 116a that form.
In addition, please in the lump with reference to Fig. 2, copper layer 118a for example is trapezoidal T3 at the section of the normal direction N of parallel copper layer 118a, copper layer 120a for example is trapezoidal T4 at the section of the normal direction N of parallel copper layer 118a, and the base angle θ 3 of trapezoidal T3 and the base angle θ of trapezoidal T4 4 are that angle difference for example is the acute angle between 5 ° to 30 °.In one embodiment, the base angle θ 3 of trapezoidal T3 for example is between 7 ° to 13 ° with the angle difference of the base angle θ 4 of trapezoidal T4, for example 10 °.Wherein, base angle θ 3 for example is less than base angle θ 4.Base angle θ 3 for example is less than 70 °, and base angle θ 4 for example is less than 80 °.
In addition, the height of trapezoidal T3 for example is the height greater than trapezoidal T4.Wherein, the height of trapezoidal T3 for example is between 1500 dust to 5000 dusts, and the height of trapezoidal T4 for example is between 50 dust to 1500 dusts.
So far, tentatively finish the making of thin-film transistor 124, thin-film transistor 124 comprises patterned conductive layer 108 (as grid), channel layer 112, ohmic contact layer 114a and patterned conductive layer 122 (as source electrode and drain electrode).
Then, please refer to Fig. 1 F, form protective layer 126 on thin-film transistor 124, wherein protective layer 126 has opening 128, and opening 128 exposes in the patterned conductive layer 122 as the part that drains.Wherein, protective layer 126 can be single layer structure or sandwich construction, and its material comprises inorganic material, organic material, other dielectric material or above-mentioned combination.When the material of protective layer 126 is inorganic material as silicon nitride or silica; formation method with protective layer 126 of opening 128 for example is earlier to form protective material layer (not shown) with chemical vapour deposition technique on substrate 100 comprehensively, again the protective material layer is carried out the patterning manufacturing process afterwards and forms.
Afterwards, please refer to Fig. 1 G, on protective layer 126, form pixel electrode 130, and pixel electrode 130 electrically connects by the part as drain electrode in the patterned conductive layer 122 of opening 128 and thin-film transistor 124.Pixel electrode 130 can be single layer structure or sandwich construction, and its material for example is transparent material, non-transparent material or above-mentioned combination.Present embodiment is that the transparent material with indium tin oxide and/or indium-zinc oxide is that example describes, but is not limited thereto.The formation method of pixel electrode 130 for example is to be formed at the pixel electrode layer (not shown) by sputtering method on protective layer 126, again pixel electrode layer is carried out the patterning manufacturing process and forms.
By the foregoing description as can be known, deposition rate compared to copper layer 104a, 118a, because it is slower to be covered in the deposition rate of copper layer 106a, 120a on copper layer 104a, the 118a respectively, so copper layer 106a, 120a have preferable atomic arrangement, less film defects reaches lower oxidation rate, therefore can reduce the broken string ratio in the active component array base board significantly.
It should be noted that, though in the above-described embodiments, the formation method of above-mentioned patterned conductive layer is to be that example describes to be respectively applied for the grid (patterned conductive layer 108), source electrode and the drain electrode (patterned conductive layer 122) that form in the active component array base board, but does not limit with this.That is to say, if the grid in the active component array base board, scan line, source electrode, drain electrode, data wire, other plain conductor, and other metal electrode in any one be to use the formation method manufacturing of above-mentioned patterned conductive layer, all belong to the scope that manufacture method contained of active component array base board of the present invention.
Below, the active component array base board of one embodiment of the present of invention is described by Fig. 1 G.This active cell array can be applicable to LCD (liquid crystal display substantially, LCD), LCD-Organic Light Emitting Diode (liquid crystal display-organic light emittingdiode, TFT-OLED), Electronic Paper or other products.
Please refer to Fig. 1 G, active component array base board has at least one patterned conductive layer.Patterned conductive layer comprises the copper layer.Copper layer in the patterned conductive layer can be single layer structure or sandwich construction, as long as the copper layer is trapezoidally to constitute by two that pile up at the section of the normal direction of parallel copper layer, and these two trapezoidal base angles are angle difference between 5 ° to 30 ° acute angle, promptly belong to the scope that active component array base board of the present invention is contained.
Active component array base board with Fig. 1 G is an example, and the patterned conductive layer in the active component array base board for example is to reach in order to the patterned conductive layer 122 as source electrode and drain electrode in order to the patterned conductive layer 108 as grid.Wherein, the copper layer in the patterned conductive layer 108 is piled up the two-layer structure that forms by copper layer 104a, 106a, and the copper layer in the patterned conductive layer 122 for example is the two-layer structure that is stacked into by copper layer 118a, 120a, but not in order to restriction the present invention.
The copper layer of patterned conductive layer 108 for example is to be made of trapezoidal T1 (section of copper layer 104a) and the trapezoidal T2 (section of copper layer 106a) that is stacked on the trapezoidal T1 at the section of the normal direction N of parallel copper layer, and the base angle θ 1 of trapezoidal T1 and the base angle θ of trapezoidal T2 2 are that angle difference for example is the acute angle between 5 ° to 30 °.In one embodiment, the base angle θ 1 of trapezoidal T1 for example is between 7 ° to 13 ° with the angle difference of the base angle θ 2 of trapezoidal T2, for example 10 °.Wherein, base angle θ 1 for example is less than base angle θ 2.Base angle θ 1 for example is less than 70 °, and base angle θ 2 for example is less than 80 °.In addition, the height of trapezoidal T1 for example is the height greater than trapezoidal T2.Wherein, the height of trapezoidal T1 for example is between 1500 dust to 5000 dusts, and the height of trapezoidal T2 for example is between 50 dust to 1500 dusts.
Please in the lump with reference to Fig. 2, the copper layer of patterned conductive layer 122 for example is to be made of trapezoidal T3 (section of copper layer 118a) and the trapezoidal T4 (section of copper layer 120a) that is stacked on the trapezoidal T3 at the section of the normal direction N of parallel copper layer, and the base angle θ 3 of trapezoidal T3 and the base angle θ of trapezoidal T4 4 are that angle difference for example is the acute angle between 5 ° to 30 °.In one embodiment, the base angle θ 3 of trapezoidal T3 for example is between 7 ° to 13 ° with the angle difference of the base angle θ 4 of trapezoidal T4, for example 10 °.Wherein, base angle θ 3 for example is less than base angle θ 4.Base angle θ 3 for example is less than 70 °, and base angle θ 4 for example is less than 80 °.In addition, the height of trapezoidal T3 for example is the height greater than trapezoidal T4.Wherein, the height of trapezoidal T3 for example is between 1500 dust to 5000 dusts, and the height of trapezoidal T4 for example is between 50 dust to 1500 dusts.
In addition, patterned conductive layer 108,122 also can comprise barrier layer 102a, 116a respectively.Copper layer 104a is stacked on the barrier layer 102a, and copper layer 118a is stacked on the barrier layer 116a.The material of barrier layer 102a, 116a for example is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.
In addition; active component array base board also comprises members such as substrate 100, dielectric layer 110, channel layer 112, ohmic contact layer 114a, protective layer 126 and pixel electrode 130; yet the configuration mode of these members, material and formation method at large illustrate in the embodiment of preamble, so do not repeat them here.
Based on above-mentioned, in active component array base board proposed by the invention, because the base angle θ 1 (or θ 3) of the trapezoidal T1 (or T3) in the section of copper layer and the base angle θ 2 (or θ 4) of trapezoidal T2 (or T4) are angle difference between 5 ° to 30 ° acute angle, so have preferable surface structure, therefore can prevent the appearance of fault of construction effectively, and then improve electrical property efficiency.
Though, patterned conductive layer in the present embodiment is being that example describes as the grid in the active array substrate (patterned conductive layer 108), source electrode and drain electrode (patterned conductive layer 122), yet so long as the grid in the active array substrate, scan line, source electrode, drain electrode, data wire, other plain conductor, and other metal electrode in any one be the structure of above-mentioned patterned conductive layer, all belong to the scope that the present invention is contained.
Table 1 is the comparison sheet of prior art and copper conductor outage of the present invention.
Table 1
In table 1, comparative example 1,2 only carries out a fast deposition by high power and forms the copper layer when copper metal film forming, and therefore after forming copper conductor, it is single trapezoidal that section is in that the copper layer is carried out patterning, and outage is higher.
Experimental example 1,2,3 is when copper metal film forming, be earlier to carry out a fast deposition and form after lower floor's copper layer with high power, (its power is high-power three/Shu) once to deposit at a slow speed and form upper copper layer with low-power again, and upper copper layer is stacked on lower floor's copper layer and forms the copper stack layer, therefore in that the copper stack layer is carried out patterning after forming copper conductor, it is two overlapping trapezoidal that section is, and outage is lower.
In sum, the foregoing description has following advantage at least:
1. above-mentioned manufacture method of initiative element array can be improved the broken string ratio effectively.
2. above-mentioned active component array base board has preferable electrical property efficiency.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (14)
1. active component array base board, it is characterized in that, described active component array base board has at least one patterned conductive layer, described patterned conductive layer comprises a bronze medal layer, described copper layer a section of a normal direction of parallel copper layer be by one first trapezoidal be stacked in first one second on trapezoidal and trapezoidally constitute, the described first trapezoidal base angle and the described second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle.
2. active component array base board according to claim 1 is characterized in that, the angle difference at the described first trapezoidal base angle and the described second trapezoidal base angle is between 7 ° to 13 °.
3. active component array base board according to claim 1 is characterized in that, the angle difference at the described first trapezoidal base angle and the described second trapezoidal base angle is 10 °.
4. active component array base board according to claim 1 is characterized in that described patterned conductive layer also comprises a barrier layer, and described copper is layered on the described barrier layer.
5. active component array base board according to claim 4 is characterized in that, the material of described barrier layer is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.
6. active component array base board according to claim 1 is characterized in that, described first is trapezoidal tall and big in the described second trapezoidal height.
7. active component array base board according to claim 1 is characterized in that, the described first trapezoidal height is between 1500 dust to 5000 dusts, and the described second trapezoidal height is between 50 dust to 1500 dusts.
8. active component array base board according to claim 1 is characterized in that, described patterned conductive layer is a plurality of grids that constitute a plurality of active members.
9. active component array base board according to claim 1 is characterized in that, described patterned conductive layer is a plurality of source electrodes and/or the drain electrode that constitutes a plurality of active members.
10. a manufacture method of initiative element array is characterized in that, described manufacture method comprises:
Deposit one first bronze medal layer on a substrate with one first deposition rate;
Deposit one second bronze medal layer on the described first bronze medal layer with one second deposition rate, wherein said first deposition rate is greater than described second deposition rate; And
Described first bronze medal layer of patterning and the described second bronze medal layer.
11. manufacture method of initiative element array according to claim 10, it is characterized in that, behind described first bronze medal layer of patterning and the described second bronze medal layer, the described first bronze medal layer is one first trapezoidal at one first section of a normal direction of the parallel first bronze medal layer, the described second bronze medal layer is one second trapezoidal at one second section of the normal direction of the parallel first bronze medal layer, and the described first trapezoidal base angle and the described second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle.
12. manufacture method of initiative element array according to claim 10 is characterized in that, the method that deposits described first bronze medal layer and the described second bronze medal layer comprises sputtering method.
13. manufacture method of initiative element array according to claim 10 is characterized in that, described first deposition rate is more than the twice of described second deposition rate.
14. manufacture method of initiative element array according to claim 10 is characterized in that, before the deposition first bronze medal layer, also comprise deposition one barrier layer on substrate, and the described first bronze medal layer is to be deposited on the described sun barrier layer.
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| CN201010161952A CN101814460A (en) | 2010-04-15 | 2010-04-15 | Active element array substrate and manufacturing method thereof |
| CN 201010258199 CN101969070B (en) | 2010-04-15 | 2010-08-18 | Active element array substrate and manufacturing method thereof |
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| WO2017071023A1 (en) * | 2015-10-28 | 2017-05-04 | 深圳市华星光电技术有限公司 | Thin-film transistor, and array substrate, and manufacturing method therefor |
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| CN102956505B (en) * | 2012-11-19 | 2015-06-17 | 深圳市华星光电技术有限公司 | Manufacture method for switching tube and array substrate |
| CN105529335A (en) * | 2015-12-17 | 2016-04-27 | 武汉华星光电技术有限公司 | Array substrate and fabrication method thereof and display panel |
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| US6909114B1 (en) * | 1998-11-17 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having LDD regions |
| CN100501942C (en) * | 2006-04-06 | 2009-06-17 | 友达光电股份有限公司 | Method for forming inclined conductive layer |
| US7847905B2 (en) * | 2007-11-07 | 2010-12-07 | Hydis Technologies Co., Ltd. | FFS mode LCD and method of manufacturing the same |
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