CN101794161A - Computer system and overlocking method thereof - Google Patents
Computer system and overlocking method thereof Download PDFInfo
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- CN101794161A CN101794161A CN200910007109A CN200910007109A CN101794161A CN 101794161 A CN101794161 A CN 101794161A CN 200910007109 A CN200910007109 A CN 200910007109A CN 200910007109 A CN200910007109 A CN 200910007109A CN 101794161 A CN101794161 A CN 101794161A
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Abstract
The invention relates to a computer system which comprises a clock pulse generator, a system chip, a controller and a multiplex unit, wherein the clock pulse generator sets a plurality of set values in a clock according to a frequency to generate a reference clock pulse; the system chip is used for generating a first clock pulse control message and a first clock pulse; the controller is used for switching a level of a control signal and generating a second clock pulse control message and a second clock pulse; and the multiplex unit is used for receiving the control signal to select the first clock pulse control message or the second clock pulse control message as a main clock pulse control message and the first clock pulse or the second clock pulse as a main clock pulse. Thus, the clock pulse generator regulates a plurality of set values according to the main clock pulse control message and the main clock pulse so as to change the frequency of the reference clock pulse.
Description
Technical field
The invention relates to a kind of computer system and its frequency multiplying method, and particularly utilize hardware to control or software set is carried out computer system and its frequency multiplying method of overclocking relevant for a kind of.
Background technology
Usually all have a clock pulse generator (clock generator) in the computer system, (central processor unit CPU) uses to the CPU (central processing unit) on the mainboard so that different work time pulses to be provided.In the setting of the work time pulse of CPU (central processing unit), the user tends to the frequency with the work time pulse of CPU (central processing unit) in order to pare down expenses, be promoted to and be higher than the preset value that manufacturer sets, be general so-called overclocking (overclocking), to improve the processing speed of CPU (central processing unit).
Known overclocking mode approximately is divided into several.Overclocking mode the earliest is that the user need take the casing of computer system apart, utilizes the wire jumper of adjusting on the mainboard then, changes the frequency of the clock pulse of computer system.Yet this mode causes the sizable inconvenience of user.In addition, in the action of dismounting casing and adjustment mainboard, once the element of not noting to damage other.
Skillful along with semiconductor technology, the wire jumper on mainboard electronic switch mostly replaces.Therefore at present to the overclocking of computer system, carry out in the mode that can utilize software set.With present, utilize software to come computer system is carried out the mode that overclocking is set, can be divided into again in the setting pattern of Basic Input or Output System (BIOS) and setting, or under operating system, carry out dynamic overclocking.
Yet, no matter be in the setting pattern of Basic Input or Output System (BIOS), to carry out, or under operating system, utilize the mode of executive utility to carry out overclocking, the overclocking mode of software set all still has certain complexity.Because the user must just can finish the action of overclocking by a series of operating and setting.
Summary of the invention
The invention provides a kind of computer system, utilize multiplex (MUX) unit switched system chip and controller control, control or the overclocking mode of software set, adjust the processing speed of CPU (central processing unit) to utilize hardware to clock pulse generator.
The invention provides a kind of frequency multiplying method of computer system, optionally utilize hardware to control or the mode of software set is carried out overclocking.When the mode of controlling with hardware is carried out overclocking, can exempt the complicated setting step on software set.
The present invention proposes a kind of computer system, comprises a clock pulse generator, a System on Chip/SoC, a controller and a multiplex (MUX) unit.Wherein, a plurality of setting values in the clock pulse generator foundation one frequency setting table, and produce a benchmark clock pulse according to this.System on Chip/SoC is in order to produce one first clock pulse control message and one first clock pulse.Controller is in order to switching the level of a control signal, and in order to produce one second clock pulse control message and one second clock pulse.The multiplex (MUX) unit is in order to receiving control signal, selecting an output with as a main clock pulse control message from first and second clock pulse control message, and selects an output with as a main clock pulse from first and second clock pulse.Wherein, clock pulse generator is to adjust a plurality of setting values according to main clock pulse control message and main clock pulse, with the frequency of change benchmark clock pulse.
In one embodiment of this invention, above-mentioned computer system also comprises user's interface.Wherein, user's interface electrically connects controller, and in order to produce an operation signal.On the other hand, when controller detected operation signal, controller was with the level of switch-over control signal, and the follow-up operation signal that detects of foundation produces second clock pulse control message and second clock pulse.
In one embodiment of this invention, above-mentioned user's interface comprises a knob, and user's interface is to come the setting operation signal according to the direction that knob is rotated.
In one embodiment of this invention, above-mentioned user's interface comprises a plurality of buttons, and user's interface is to come the setting operation signal according to the state that these buttons are pressed.
In one embodiment of this invention, above-mentioned computer system also comprises a CPU (central processing unit).Wherein, CPU (central processing unit) is in order to receiving the benchmark clock pulse, and the benchmark clock pulse is carried out frequency multiplication, to produce a work time pulse.
From another viewpoint, the present invention proposes a kind of frequency multiplying method of computer system, and comprises the following steps.At first, provide a benchmark clock pulse according to a plurality of setting values in the frequency setting table, and one first clock pulse control message and one first clock pulse are provided.Then, switch the level of a control signal, and one second clock pulse control message and one second clock pulse are provided.Afterwards,, from first and second clock pulse control message, choose one as a main clock pulse control message, and from first and second clock pulse, choose one as a main clock pulse with reference to the level of control signal.By this, will adjust a plurality of setting values, with the frequency of change benchmark clock pulse according to main clock pulse control message and main clock pulse.
Based on above-mentioned, the present invention utilizes the multiplex (MUX) unit to come switched system chip and the controller control to clock pulse generator, to reach the overclocking mode that software set or hardware are controlled respectively.What deserves to be mentioned is that the present invention be except can providing diversified overclocking mode, and the overclocking mode that can utilize hardware to control exempts the complicated setting step on the software set, and then help the user in operational convenience.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the circuit box synoptic diagram according to the computer system of one embodiment of the invention.
Figure 2 shows that frequency multiplying method process flow diagram according to the computer system of one embodiment of the invention.
Embodiment
Fig. 1 is the circuit box synoptic diagram according to the computer system of one embodiment of the invention.With reference to Fig. 1, computer system 100 comprises a clock pulse generator 110, a System on Chip/SoC 120, a controller 130, a multiplex (MUX) unit 140, user's interface 150 and a CPU (central processing unit) 160.
In whole start, clock pulse generator 110 is according to a plurality of setting values in the frequency setting table, and produces a benchmark clock pulse CLK22 according to this.On the other hand, CPU (central processing unit) 160 can receive benchmark clock pulse CLK22, and received benchmark clock pulse CLK22 is carried out frequency multiplication, to produce a work time pulse.In other words, computer system 100 can be changed the work time pulse of CPU (central processing unit) 160 by the setting of benchmark clock pulse CLK22, and then adjusts the processing speed of CPU (central processing unit) 160.
In the setting of benchmark clock pulse CLK22, clock pulse generator 110 is according to a main clock pulse CLK21 and a main clock pulse control message D21, a plurality of setting values in the setting table of adjusting frequency.Relatively, along with resetting of these setting values, the frequency of the benchmark clock pulse CLK22 that clock pulse generator 110 is produced also will change thereupon.
It should be noted that present embodiment is the control of coming switched system chip 120 and 130 pairs of clock pulse generators 110 of controller by multiplex (MUX) unit 140.Therefore, main clock pulse CLK21 and main clock pulse control message D21 that clock pulse generator 110 is received are to be provided by System on Chip/SoC 120 or controller 130.Usually know that in order to cause this area to have the knowledgeable more understands present embodiment, below will do further explanation at the System on Chip/SoC 120 and the control of 130 pairs of clock pulse generators 110 of controller.
Please continue with reference to Fig. 1, System on Chip/SoC 120 can be South Bridge chip, or any can be in order to produce chip/assembly that clock pulse and clock pulse control information reach, it is in order to produce one first clock pulse control message D11 and one first clock pulse CLK11, and transmit the first clock pulse control message D11 and the first clock pulse CLK11 to multiplex (MUX) unit 140 by System Management Bus (System Management Bus, SM Bus).In addition, controller 130 can be embedded controller, and it is in order to switching the level of a control signal S11, and in order to produce one second clock pulse control message D12 and one second clock pulse CLK12.Wherein, controller 130 also is to transmit the second clock pulse control message D12 and the second clock pulse CLK12 to multiplex (MUX) unit 140 by System Management Bus, and (General Purpose Input Output, GPIO) pin is exported control signal S11 to pass through general input and output.
On the other hand, in the present embodiment, multiplex (MUX) unit 140 comprises a switch SW 1 and a switch SW 2.Wherein, the first end TM11 of switch SW 1 is electrically connected to System on Chip/SoC 120, to receive the first clock pulse control message D11.The second end TM12 of switch SW 1 is electrically connected to controller 130, to receive the second clock pulse control message D12.The 3rd end TM13 of switch SW 1 then is electrically connected to clock pulse generator 110.Moreover the first end TM21 of switch SW 2 is electrically connected to System on Chip/SoC 120, to receive the first clock pulse CLK11.The second end TM22 of switch SW 2 is electrically connected to controller 130, to receive the second clock pulse CLK12.The 3rd end TM23 of switch SW 2 then is electrically connected to clock pulse generator 110.
In integrated operation, switch SW 1 all is the control signal S11 that is produced according to controller 130 with switch SW 2, controls the conducting state of its end points.For instance, table () is the source table of comparisons of main clock pulse CLK21 and main clock pulse control message D21.
| ??S11＝0 | ??S11＝1 | |
| ??D21 | ??D11 | ??D12 |
| ??CLK21 | ??CLK11 | ??CLK12 |
Table (one)
Shown in table (), when the level of control signal S11 is switched to logical zero, the 3rd end TM13 of switch SW 1 and the first end TM11 are sent to mutual conduction clock pulse generator 110 to cause the first clock pulse control message D11, and are regarded as main clock pulse control message D21.In addition, the 3rd end TM23 of switch SW 2 and the first end TM21 are sent to mutual conduction clock pulse generator 110 to cause the first clock pulse CLK11, and are regarded as main clock pulse CLK21.In other words, Ci Shi clock pulse generator 110 is to be controlled by System on Chip/SoC 120.Therefore, the user can change the frequency of benchmark clock pulse CLK22 by the overclocking mode of software set in the setting pattern of Basic Input or Output System (BIOS) or under operating system, and then reaches the purpose of the processing speed of adjusting CPU (central processing unit) 160.
On the other hand, when the level of control signal S11 was switched to logical one, the 3rd end TM13 of switch SW 1 and the second end TM12 were sent to mutual conduction clock pulse generator 110 to cause the second clock pulse control message D12, and are regarded as main clock pulse control message D21.In addition, the 3rd end TM23 of switch SW 2 and the second end TM22 are sent to mutual conduction clock pulse generator 110 to cause the second clock pulse CLK12, and are regarded as main clock pulse CLK21.In other words, Ci Shi clock pulse generator 110 is to be controlled by controller 130.
It should be noted that in the present embodiment user's interface 150 electrically connects controller 130, and in order to produce an operation signal S12.By this, controller 130 will decide its control signal S11 that produces, the second clock pulse CLK12 and the second clock pulse control message D12 according to the operation signal S12 from user's interface 150.
For instance, in the present embodiment, the control right of priority (priority) of 130 pairs of clock pulse generators 110 of controller is set to 1.Therefore, when controller 130 on detection of during operation signal S12, it will switch to logical one with the level of control signal S11, is controlled by controller 130 to cause clock pulse generator 110.Then, controller 130 will produce the second clock pulse control message D12 and the second clock pulse CLK12 according to the follow-up operation signal S12 that detects.
What deserves to be mentioned is that the described user's interface 150 of present embodiment comprises a plurality of operating parts, and these operating parts for example are knob or button.When user's interface 150 included operating parts were knob, user directly rotary knob came setting operation signal S12, to control clock pulse generator 110 by controller 130.In other words, when user's desire is adjusted the processing speed of CPU (central processing unit) 160, originally the user can be earlier rotates knob in user's interface 150 with clockwise or counterclockwise, switches to the control with clock pulse generator 110 and controls in controller 130.
Afterwards, when the knob counterclockwise in user's interface 150 is rotated, controller 130 will send the corresponding second clock pulse control message D12 and the second clock pulse CLK12, and cause the frequency of benchmark clock pulse CLK22 to descend.Otherwise when the knob in user's interface 150 is rotated clockwise, controller 130 will send the corresponding second clock pulse control message D12 and the second clock pulse CLK12, and cause the frequency upgrading of benchmark clock pulse CLK22.
On the other hand, when user's interface 150 included operating parts are button, the user then can by different key push setting operation signal S12, to control clock pulse generator 110 by controller 130.For instance, if comprising respectively, user's interface 150 controls buttons frequently in order to two of frequency reducing and raising frequency.When user's desire was adjusted the processing speed of CPU (central processing unit) 160, originally the user can push the two controls one of button frequently earlier, switched to the control with clock pulse generator 110 and controlled in controller 130.Afterwards, the user can directly push the two controls one of button frequently, cause controller 130 to produce the corresponding second clock pulse control message D12 and the second clock pulse CLK12, and then the frequency of change benchmark clock pulse CLK22.
In other words, when clock pulse generator 110 is controlled by controller 130, the user can be directly by the controlling of operating parts in user's interface 150 (for example: knob or button), adjust the processing speed of CPU (central processing unit) 160.At this moment, the user can exempt the complicated setting step on software set, change the processing speed that the overclocking mode of controlling with hardware is adjusted CPU (central processing unit) 160.
Figure 2 shows that frequency multiplying method process flow diagram according to the computer system of one embodiment of the invention.With reference to Fig. 2, at first,, provide a benchmark clock pulse according to a plurality of setting values in the frequency setting table in step S210.Afterwards, in step S220, provide one first clock pulse control message and one first clock pulse.Then, in step S230, switch the level of a control signal, and one second clock pulse control message and one second clock pulse are provided.
By this, in step S240, can from first clock pulse control message and second clock pulse control message, choose one as a main clock pulse control message with reference to the level of control signal, and from first clock pulse and second clock pulse, choose one as a main clock pulse.Thus, the described frequency multiplying method of present embodiment can pass through step S250, adjust a plurality of setting values according to main clock pulse control message and main clock pulse, frequency with change benchmark clock pulse, and, the benchmark clock pulse is carried out frequency multiplication, to produce a work time pulse by step S260.Thin portion flow process as for the described frequency multiplying method of present embodiment is included in the various embodiments described above, so do not repeat them here.
In sum, the present invention utilizes the multiplex (MUX) unit to come switched system chip and the controller control to clock pulse generator.When clock pulse generator is when being controlled by System on Chip/SoC, the user can utilize the overclocking mode of software set to adjust the processing speed of CPU (central processing unit).On the other hand, when clock pulse generator is when being controlled by controller, the user then can be by the operating parts (for example: knob or button) in user's interface, the overclocking mode of utilizing hardware to control is adjusted the processing speed of CPU (central processing unit), and then exempts the complicated setting step on software set.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (13)
1. a computer system is characterized in that, comprising:
Clock pulse generator according to a plurality of setting values in the frequency setting table, and produces the benchmark clock pulse according to this;
System on Chip/SoC is in order to produce first clock pulse control message and first clock pulse;
Controller, in order to the level of switch-over control signal, and in order to produce second clock pulse control message and second clock pulse; And
The multiplex (MUX) unit, in order to receiving above-mentioned control signal, with from above-mentioned first with above-mentioned second clock pulse control message select an output with as main clock pulse control message, and from above-mentioned first with above-mentioned second clock pulse select an output with as main clock pulse,
Wherein, above-mentioned clock pulse generator is to adjust above-mentioned these setting values according to above-mentioned main clock pulse control message and above-mentioned main clock pulse, with the frequency of change said reference clock pulse.
2. computer system according to claim 1 is characterized in that, also comprises:
User's interface electrically connects above-mentioned controller, in order to produce operation signal;
Wherein, when above-mentioned controller detects the aforesaid operations signal, above-mentioned controller will switch the level of above-mentioned control signal, and produce above-mentioned second clock pulse control message and above-mentioned second clock pulse according to the follow-up aforesaid operations signal that detects.
3. computer system according to claim 2 is characterized in that, wherein above-mentioned user's interface comprises knob, and above-mentioned user's interface is to set the aforesaid operations signal according to the direction that above-mentioned knob is rotated.
4. computer system according to claim 2 is characterized in that, wherein above-mentioned user's interface comprises a plurality of buttons, and above-mentioned user's interface is to set the aforesaid operations signal according to the state that above-mentioned these buttons are pressed.
5. computer system according to claim 1 is characterized in that, also comprises:
CPU (central processing unit) in order to receiving the said reference clock pulse, and is carried out frequency multiplication to the said reference clock pulse, to produce work time pulse.
6. computer system according to claim 1 is characterized in that, wherein above-mentioned multiplex (MUX) unit comprises:
First switch, have in order to first end that receives above-mentioned first clock pulse control message, in order to second end that receives above-mentioned second clock pulse control message and the 3rd end that electrically connects above-mentioned clock pulse generator, wherein above-mentioned first switch is extremely first end or second end of above-mentioned first switch of the 3rd end conducting that will above-mentioned first switch according to above-mentioned control signal; And
Second switch, have in order to first end that receives above-mentioned first clock pulse, in order to second end that receives above-mentioned second clock pulse and the 3rd end that electrically connects above-mentioned clock pulse generator, wherein above-mentioned second switch is according to above-mentioned control signal and with the 3rd end conducting of above-mentioned second switch first end or second end to above-mentioned second switch.
7. computer system according to claim 1 is characterized in that, wherein the said system chip transmits above-mentioned first clock pulse control message and above-mentioned first clock pulse to above-mentioned multiplex (MUX) unit by first System Management Bus.
8. computer system according to claim 1, it is characterized in that, wherein above-mentioned controller transmits above-mentioned second clock pulse control message and above-mentioned second clock pulse to above-mentioned multiplex (MUX) unit by second System Management Bus, and exports above-mentioned control signal by general input and output pin.
9. computer system according to claim 1 is characterized in that, wherein the said system chip is a South Bridge chip.
10. computer system according to claim 1 is characterized in that, wherein above-mentioned controller is an embedded controller.
11. the frequency multiplying method of a computer system is characterized in that, comprising:
Provide the benchmark clock pulse according to a plurality of setting values in the frequency setting table;
First clock pulse control message and first clock pulse are provided;
The level of switch-over control signal, and second clock pulse control message and second clock pulse are provided;
With reference to the level of above-mentioned control signal, from above-mentioned first with above-mentioned second clock pulse control message choose one as main clock pulse control message, and from above-mentioned first with above-mentioned second clock pulse choose one as main clock pulse; And
Adjust above-mentioned these setting values according to above-mentioned main clock pulse control message and above-mentioned main clock pulse, with the frequency of change said reference clock pulse.
12. the frequency multiplying method of computer system according to claim 11 is characterized in that, wherein switches the level of above-mentioned control signal, and provides the step of above-mentioned second clock pulse control message and above-mentioned second clock pulse to comprise:
Provide operation signal by user's interface; And
When detecting the aforesaid operations signal, switch the level of above-mentioned control signal, and provide above-mentioned second clock pulse control message and above-mentioned second clock pulse according to the follow-up aforesaid operations signal that detects.
13. the frequency multiplying method of computer system according to claim 11 is characterized in that, also comprises:
The said reference clock pulse is carried out frequency multiplication, to produce work time pulse.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009100071097A CN101794161B (en) | 2009-02-02 | 2009-02-02 | Computer system and overclocking method thereof |
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| CN2009100071097A CN101794161B (en) | 2009-02-02 | 2009-02-02 | Computer system and overclocking method thereof |
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| CN101794161A true CN101794161A (en) | 2010-08-04 |
| CN101794161B CN101794161B (en) | 2012-11-07 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467153A (en) * | 2010-11-18 | 2012-05-23 | 精英电脑股份有限公司 | Frequency modulating method executed in operating system |
| CN102467475A (en) * | 2010-10-28 | 2012-05-23 | 英业达股份有限公司 | Computer system |
| CN104216857A (en) * | 2013-05-31 | 2014-12-17 | 英业达科技有限公司 | Multiplexing switching device and method |
| CN105843370A (en) * | 2016-05-31 | 2016-08-10 | 合肥联宝信息技术有限公司 | Electronic device and power saving control method thereof |
| CN105938387A (en) * | 2016-04-16 | 2016-09-14 | 合肥博雷电气有限公司 | Ultrahigh frequency superconductive modulator |
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| US5579353A (en) * | 1993-10-12 | 1996-11-26 | Texas Instruments Incorporated | Dynamic clock mode switch |
| EP1338948A1 (en) * | 2002-02-25 | 2003-08-27 | Hewlett Packard Company, a Delaware Corporation | Clock control arrangement for a computing system |
| CN1605972A (en) * | 2003-10-06 | 2005-04-13 | 华邦电子股份有限公司 | Supply voltage control circuit of central processing unit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5579353A (en) * | 1993-10-12 | 1996-11-26 | Texas Instruments Incorporated | Dynamic clock mode switch |
| EP1338948A1 (en) * | 2002-02-25 | 2003-08-27 | Hewlett Packard Company, a Delaware Corporation | Clock control arrangement for a computing system |
| CN1605972A (en) * | 2003-10-06 | 2005-04-13 | 华邦电子股份有限公司 | Supply voltage control circuit of central processing unit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467475A (en) * | 2010-10-28 | 2012-05-23 | 英业达股份有限公司 | Computer system |
| CN102467475B (en) * | 2010-10-28 | 2014-10-08 | 英业达股份有限公司 | Computer system |
| CN102467153A (en) * | 2010-11-18 | 2012-05-23 | 精英电脑股份有限公司 | Frequency modulating method executed in operating system |
| CN104216857A (en) * | 2013-05-31 | 2014-12-17 | 英业达科技有限公司 | Multiplexing switching device and method |
| CN104216857B (en) * | 2013-05-31 | 2017-09-22 | 英业达科技有限公司 | Multiplexing switching device and its switching method |
| CN105938387A (en) * | 2016-04-16 | 2016-09-14 | 合肥博雷电气有限公司 | Ultrahigh frequency superconductive modulator |
| CN105843370A (en) * | 2016-05-31 | 2016-08-10 | 合肥联宝信息技术有限公司 | Electronic device and power saving control method thereof |
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| Publication number | Publication date |
|---|---|
| CN101794161B (en) | 2012-11-07 |
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