CN101783367B - Nanowire MOS transistor based on III-V element and preparation method thereof - Google Patents

Nanowire MOS transistor based on III-V element and preparation method thereof Download PDF

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CN101783367B
CN101783367B CN201010111275A CN201010111275A CN101783367B CN 101783367 B CN101783367 B CN 101783367B CN 201010111275 A CN201010111275 A CN 201010111275A CN 201010111275 A CN201010111275 A CN 201010111275A CN 101783367 B CN101783367 B CN 101783367B
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iii
preparation
mos transistor
annealing
nanowire
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CN101783367A (en
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刘晗
顾晶晶
王鹏飞
张卫
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Fudan University
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Fudan University
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Abstract

The invention belongs to the technical field of micro-electronics, particularly disclosing a nanowire MOS transistor and a preparation method thereof. The nanowire MOS transistor uses metallic nickel to serve as the drain and source diffusion material of III-V semiconductor nanowire and utilizes the nickel diffusion mechanism under high temperature to ensure that metallic nickel diffuses to III-V material; formed low-resistance Ni-III-V alloy serves as the drain and source diffusion material of the III-V semiconductor nanowire MOS pipe so as to realize ohmic contact between the drain and source material and channel material. The MOS transistor disclosed by the invention has the advantages of simple structure, convenient manufacture, small contact resistance and the like, can effectively lower the possibility of producing parasitic capacitance and effectively lowers the cut-off current of the MOS transistor. Meanwhile, the invention also discloses a preparation method of the nanowire MOS transistor, can effectively control the channel length of the MOS transistor so as to ensure that a semiconductor device has larger operating current.

Description

A kind of nanowire MOS transistor based on III-V element and preparation method thereof
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of mos transistor structure and preparation method thereof, particularly a kind of based on Ni xThe nanowire MOS transistor structure of-III-V element simultaneously, the invention allows for said based on Ni xThe manufacturing approach of the nanowire MOS transistor structure of-III-V element.
Background technology
The transistor (abbreviation MOS transistor) of conventional Metal-oxide-semicondutor (Metal-Oxide-Semiconductor) structure is that the method that adopts ion to inject forms source region and drain region, adopts heavily doped polysilicon to do grid.Therefore, need carry out high temperature (about 1000 ℃) after annealing and handle and activate doping, inject the lattice damage that causes, reduce contact resistance to eliminate ion.Yet so high processing temperature can cause the diffusion again of source region and drain region doping (boron or phosphorus), thereby causes the variation of junction depth and channel length, finally causes device performance off-design standard.Especially along with device feature size narrows down to below 50 nm technology node; The junction depth in source region and drain region and channel length all get into nanometer scale; And adopting conventional method can't realize ultra shallow junction source region and drain region, this has brought very big challenge for the processing of small size device.
In recent years, one-dimensional nano structure, for example nanotube, nano wire, nano belt etc. because they are yardstick and the physics of dimension decision and the ideal system of chemical property, have caused people's extensive studies interest.Based on its unique physicochemical characteristics, the concern to the one dimension semiconductor nano wire now also increases gradually, and it is considered to might be the basic composition element of following integrated circuit.III-V family material semiconductor nanowires, like GaAs, InAs, InGaAs, InP etc. are because its higher electron mobility has obtained extensive attention.But owing to reducing of its contact area, the source of based semiconductor nanowire MOS transistor is leaked manufacturing technology and is remained one of great challenge.The source drain contact of nanoscale not only need obtain lower contact resistance, and need reduce parasitic capacitance.Leak in the manufacturing in source at existing nano-wire transistor, just utilizes two metal electrodes of photoetching making at the two ends of nano wire usually, reduces its contact resistance through subsequent anneal then.This method not only receives the restriction of lithographic accuracy and can't reduce channel length, and the parasitic capacitance that has also increased device is leaked in large-area source.In addition, wherein heat treatment has also improved the cost in making.
Summary of the invention
The objective of the invention is to propose a kind of nano-wire transistor structure and preparation method thereof, this nano-wire transistor structure can reduce the contact resistance between the leakage of source, and can effectively reduce the generation of parasitic capacitance.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of based on Ni xThe nanowire MOS transistor structure of-III-V element.In the present invention, use metallic nickel to leak diffusion material, sharp body tubular construction as the source of III-V family semiconductor nanowires.In the present invention, use metallic nickel to leak diffusion material, utilize the mechanism of nickel diffusion under the high temperature, make metallic nickel can be spread in the III-V family material, form low-resistance Ni as the source of III-V family semiconductor nanowires xThe alloy of-III-V form leak material as the source of III-V family semiconductor nanowires MOS transistor, thereby the ohmic contact of material and channel material is leaked in the realization source.Here 0.1≤x≤3.
That the disclosed nanowire MOS transistor of the present invention has is simple in structure, easily manufactured, contact resistance is little and can effectively reduce the generation of parasitic capacitance and make the cut-off current of MOS transistor advantage such as effectively reduce.
Further, the present invention also provides a kind of manufacturing approach of above-mentioned nanowire MOS transistor structure, and this method comprises the following steps:
On the insulator substrates that provides, form the film of layer of metal nickel;
Carry out the annealing first time, on insulator substrates, obtain metallic nickel nano granule; Annealing temperature can be 800-900 ℃, and annealing atmosphere can be used H 2
With III-V family semiconductor is Solid State Source; The temperature in Solid State Source source region is controlled at (as 700-800 ℃) more than 700 ℃; With the metallic nickel nano granule is catalyst; The temperature of insulator substrates is controlled in 450-550 ℃, utilizes gaseous state-liquid state-solid state process (VLS) III-V family nano wire of on insulator substrates, growing;
On the Semiconductor substrate that provides, form single III-V semiconductor nanowires or parallel III-V conductor nano tube/linear array;
On the zone of needs growth raceway groove, form the grid structure of device;
Form the abutment wall structure of insulation on the both sides of said grid structure;
Both sides in said abutment wall structure form metal nickel film;
Carry out the annealing second time, nickle atom is diffused in the III-V family semiconductor nanowires, obtain low-resistance Ni xThe alloy of-III-V form.Annealing temperature can be 200-250 ℃, selects for use reducibility gas (like H 2Or NH 3Deng).
Described insulator substrates is SiO 2, Si 3N 4The perhaps insulator of other material.Described Semiconductor substrate is the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator.Described abutment wall structure is by SiO 2, Si 3N 4The insulating material that perhaps mixes mutually between them constitutes.
Further; Described grid structure comprises at least one conductive layer and the insulating barrier with said conductive layer and the isolation of said Semiconductor substrate; Described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, and described insulating barrier is SiO 2, HfO 2, HfSiO, HfSiON, SiON, Al 2O 3Perhaps several kinds mixture among them.
It should be noted that when carrying out annealing the second time, can be through the temperature and time of control annealing, make nano-channel length, thereby make device that bigger operating current arranged.
Description of drawings
Fig. 1 to Fig. 3 is the forming process sketch map of III-V family nano wire.
Fig. 4 to Fig. 8 is provided by the invention based on Ni xThe forming process sketch map of the nanowire MOS transistor structure of-III-V element.
Fig. 5 b, Fig. 6 b and Fig. 7 b are respectively the sectional view of structure shown in Fig. 5 a, Fig. 6 a and Fig. 7 a.
Embodiment
Below with reference to accompanying drawings an illustrative embodiments of the present invention is elaborated.In the drawings, the thickness in layer and zone is amplified or has dwindled in explanation for ease, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, their zones that still has been complete reflection and form the mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.Reference diagram is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all representes with rectangle, and the expression among the figure is schematically, but this should not be considered to limit scope of the present invention.Simultaneously in the following description, employed term substrate is appreciated that to be to comprise the just Semiconductor substrate in processes, possibly comprise other prepared thin layer above that.
Like Fig. 1, the film 102 of long layer of metal nickel on the insulator substrates 101 is provided, thickness is about tens nanometers, and insulator substrates is such as being SiO 2Substrate.
Next, temperature is used H in 800-900 ℃ of scope 2Annealing obtains the metallic nickel nano granule that on insulator substrates 101, generates.Like Fig. 2, shown in 103 be in a plurality of nano nickel particles one.
Next; With III-V family semiconductor is Solid State Source; The source region temperature is controlled at more than 700 ℃, is catalyst with the nickel nano particle, and the insulator substrates temperature is in 450-550 ℃; Utilize gaseous state-liquid state-solid-state (VLS) method growth III-V family semiconductor nanowires, III-V family semiconductor nanowires is such as being Ni xGaAs, Ni xInAs, Ni xInGaAs etc.Like Fig. 3, shown in 104 be in the many III-V family semiconductor nanowires one, shown in 105 be a nickel nanoparticle.
Next, be spin-coated on the substrate after being dispersed in III-V family semiconductor nanowires in the solution, or directly utilize contact printing, the III-V family conductor nano tube/linear array of to arrange parallel on the Semiconductor substrate of fabricate devices.Like Fig. 4, shown in Semiconductor substrate 200 be the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator, shown in 201a be an III-V family semiconductor nanowires in the parallel III-V family conductor nano tube/linear array, shown in 201b be a nickel nano particle.
Next, on the zone of needs growths raceway groove, growth gate medium 203 and gate stack structure 204, like Fig. 5 a, shown in gate medium 203 such as being SiO 2, shown in gate stack structure 204 comprise high-k gate dielectric layer, metal gate electrode layer and polysilicon layer.Fig. 5 b is the sectional view of structure shown in Fig. 5 a.
Next, deposit forms one deck dielectric, then dielectric is carried out etching, forms abutment wall structure 205a and 205b on the both sides of gate stack structure 204 and gate medium 204, and like Fig. 6 a, abutment wall structure 205a and 205b are SiO 2, Si 3N 4The insulating material that perhaps mixes mutually between them, Fig. 6 b is the sectional view of structure shown in Fig. 6 a.
Again next, deposit layer of metal nickel carries out etching to it then and forms the structure shown in Fig. 7 a, shown in 206a and 206b be metallic nickel, Fig. 7 b is the sectional view of structure shown in Fig. 7 a.
At last, under 200-250 ℃ of temperature range, feed the gas such as the H of reproducibility 2, NH 3Deng, anneal, nickle atom is diffused among the semiconductor nanowires 201a of III-V family, obtain Ni xThe alloy of-III-V form is as the source drain contact.Like Fig. 8, shown in 207a and 207b Ni for forming xThe alloy of-III-V form, shown in 201c be the remaining part of the semiconductor nanowires 201a of III-V family, as the channel structure of device.It should be noted that when this time annealing, need the temperature and time of control annealing, make the channel length of III-V family semiconductor nanowires long consistent with the grid of device.
Such one based on Ni xThe nanowire MOS transistor structure of-III-V element has just formed.
Nanowire MOS transistor structure proposed by the invention can be used for the preparation of high speed mos transistor, or on the following printed IC.
As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the instantiation described in the specification.

Claims (11)

1. the preparation method of a nanowire MOS transistor is characterized in that, comprises the following steps:
On the insulator substrates that provides, form the film of layer of metal nickel;
Carry out the annealing first time, on insulator substrates, obtain metallic nickel nano granule;
With III-V family semiconductor is Solid State Source, is catalyst with the metallic nickel nano granule, utilizes gaseous state-liquid state-solid state process III-V family nano wire of on said insulator substrates, growing;
On the Semiconductor substrate that provides, form single III-V semiconductor nanowires or parallel nano-wire array;
On the zone of needs growth raceway groove, form the grid structure of device;
Form the abutment wall structure of insulation on the both sides of said grid structure;
Both sides in said abutment wall structure form metal nickel film;
Carry out the annealing second time, nickle atom is diffused in the III-V family semiconductor nanowires, obtain Ni xThe alloy of-III-V form.
2. preparation method according to claim 1 is characterized in that, described insulator substrates is SiO 2Or Si 3N 4
3. preparation method according to claim 1 is characterized in that, the condition of said first time of annealing be temperature in 800-900 ℃ of scope, use H 2Annealing.
4. preparation method according to claim 1 is characterized in that, when on said insulator substrates, growing III-V family nano wire, the temperature in said Solid State Source source region is more than 700 ℃, and the temperature of insulator substrates is 450-550 ℃.
5. preparation method according to claim 1 is characterized in that, described Semiconductor substrate is the silicon on monocrystalline silicon, polysilicon or the insulator.
6. preparation method according to claim 1 is characterized in that, described grid structure comprises at least one conductive layer and the insulating barrier with said conductive layer and the isolation of said Semiconductor substrate.
7. preparation method according to claim 6 is characterized in that, described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide.
8. preparation method according to claim 6 is characterized in that, described insulating barrier is SiO 2, HfO 2, HfSiO, HfSiON, SiON, Al 2O 3Perhaps several kinds mixture among them.
9. preparation method according to claim 1 is characterized in that, described abutment wall structure is by SiO 2, Si 3N 4The insulating material that perhaps several kinds are mixed mutually among them constitutes.
10. preparation method according to claim 1 is characterized in that, the condition of described second time of annealing be temperature in 200-250 ℃ of scope, select the gas H of reproducibility for use 2Or NH 3
11. manufacturing approach according to claim 1 is characterized in that, when carrying out annealing the second time, the temperature and time through control annealing makes that the channel length of nanowire MOS transistor is consistent with the length of grid.
CN201010111275A 2010-02-11 2010-02-11 Nanowire MOS transistor based on III-V element and preparation method thereof Expired - Fee Related CN101783367B (en)

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US8941123B2 (en) 2013-05-30 2015-01-27 International Business Machines Corporation Local interconnects by metal-III-V alloy wiring in semi-insulating III-V substrates

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CN102456733B (en) * 2010-10-29 2016-05-04 鸿富锦精密工业（深圳）有限公司 Transistor and preparation method thereof
KR101631778B1 (en) 2011-12-23 2016-06-24 인텔 코포레이션 Nanowire structures having wrap-around contacts
CN105810730B (en) * 2014-12-29 2018-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device and its manufacturing method
CN104934479A (en) * 2015-05-11 2015-09-23 中国科学院半导体研究所 III-V clan nano wire planar transistor based on SOI substrate and preparation method thereof
CN106887409B (en) * 2015-12-15 2020-02-21 上海新昇半导体科技有限公司 Complementary nanowire semiconductor device and manufacturing method thereof

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CN101510504A (en) * 2009-03-13 2009-08-19 苏州纳晶光电有限公司 Transversal epitaxial growth method for nano area of semiconductor film

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CN101510504A (en) * 2009-03-13 2009-08-19 苏州纳晶光电有限公司 Transversal epitaxial growth method for nano area of semiconductor film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941123B2 (en) 2013-05-30 2015-01-27 International Business Machines Corporation Local interconnects by metal-III-V alloy wiring in semi-insulating III-V substrates

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