CN101783352B - Nonvolatile memory and design method thereof - Google Patents
Nonvolatile memory and design method thereof Download PDFInfo
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- CN101783352B CN101783352B CN2010101053243A CN201010105324A CN101783352B CN 101783352 B CN101783352 B CN 101783352B CN 2010101053243 A CN2010101053243 A CN 2010101053243A CN 201010105324 A CN201010105324 A CN 201010105324A CN 101783352 B CN101783352 B CN 101783352B
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Abstract
The invention disclose a nonvolatile memory and a design method thereof, the nonvolatile memory comprises a source electrode, a drain electrode, a floating gate and a control grid, wherein, the floating gate comprises a silicon dioxide layer, a polycrystalline silicon layer and a first part of a first metal layer; wherein, the polycrystalline silicon layer is connected with the first part of the first metal layer by a contact hole; the control grid comprises a second part of the first metal layer and a third part of the first metal layer; wherein, the second part of the first metal layer and the third part of the first metal layer are electrically insulated with the first part of the first metal layer to form a coupling capacitance. A nonvolatile memory design and manufacturing proposal with the advantages of low cost and superior memory performance, which is based on the existing logical technology is provided to users by the invention.
Description
The application be that May 30, application number in 2007 are 200710099806.0 the applying date, denomination of invention divides an application for the application for a patent for invention of " a kind of nonvolatile memory and method for designing thereof ".
Technical field
The present invention relates generally to semiconductor memory, relates in particular to a kind of nonvolatile memory and method for designing thereof.
Background technology
Memory is broadly divided into two big classes: volatibility and non-volatile.Volatile memory loses the information in being stored in immediately when system closing; The power supply supply that it need continue is to keep data.Most of random asccess memory all belongs to this type of.Nonvolatile memory still can keep data message when system closing or non-transformer supply.
A floating gate type nonvolatile memory (NVM) device also is a MOS transistor usually, this MOS transistor has a source electrode (Source), a drain electrode (Drain) and a grid (Gate), what it was different with the structure of general metal-oxide-semiconductor is that grid comprises two parts: floating boom (Floating Gate) and control gate (Control Gate).Floating boom is between grid oxic horizon and interpolar oxide layer, and the interpolar oxide layer is used for isolated floating boom, and the composition of two kinds of oxide layers can be oxygen-nitrogen-oxygen (O-N-O) or silicon dioxide (SiO
2).Be one deck grid oxic horizon between control gate and the floating boom, control gate is connected with outside electrode.
Floating gate type nonvolatile memory is realized the storage to data message by electric charge is kept in the floating boom.For example, when carrying out write operation, on control gate, apply voltage, by the capacitive coupling effect between control gate and the floating boom, make control gate and other such as setting up an electrical potential difference between source electrode, drain electrode or the channel region, in floating boom, place electric charge by this electrical potential difference, finish whole write operation process.
Along with developing rapidly of integrated circuit technique, the size of integrated circuit (IC)-components is more and more littler, thereby makes that SOC (system on a chip) (SoC, System On Chip) is also more and more universal.And a considerable module is exactly a nonvolatile memory among the SOC.In order to provide multiple function, the module of many difference in functionalitys must be integrated on the chip to SoC.Yet the manufacturing of nonvolatile memory need be adopted special process, and it is different from the main logic process that adopts in the present SoC manufacture process.Logic process is the main flow technology that most of integrated circuits (IC, Integrated Circuits) designer generally uses.Because making the special process of the required employing of nonvolatile memory seldom uses, therefore, if adopt this special process to develop and make the SOC device, will expend great amount of cost, will make the price of the SOC device that manufactures expensive more a lot of than the SOC device that adopts logic process to make.
Although can be in order to make nonvolatile memory easily, and use this special process to make whole SOC, the cost of being paid be to reduce the performance of other logical device greatly.In addition, many IC designers also are familiar with this special process unlike understanding traditional logic process, and therefore, the method for using this special process to make whole SOC has increased design risk and complexity, and worse also has technical support expensive and that lag behind.Wherein, the technical support of hysteresis will cause the delay of whole SoC on the development time, be because also do not use this special process widely in the semiconductor manufacturing and cause the main cause of the technical support of hysteresis.
At present, release the SOC that much takes into account design special process of nonvolatile memory and traditional logic technology and made solution.For example, adopt a pair of P-type mos (PMOS, P typeMetal-Oxide Semiconductor) and N type metal oxide semiconductor (NMOS, N typeMetal-Oxide Semiconductor) transistor, their grid is coupled together and suspend, be formed for the floating boom of stored charge.Raceway groove or other physical effect by PMOS and nmos pass transistor realize activating programming and erase feature.But, for fear of incidental latch phenomenon between PMOS and the nmos pass transistor when high level is operated, have to sort memory spare is designed to large scale, and large-sized design will cause the increase of PMOS and nmos pass transistor internal capacitance, and then have influence on NMOS and the transistorized capacity ratio of PMOS that guarantees the memory operate as normal.In addition, because the mode of operation of NMOS and PMOS is different, wherein, nmos pass transistor is an accumulation mode, the PMOS transistor is a rp mode, and the two all can produce nonlinear capacitance, and this nonlinear capacitance will directly influence the memory property of this memory, therefore, need to add extra circuit and give to note to obtain the required linear characteristic of this memory device especially.
Other method utilizes soft breakdown and hard breakdown effect to obtain a succession of different resistance in addition, distinguishes and identification so that storing value can be carried out.Yet in view of puncturing not main effect of control difficulty in the operating process and some, the programmable number of times of the nonvolatile memory by utilizing the design of soft breakdown and hard breakdown effect will be very limited.
Therefore, to the design of nonvolatile memory, when attempting guaranteeing the compactedness and reliability of memory cell, should be consistent with logic process as far as possible, overcome the defective of above-mentioned prior art design initial as much as possible.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of nonvolatile memory and method for designing thereof, a cover cost input is little, memory property is superior, make solution based on the nonvolatile memory designs of existing logic process for the user provides by the present invention.
The invention provides a kind of nonvolatile memory, comprise the multilayer that source electrode, drain electrode and floating boom are provided, this multilayer is included as the multiple layer metal layer that memory provides interconnection line.Two metal layers capacitive couplings at least wherein is for floating boom provides electric capacity.
Electric capacity described in this nonvolatile memory is control gate.
This nonvolatile memory also comprises through hole, is used to connect the metal level that is used for forming capacitor more than two-layer.
Be electrically insulated between the multiple layer metal layer in this nonvolatile memory.
Control gate in this nonvolatile memory comprises a plurality of electric capacity.
A plurality of electric capacity in this nonvolatile memory are formed by two-layer above metal level.
This nonvolatile memory also comprises another electric capacity, and this electric capacity is formed by the one deck in another metal level and the multiple layer metal layer, the capacitive coupling that this electric capacity and other multiple layer metal layer form.
Floating boom in this nonvolatile memory and a plurality of capacitor-coupled.
This nonvolatile memory adopts P-type mos transistor or N type metal oxide semiconductor transistor.
The present invention also provides a kind of nonvolatile memory designs method, comprising:
The multilayer that forms source electrode, drain electrode and floating boom is provided, and this multilayer is included as the multiple layer metal layer that memory provides interconnection line.Two metal layers capacitive couplings at least wherein is for floating boom provides electric capacity.
This method further comprises: be provided for connecting the through hole of two metal layers at least.
Nonvolatile memory of the present invention and method for designing by with the control gate structure of metal-layer structure as nonvolatile memory among the present invention, are used for the polysilicon of control gate thereby saved one deck, and then have saved manufacturing cost; The coupling capacitance between control gate and floating boom becomes the main electric capacity that memory is realized memory function in the prior art by the coupling capacitance between metal wire is replaced, thereby obtains a preferable capacity ratio that helps improving the nonvolatile memory stores performance; By increasing oxidated layer thickness, make manufacturing process and I/O (I/O, Input/Output) the device unanimity of nonvolatile memory among the present invention; Be reached for the user provide a cover cost drop into little, memory property is superior, make the beneficial effect of solution based on the nonvolatile memory designs of existing logic process.
Description of drawings
Fig. 1 is the canonical schema of first kind of PMOS type Nonvolatile programmable memory cell among the present invention;
Fig. 2 is the canonical schema of first kind of NMOS type Nonvolatile programmable memory cell among the present invention;
Fig. 3 is the vertical view of Nonvolatile programmable memory cell among the present invention;
Fig. 4 is the canonical schema of second kind of PMOS type Nonvolatile programmable memory cell among the present invention;
Fig. 5 is the canonical schema of second kind of NMOS type Nonvolatile programmable memory cell among the present invention.
Embodiment
Nonvolatile memory of the present invention and method for designing are still used logic process first-selected in the IC manufacturing industry on the structural design; Utilize the geometry advantage of the original layering of material and size reduces to cause can produce between metal wire big coupling capacitance in the submicrometer processing process advantage, change the grid structure of floating gate type nonvolatile memory in the prior art, with the control gate structure of metal-layer structure as nonvolatile memory among the present invention, and appropriate change floating gate structure of the prior art, coupling capacitance between control gate and floating boom in the bigger coupling capacitance replacement prior art that produces between metal wire is become the main electric capacity that memory is realized memory function, drop into little for the user provides a cover cost, memory property is superior, nonvolatile memory designs based on existing logic process is made solution.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described.
Because modern advanced integrated circuit (IC) design and manufacturing process technology, the size of integrated circuit (IC)-components is more and more littler, its inner metal live width is also more and more littler, because constantly reducing of metal live width, cause the continuous increase of coupling capacitance and constantly reducing of device inside plate capacitance between the metal wire, thereby make coupling capacitance between metal wire become the major part of device inside electric capacity gradually.For example, in typical 0.25um technology, minimum metal wire separation only is 0.3um, and in typical 0.18um technology, minimum metal wire separation only is 0.23um.When metal wire separation when 0.3um is reduced to 0.23um, the coupling capacitance between the identical layer metal wire will increase by 30%.In view of this, more and more littler along with the integrated circuit (IC)-components size, the coupling capacitance that generates between the metal wire of identical layer will be above the coupling capacitance of grid inside, therefore, with the control gate structure of metal-layer structure as nonvolatile memory among the present invention, and appropriate change floating gate structure of the prior art, make the bigger coupling capacitance that produces between metal wire replace in the prior art coupling capacitance in the grid and become the main electric capacity that memory is realized memory function, thereby provide more appropriate capacity ratio for programmable memory cell carries out the operation of specific memory device.This capacity ratio is defined as: in a programmable unit, the capacitance between control gate and the floating boom is divided by the capacitance between floating boom and the MOS transistor substrate, and gained ratio is capacity ratio.Generally, the ratio range of this capacity ratio is [5,10].
Characteristic of the present invention and advantage can be able to better understanding according to the following drawings and explanation.With reference to structure of the present invention, Fig. 1 is the canonical schema of first kind of PMOS type Nonvolatile programmable memory cell among the present invention, comprises control gate 100 that disposes electric capacity and the pmos type floating gate memory cell 101 with floating boom 102 among the figure.This pmos type floating gate memory cell 101 comprises a PMOS transistor, and this PMOS transistor comprises N type substrate 103, forms the p type ion diffusion region 104 of source electrode and drain electrode.Floating boom 102 comprises silicon dioxide (SiO
2) layer 108, polysilicon (Poly) layer 107, polysilicon layer 107 links to each other with the first metal layer 109 by contact hole (contact) 105, and the first metal layer (M1) 109 passes through first through hole (via 1) 119 and links to each other with second metal level (via 2) 111.Floating boom 102 is insulated layer and surrounds.Control gate 100 comprises the first metal layer 110, second metal level 112 and the 3rd metal level (via 3) 114.The first metal layer 110 is connected with second metal level 112 by first through hole 118.Second through hole, 120 second metal levels 112 are connected with the 3rd metal level 114 by second through hole 120.The first metal layer 110 and second metal level 112 surround floating boom 102, and the 3rd metal level 114 covers whole memory unit.
By among the present invention since electric capacity be by between the metal level coupling form, this electric capacity increases along with the minimizing of process.In addition, the coupling capacitance between the metal level has better linearity and stability than the coupling capacitance between control gate in the metal-oxide-semiconductor and floating boom.
Fig. 2 is the canonical schema of first kind of NMOS type Nonvolatile programmable memory cell among the present invention, comprises control gate 200 that disposes electric capacity and the nmos type floating gate memory cell 201 with floating boom 202 among the figure.Floating gate memory cell 201 comprises a nmos device, and it is made up of the n type ion diffusion region 204 of p type substrate 203, source electrode and drain electrode.Floating boom 202 comprises silicon dioxide layer 208, polysilicon layer 207, and polysilicon layer 207 links to each other with the first metal layer 209 by contact hole 205.The first metal layer 209 is connected with second metal level 211 by first through hole 219.Floating boom 202 is insulated layer and surrounds.Control gate 200 comprises the first metal layer 210, second metal level 212 and the 3rd metal level 214.The first metal layer 210 is connected with second metal level 212 by first through hole 218.Second metal level 212 is connected with the 3rd metal level 214 by second through hole 220.The first metal layer 210 and second metal level 212 surround floating boom 202, and the 3rd metal level 214 covers whole memory unit.
Fig. 3 is the vertical view of Nonvolatile programmable memory cell structure among the present invention.In conjunction with Fig. 1, comprise the first metal layer 109, second metal level 111 among Fig. 3, the contact hole 105 and first through hole 119, polysilicon layer 107 and p type ion diffusion region 104.As can be seen, the first metal layer 110 and second metal level 112 have surrounded floating boom 102 from the vertical view.Because the 3rd metal level 114 covered whole memory unit, for the each several part sake of clarity among the figure, this vertical view does not provide the 3rd metal level 114.Because Fig. 1 is described pmos type Nonvolatile programmable memory cell structure, Fig. 2 is described nmos type Nonvolatile programmable memory cell structure, the two only is different on the transistor types, structurally in full accord, therefore, Fig. 3 also can be used as the vertical view to nmos type Nonvolatile programmable memory cell structure among Fig. 2.
In conjunction with another kind of structure of the present invention, Fig. 4 is the canonical schema of second kind of PMOS type Nonvolatile programmable memory cell among the present invention, and this unit comprises control gate 400 that disposes electric capacity and the PMOS type floating gate memory cell 401 with floating boom 402.Floating gate memory cell 401 comprises the PMOS device, and it is made up of the p type ion diffusion region 404 of n type substrate and source electrode and drain electrode.Floating boom 402 comprises silicon dioxide layer 408, polysilicon layer 407, and polysilicon layer 407 links to each other with the first metal layer 409 by contact hole 405.Floating boom 402 is insulated layer and surrounds.Control gate 400 comprises the first metal layer 410, it and floating boom 402 capacitive couplings.Along with live width constantly reduces, the electric capacity between the metal increases to form control gate 400.
Fig. 5 is the canonical schema of second kind of NMOS type Nonvolatile programmable memory cell among the present invention.The nonvolatile memory of NMOS type comprises control gate 500 that disposes electric capacity and the floating-gate memory 501 with NMOS type of floating boom 502.Floating gate memory cell 501 comprises nmos device, and this device is made up of the n type ion diffusion region 504 of p type substrate 503 and source electrode and drain electrode.Floating boom 502 comprises silicon dioxide layer 508, polysilicon layer 507, and polysilicon layer 507 links to each other with the first metal layer 509 by contact hole 505.Floating boom 502 is insulated layer and surrounds.Control gate 500 comprises the first metal layer 510, it and floating boom 502 capacitive couplings.Along with live width constantly reduces, the electric capacity between the metal is scalable to form control gate 500.
According to another kind of structure of the present invention, diffusion layer 104,204,404 or 504 are used to provide and comprise the interconnection of bit line at interior memory, thereby make the metal level can be isolated with interconnection line better, and then electric capacity is provided more fully.
Programmable unit among the present invention can adopt the PMOS device of logic-based technology.Usually, logic process provides two class devices at least: core devices and I/O device.Wherein, thickness of oxide layer is bigger than thickness of oxide layer in the core devices in the I/O device.As use the programmable unit of I/O device, its thickness of oxide layer is usually greater than 70 dusts.In addition, the operation level of I/O device is also than the operation level height of core devices.The operation level of I/O device is generally 3.3V, and the operation level of core devices is generally 1.8V.In order to satisfy the requirement of logic process, the present invention is by the thickness of oxide layer of increase programmable unit, in the device fabrication as 0.18um and 0.13um, in manufacture process, increase the thickness of oxide layer of programmable unit, make it reach consistent with the thickness of oxide layer of I/O device.The increase of oxidated layer thickness also makes the operation level of programmable unit rise to the operation level 3.3V of I/O device by 1.8V, and programmable unit can satisfy the requirement that has logic process now among the present invention thereby make.
From aforementioned content as can be seen, nonvolatile memory of the present invention has utilized the size of dwindling and the electric capacity that is coupled out of close metal level mutually, for the electric charge on the control floating boom provides control gate electric capacity.PMOS of the present invention and nmos type transistor can replace with the transistor of other type.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a nonvolatile memory comprises source electrode, drain electrode, floating boom and control gate are provided, it is characterized in that,
Described floating boom comprises the first of silicon dioxide layer, polysilicon layer, the first metal layer and the first of second metal level; Wherein, described polysilicon layer is connected with the first of described the first metal layer by contact hole, and the first of described the first metal layer is connected by the first of through hole with described second metal level;
Described control gate comprises the third part and described the 3rd metal level of the second portion of the third part of the second portion of described the first metal layer, described the first metal layer, described second metal level, described second metal level; Wherein, the second portion of described the first metal layer is connected by the second portion of through hole with described second metal level, the third part of described the first metal layer is connected by the third part of through hole with described second metal level, and the second portion of described second metal level is connected with described the 3rd metal level by through hole respectively with third part;
Wherein, be electrically insulated between the first of the second portion of described the first metal layer and third part and described the first metal layer, form first capacitive coupling; Be electrically insulated between the first of the second portion of described second metal level and third part and described second metal level, form second capacitive coupling.
2. nonvolatile memory according to claim 1 is characterized in that, described nonvolatile memory comprises P-type mos transistor or N type metal oxide semiconductor transistor.
3. nonvolatile memory designs method, described nonvolatile memory comprises source electrode, drain electrode, floating boom and control gate, it is characterized in that,
The first of silicon dioxide layer, polysilicon layer, the first metal layer and the first of second metal level are formed described floating boom; Wherein, described polysilicon layer is connected with the first of described the first metal layer by contact hole, the first of described the first metal layer is connected by the first of through hole with described second metal level;
The third part and described the 3rd metal level of the second portion of the third part of the second portion of described the first metal layer, described the first metal layer, described second metal level, described second metal level are formed described control gate; Wherein, the second portion of described the first metal layer is connected by the second portion of through hole with described second metal level, the third part of described the first metal layer is connected by the third part of through hole with described second metal level, and the second portion of described second metal level is connected with described the 3rd metal level by through hole respectively with third part;
Wherein, be electrically insulated between the first of the second portion of described the first metal layer and third part and described the first metal layer, form first capacitive coupling; Be electrically insulated between the first of the second portion of described second metal level and third part and described second metal level, form second capacitive coupling.
4. method according to claim 3 is characterized in that, described nonvolatile memory adopts P-type mos transistor or N type metal oxide semiconductor transistor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528842B1 (en) * | 2001-12-31 | 2003-03-04 | Jet City Electronics, Inc. | Electronically erasable memory cell using CMOS technology |
| US6806529B1 (en) * | 2003-01-30 | 2004-10-19 | National Semiconductor Corporation | Memory cell with a capacitive structure as a control gate and method of forming the memory cell |
| CN1550040A (en) * | 2001-08-28 | 2004-11-24 | �ʼҷ����ֵ��ӹɷ�����˾ | Non-volatile semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1550040A (en) * | 2001-08-28 | 2004-11-24 | �ʼҷ����ֵ��ӹɷ�����˾ | Non-volatile semiconductor memory |
| US6528842B1 (en) * | 2001-12-31 | 2003-03-04 | Jet City Electronics, Inc. | Electronically erasable memory cell using CMOS technology |
| US6806529B1 (en) * | 2003-01-30 | 2004-10-19 | National Semiconductor Corporation | Memory cell with a capacitive structure as a control gate and method of forming the memory cell |
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