CN101777564B - 一种具有垂直栅结构的soi cmos器件 - Google Patents
一种具有垂直栅结构的soi cmos器件 Download PDFInfo
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Abstract
本发明公开了一种具有垂直栅结构的SOI CMOS器件,包括SOI衬底,以及生长在SOI衬底上的NMOS区和PMOS区,所述NMOS区和PMOS区共用一个垂直栅区,所述垂直栅区与NMOS区和PMOS区位于同一平面上,垂直栅区位于NMOS区和PMOS区之间;垂直栅区与NMOS区之间隔离有栅氧化层;垂直栅区与PMOS区之间隔离有栅氧化层。本发明占用面积小,版图层数少,工艺简单,敞开的体区能够完全避免传统SOI CMOS器件的浮体效应,并方便对寄生电阻、电容的测试。
Description
技术领域
本发明属于微电子与固体电子技术领域,涉及一种具有垂直栅结构的SOICMOS器件。
背景技术
互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)器件是在将N型金属氧化物半导体晶体管(NMOS)与P型金属氧化物半导体晶体管(PMOS)集成在同一块硅片上的半导体器件。随着器件尺寸的不断缩小,短沟道效应(SCE)成为所有常规平面CMOS器件按比例进一步缩小所难以逾越的一道障碍,它导致器件特性退化,寄生效应增加,限制了常规平面CMOS器件的进一步缩小。
绝缘体上硅(Silicon On Insulator,SOI)是指以“工程化的”基板代替传统的体型衬底硅的基板技术,这种基板通常由以下三层构成:薄的单晶硅顶层,在其上形成蚀刻电路;相当薄的埋层氧化层(Buried Oxide,BOX),即绝缘二氧化硅中间层;非常厚的体型衬底硅衬底层,其主要作用是为上面的两层提供机械支撑。由于SOI结构中氧化层把其上的硅膜层与硅衬底层分隔开来,大面积的p-n结将被介电隔离(dielectric isolation)取代。源极(source region)和漏极(drain region)向下延伸至埋层氧化层,有效减少了漏电流和结电容,彻底消除了体硅CMOS器件的寄生闩锁效应,具有速度快、功耗低、集成密度高、抗干扰能力强等优点,广泛应用于射频、高压、抗辐照等领域。
由于SOI材料的介质隔离,制作在厚膜SOI衬底上MOS器件上下Si-SiO2界面处的耗尽层没有接触,在它们中间存在一中性体区,这一中性体区使得硅体处于电学浮空状态,产生了两个明显的二级寄生效应,一个是″翘曲效应″,即Kink效应;另一个是器件源漏之间形成的基极开路NPN寄生晶体管效应。这种由于体区处于悬浮状态,电势被抬高,使得碰撞电离产生的电荷无法被迅速移走的现象叫作浮体效应。SOI CMOS器件特有的浮体效应不仅会降低器件增益,降低源漏击穿电压,引起单管闩锁,带来较大的泄漏电流,导致功耗增加,还会引起电路工作的不稳定,带来噪声过冲,对器件和电路性能的影响很大。
为解决SOI衬底带来的浮体效应,通常采用体引出(body contact)的方法将“体”接固定电位(源端或地)。传统的体引出结构如图1、2所示,在源区左侧形成的P+注入区与源区下面的P型体区相连,MOS器件工作时,体区积累的载流子通过P+通道泄放,达到降低体区电势的目的;但这种方法使工艺流程复杂化,寄生效应增加,不仅降低了部分电学性能还增大了器件面积。
发明内容
本发明所要解决的技术问题是:提供一种具有垂直栅结构的SOI CMOS器件,此器件能够避免传统SOI CMOS器件的浮体效应。
为解决上述技术问题,本发明采用如下技术方案。
一种具有垂直栅结构的SOI CMOS器件,包括SOI衬底,以及生长在SOI衬底上的NMOS区和PMOS区,所述NMOS区和PMOS区共用一个垂直栅区,所述垂直栅区与NMOS区和PMOS区位于同一平面上,垂直栅区位于NMOS区和PMOS区之间;垂直栅区与NMOS区之间隔离有栅氧化层;垂直栅区与PMOS区之间隔离有栅氧化层。
作为本发明的一种优选方案,所述SOI衬底包括由下至上生长的硅衬底层,埋层氧化层,单晶硅顶层。
作为本发明的另一种优选方案,所述栅氧化层向下延伸至埋层氧化层;所述垂直栅区、NMOS区和PMOS区与硅衬底层之间隔离有埋层氧化层。
作为本发明的再一种优选方案,所述NMOS区包括NMOS源区、NMOS漏区、NMOS沟道,NMOS源区引出有NMOS源极,NMOS漏区引出有NMOS漏极,NMOS沟道引出有NMOS体电极。
作为本发明的再一种优选方案,所述PMOS区包括PMOS源区、PMOS漏区、PMOS沟道,PMOS源区引出有PMOS源极,PMOS漏区引出有PMOS漏极,PMOS沟道引出有PMOS体电极。
作为本发明的再一种优选方案,所述垂直栅区与NMOS沟道、PMOS沟道垂直对准。
作为本发明的再一种优选方案,所述垂直栅区引出有栅极。
作为本发明的再一种优选方案,所述NMOS区上生长有NMOS保护层,所述PMOS区上生长有PMOS保护层。
本发明的有益效果在于:它占用面积小,版图层数少,工艺简单,敞开的体区能够完全避免传统SOI CMOS器件的浮体效应,并方便对寄生电阻、电容的测试。
附图说明
图1为体引出结构的俯视图;
图2为体引出结构的剖面图;
图3为本发明的三维示意图;
图4为本发明的x-z轴方向上的剖面示意图;
图5A为本发明的y-z轴方向上NMOS的剖面示意图;
图5B为本发明的y-z轴方向上PMOS的剖面示意图;
图6为本发明的俯视图;
图7为本发明的栅氧化层工艺示意图。
主要组件符号说明:
1、NMOS的源区; 2、NMOS的沟道;
3、NMOS的漏区; 4、NMOS的栅氧化层;
5、垂直栅区; 6、PMOS的栅氧化层;
7、PMOS的漏区; 8、PMOS的沟道;
9、PMOS的源区; 10、埋层氧化层;
11、硅衬底层; 12、NMOS体电极;
13、PMOS体电极; 14、NMOS漏极;
15、PMOS漏极; 16、NMOS源极;
17、PMOS源极; 18、栅极;
19、NMOS保护层; 20、PMOS保护层。
具体实施方式
下面结合附图对本发明的具体实施方式作进一步详细说明。
本发明为了消除SOI CMOS器件中的浮体效应,提出一种新型的、具有垂直栅结构的SOI CMOS器件,通过引入体电极便可将体区电势箝位,而且其电势可根据需要接地或接源极,几乎完全消除了SOI CMOS器件中的浮体效应。
实施例一
如图3至7所示,本实施例提供一种具有垂直栅结构的SOI CMOS器件,包括SOI衬底,以及生长在SOI衬底上的NMOS区和PMOS区,所述NMOS区和PMOS区共用一个垂直栅区5,所述垂直栅区5与NMOS区和PMOS区位于同一平面上,垂直栅区5位于NMOS区和PMOS区之间;垂直栅区5与NMOS区之间隔离有NMOS栅氧化层4;垂直栅区5与PMOS区之间隔离有PMOS栅氧化层6。
所述SOI衬底包括由下至上生长的硅衬底层11,埋层氧化层10,单晶硅顶层。所述NMOS栅氧化层4和PMOS栅氧化层6均向下延伸至埋层氧化层10;所述垂直栅区5、NMOS区和PMOS区与硅衬底层11之间隔离有埋层氧化层10。所述NMOS区包括NMOS源区1、NMOS漏区3、NMOS沟道2,NMOS源区1引出有NMOS源极16,NMOS漏区3引出有NMOS漏极14,NMOS沟道2引出有NMOS体电极12。所述PMOS区包括PMOS源区9、PMOS漏区7、PMOS沟道8,PMOS源区9引出有PMOS源极17,PMOS漏区7引出有PMOS漏极15,PMOS沟道8引出有PMOS体电极13。所述垂直栅区5引出有栅极18。所述垂直栅区5与NMOS沟道2、PMOS沟道8垂直对准。所述NMOS区上生长有NMOS保护层19,如图5A所示;所述PMOS区上生长有PMOS保护层20,如图5B所示。
本发明公开的可消除SOI CMOS器件浮体效应的具有垂直栅结构的SOI CMOS器件,其主要包括:SOI衬底、具有P沟道的PMOS区、具有N沟道的NMOS区及垂直栅区,其中PMOS和NMOS共用一个垂直栅区;垂直栅区在水平方向上位于PMOS区和NMOS区之间;垂直栅区延伸至BOX层,且在水平方向上与PMOS沟道和NMOS沟道平行;在PMOS区或NMOS区与硅衬底层之间均有埋层氧化层将它们隔离。这种具有垂直栅结构的SOI CMOS器件占用面积小,版图层数少,工艺简单,敞开的体区能够完全避免传统SOI CMOS器件的浮体效应,并方便对寄生电阻、电容的测试。
实施例二
本实施例提供一种具有垂直栅结构的SOI CMOS器件的制作方法,其主要包括如下工艺步骤:
1.利用STI技术对PMOS区和NMOS区进行氧化物隔离。
2.在PMOS区和NMOS区中间刻蚀出一个窗口,其它部位用氮化硅保护,利用热氧化的方法,氧化侧壁,形成PMOS和NMOS的栅氧化层,然后淀积多晶硅,再对多晶硅进行掺杂,最后经化学机械抛光CMP平面化后,只保留窗口处多晶硅。
3.NMOS和PMOS的沟道采用多次离子注入的方式掺杂,掺杂完毕后再进行快速退火处理,纵向深度可通过调节注入能量和剂量调节。掺杂完毕后剖面杂质应分布均匀,边缘处杂质分布清晰陡峭。
4.用离子注入的方式分别对NMOS和PMOS的源区、漏区进行重掺杂,掺杂完毕后再进行快速退火处理。
5.分别对PMOS和NMOS的沟道、源区、漏区和垂直栅区刻蚀窗口后淀积金属引出体电极、源极、漏极、栅极,其中体电极可根据需要选择接地或与源极相连。
具有垂直栅结构的SOI CMOS器件的制作方法的详细工艺步骤为:
步骤一,由下至上依次生长硅衬底层,埋层氧化层,单晶硅顶层构成SOI衬底;
步骤二,采用集成电路STI工艺在SOI衬底上的单晶硅顶层位置处形成的有源区进行氧化物隔离;所述有源区包括NMOS区和PMOS区;
步骤三,在NMOS区和PMOS区中间刻蚀一个窗口,利用热氧化的方法在窗口内侧壁形成NMOS栅氧化层和PMOS栅氧化层;NMOS区包括NMOS源区、NMOS漏区、NMOS沟道;PMOS区包括PMOS源区、PMOS漏区、PMOS沟道;
步骤四,在窗口处淀积多晶硅,填满,掺杂,然后通过化学机械抛光形成垂直栅区;
步骤五,在NMOS沟道和PMOS沟道采用多次离子注入的方式掺杂,掺杂完毕后再进行快速退火处理;
步骤六,在NMOS源区、NMOS漏区、PMOS源区、和PMOS漏区采用离子注入的方式重掺杂,掺杂完毕后再进行快速退火处理;
步骤七,分别对NMOS源区、NMOS漏区、NMOS沟道淀积金属引出NMOS源极、NMOS漏极、NMOS体电极;分别对PMOS源区、PMOS漏区、PMOS沟道淀积金属引出PMOS源极、PMOS漏极、PMOS体电极;对垂直栅区淀积金属引出栅极。
步骤三中,除窗口内侧壁外的器件部分用光刻胶保护。所述步骤五中,NMOS沟道和PMOS沟道的纵向深度通过调节离子注入能量和剂量调节。所述步骤五中,掺杂完毕后的NMOS沟道和PMOS沟道的剖面杂质分布均匀,边缘处杂质分布清晰陡峭。
这里本发明的描述和应用是说明性的,并非想将本发明的范围限制在上述实施例中。这里所披露的实施例的变形和改变是可能的,对于那些本领域的普通技术人员来说实施例的替换和等效的各种部件是公知的。本领域技术人员应该清楚的是,在不脱离本发明的精神或本质特征的情况下,本发明可以以其他形式、结构、布置、比例,以及用其他元件、材料和部件来实现。
Claims (8)
1.一种具有垂直栅结构的SOI CMOS器件,包括SOI衬底,以及生长在SOI衬底上的NMOS区和PMOS区,其特征在于:所述NMOS区和PMOS区共用一个垂直栅区,所述垂直栅区与NMOS区和PMOS区位于同一平面上,垂直栅区位于NMOS区和PMOS区之间;垂直栅区与NMOS区之间隔离有栅氧化层;垂直栅区与PMOS区之间隔离有栅氧化层。
2.根据权利要求1所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述SOI衬底包括由下至上生长的硅衬底层,埋层氧化层,单晶硅顶层。
3.根据权利要求2所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述栅氧化层向下延伸至埋层氧化层;所述垂直栅区、NMOS区和PMOS区与硅衬底层之间隔离有埋层氧化层。
4.根据权利要求1所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述NMOS区包括NMOS源区、NMOS漏区、NMOS沟道,NMOS源区引出有NMOS源极,NMOS漏区引出有NMOS漏极,NMOS沟道引出有NMOS体电极。
5.根据权利要求1所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述PMOS区包括PMOS源区、PMOS漏区、PMOS沟道,PMOS源区引出有PMOS源极,PMOS漏区引出有PMOS漏极,PMOS沟道引出有PMOS体电极。
6.根据权利要求4或5所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述垂直栅区与NMOS沟道、PMOS沟道垂直对准。
7.根据权利要求1所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述垂直栅区引出有栅极。
8.根据权利要求1所述的具有垂直栅结构的SOI CMOS器件,其特征在于:所述NMOS区上生长有NMOS保护层,所述PMOS区上生长有PMOS保护层。
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US13/254,041 US20110316073A1 (en) | 2009-12-24 | 2010-12-15 | Soi cmos device having vertical gate structure |
PCT/CN2010/079812 WO2011076072A1 (zh) | 2009-12-24 | 2010-12-15 | 一种具有垂直栅结构的soicmos器件 |
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