CN101770997A - Down and up arranged resin circuit board and chip packaging structure with radiation block - Google Patents

Down and up arranged resin circuit board and chip packaging structure with radiation block Download PDF

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Publication number
CN101770997A
CN101770997A CN201010112819A CN201010112819A CN101770997A CN 101770997 A CN101770997 A CN 101770997A CN 201010112819 A CN201010112819 A CN 201010112819A CN 201010112819 A CN201010112819 A CN 201010112819A CN 101770997 A CN101770997 A CN 101770997A
Authority
CN
China
Prior art keywords
chip
circuit board
resin circuit
packaging structure
radiation block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201010112819A
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Chinese (zh)
Inventor
王新潮
梁志忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201010112819A priority Critical patent/CN101770997A/en
Publication of CN101770997A publication Critical patent/CN101770997A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a down and up arranged resin circuit board and chip packaging structure with a radiation block, which comprises a chip (3), a single-layer or multi-layer resin circuit board (9) supported below the chip, metal bumps (10) for interworking signals from the chip to the single-layer or multi-layer resin circuit board, a conductive or non-conductive heat-conducting binding material I (2) between the chip and the single-layer or multi-layer resin circuit board and a plastic packaging body (8). The packaging structure is characterized in that: the radiation block (7) is arranged above the chip (3); and a conductive or non-conductive heat-conducting binding material II (6) is embedded between the radiation block (7) and the chip (3). The radiation block is arranged above the chip and used for radiating high heat, so the packaging structure has high radiating capability, and ensures that the heat of the chip can be quickly conducted to the outside of a package.

Description

Down and up arranged resin circuit board and chip packaging structure with radiation block
(1) technical field
The present invention relates to a kind of down and up arranged resin circuit board and chip packaging structure with radiation block.Belong to the semiconductor packaging field.
(2) background technology
The radiating mode of traditional Chip Packaging form mainly be to have adopted the Metal Substrate island of chip below as heat radiation conduction instrument or approach, and there is following not enough point in the heat radiation of this conventional package mode conduction:
1, Metal Substrate island volume is too little
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and in limited packaging body, to imbed the interior pin (as shown in Figures 1 and 2) of metal of Metal Substrate island and signal, power supply conduction usefulness simultaneously, very the little so effective area on Metal Substrate island and volume just seem, and the function of the heat radiation of high heat also will be served as in the Metal Substrate island simultaneously, will seem deficiency more.
2, baried type Metal Substrate island (as shown in Figures 1 and 2)
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and the Metal Substrate island is about dependence or four fine support bars in corner fix or support metal Ji Dao, also because the characteristic of this fine support bar, the heat that has caused the Metal Substrate island to be absorbed from the chip, can't conduct out from fine support bar fast, so the heat of chip can't or be transmitted to the packaging body external world fast, caused the life-span quick aging of chip even burn or burnt out.
3, Metal Substrate island exposed type (as shown in Figures 3 and 4)
Though expose on the Metal Substrate island, can provide also will good heat-sinking capability than the heat sinking function of baried type, because the volume on Metal Substrate island and area still very little in packaging body, so heat dissipation capability can be provided, still very limited.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, providing a kind of can provide heat dissipation capability strong down and up arranged resin circuit board and chip packaging structure with radiation block.
The object of the present invention is achieved like this: a kind of down and up arranged resin circuit board and chip packaging structure with radiation block, include the single or multiple lift resin circuit board that is carried of chip, chip below, conduction or nonconducting heat conduction bonding material I and the plastic-sealed body between metal coupling, chip and the described single or multiple lift resin circuit board that chip is used to the signal interconnection of single or multiple lift resin circuit board, above described chip, be provided with radiating block, be equipped with conduction or nonconducting heat conduction bonding material II between this radiating block and the described chip.
The invention has the beneficial effects as follows:
The present invention serves as the function of the heat radiation of high heat by addition radiating block above chip, can provide heat dissipation capability strong, makes the heat of chip can be transmitted to the packaging body external world fast.Can be applied in and make it become height or superelevation heat radiation (High Thermal or Super High Thermal) ability on the packaging body of general packing forms and the packaging technology, can become SHT-FBP/QFN as FBP can become SHT-QFN/BGA and can become SHT-BGA/CSP and can become SHT-CSP ...Avoided the life-span quick aging of chip even burn or burnt out.
(4) description of drawings
Fig. 1 is Metal Substrate island baried type chip-packaging structure schematic diagram in the past.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 is Metal Substrate island exposed type chip-packaging structure schematic diagram in the past.
Fig. 4 is the vertical view of Fig. 3.
Fig. 5 is a down and up arranged resin circuit board and chip packaging structure with radiation block schematic diagram of the present invention.
Reference numeral among the figure:
Conduction or nonconducting heat conduction bonding material I2, chip 3, conduction or nonconducting heat conduction bonding material II6, radiating block 7, plastic-sealed body 8, resin circuit board 9, metal coupling 10.
(5) embodiment
Referring to Fig. 5, Fig. 5 is a down and up arranged resin circuit board and chip packaging structure with radiation block schematic diagram of the present invention.As seen from Figure 5, down and up arranged resin circuit board and chip packaging structure with radiation block of the present invention, include the single or multiple lift resin circuit board 9 that is carried of chip 3, chip below, conduction or nonconducting heat conduction bonding material I2 and the plastic-sealed body 8 between metal coupling 10, chip and the described single or multiple lift resin circuit board that chip is used to the signal interconnection of single or multiple lift resin circuit board, above described chip 3, be provided with radiating block 7, be equipped with conduction or nonconducting heat conduction bonding material II6 between this radiating block 7 and the described chip 3.
The material of described radiating block 7 can be copper, aluminium, pottery or alloy etc.
The material of described metal coupling 10 can be tin, gold or alloy etc.

Claims (3)

1. down and up arranged resin circuit board and chip packaging structure with radiation block, include chip (3), the single or multiple lift resin circuit board (9) that is carried of chip below, the metal coupling that chip is used to the signal interconnection of single or multiple lift resin circuit board (10), conduction between chip and the described single or multiple lift resin circuit board or nonconducting heat conduction bonding material I (2) and plastic-sealed body (8), it is characterized in that being provided with radiating block (7), be equipped with conduction or nonconducting heat conduction bonding material II (6) between this radiating block (7) and the described chip (3) in described chip (3) top.
2. a kind of down and up arranged resin circuit board and chip packaging structure with radiation block according to claim 1, the material that it is characterized in that described radiating block (7) is copper, aluminium, pottery or alloy.
3. a kind of down and up arranged resin circuit board and chip packaging structure with radiation block according to claim 1, the material that it is characterized in that described metal coupling (10) is tin, gold or alloy.
CN201010112819A 2010-01-29 2010-01-29 Down and up arranged resin circuit board and chip packaging structure with radiation block Pending CN101770997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010112819A CN101770997A (en) 2010-01-29 2010-01-29 Down and up arranged resin circuit board and chip packaging structure with radiation block

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010112819A CN101770997A (en) 2010-01-29 2010-01-29 Down and up arranged resin circuit board and chip packaging structure with radiation block

Publications (1)

Publication Number Publication Date
CN101770997A true CN101770997A (en) 2010-07-07

Family

ID=42503761

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010112819A Pending CN101770997A (en) 2010-01-29 2010-01-29 Down and up arranged resin circuit board and chip packaging structure with radiation block

Country Status (1)

Country Link
CN (1) CN101770997A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012174833A1 (en) * 2011-06-21 2012-12-27 中兴通讯股份有限公司 Plastic packaged chip and manufacturing method thereof
CN102956569A (en) * 2011-08-26 2013-03-06 三菱电机株式会社 Semiconductor device and method of manufacture thereof
CN108962762A (en) * 2018-07-13 2018-12-07 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012174833A1 (en) * 2011-06-21 2012-12-27 中兴通讯股份有限公司 Plastic packaged chip and manufacturing method thereof
CN102956569A (en) * 2011-08-26 2013-03-06 三菱电机株式会社 Semiconductor device and method of manufacture thereof
CN102956569B (en) * 2011-08-26 2016-01-13 三菱电机株式会社 Semiconductor device and manufacture method thereof
CN108962762A (en) * 2018-07-13 2018-12-07 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method

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Open date: 20100707