CN101770947B - Poly(p-phenylene benzobisoxazole) fiber surface-processing method - Google Patents
Poly(p-phenylene benzobisoxazole) fiber surface-processing method Download PDFInfo
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- CN101770947B CN101770947B CN2008102049623A CN200810204962A CN101770947B CN 101770947 B CN101770947 B CN 101770947B CN 2008102049623 A CN2008102049623 A CN 2008102049623A CN 200810204962 A CN200810204962 A CN 200810204962A CN 101770947 B CN101770947 B CN 101770947B
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Abstract
The invention provides a PBO surface-processing method in order to reduce the leakage current in PBO with the surface splashed with metal and improve the performance of an integrated circuit. The method uses argon ions to etch the PBO surface splashed with metal.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of Poly-p-phenylene benzobisthiazole (PBO, Poly-P-phenylene-2,6-benzobisoxazole) surface treatment method.
Background technology
Based on unique physical propertys such as good mechanical stretching and fracture strengths, PBO is widely used in technique of integrated circuit packaging as passivating material.
For simplicity's sake, provide the common simple application model of PBO as passivation layer below, this application model is applicable to kinds of processes, and for example salient point forms the making of technology bumps lower metal layer (UBM) or re-wiring layer (RDL) etc.
Figure 1A～1C is for the structural representation of existing PBO as passivation layer, and in conjunction with this figure, the flow process that application PBO does passivation layer is generally:
With reference to Figure 1A, at first on matrix 10, deposit PBO layer 11;
For different technology, the structure difference of this matrix 10 for example forms the making of UBM in the technology for some salient point, and this matrix 10 has been made the substrate of aluminium cushion block for comprising semiconductor device and upper surface;
With reference to Figure 1B, on PBO layer 11, form splash-proofing sputtering metal layer 12, the material of this splash-proofing sputtering metal layer 12 includes but not limited to titanium (Ti) and copper (Cu) etc.;
With reference to Fig. 1 C, remove part splash-proofing sputtering metal layer 12, expose PBO layer 11.
Wherein, may comprise other treatment steps between above-mentioned each step based on various different process.
PBO uses increasingly extensive as passivating material, but in the technology that adopts above-mentioned application model, owing to having under the situation of metal sputtering, the leakage current in PBO layer 11 is very big, and the order of magnitude is in microampere order, and this will reduce performance of integrated circuits.
When adopting other passivating material polyimides (PI) and benzocyclobutene (BCB) etc. to make passivation layer, the existing scheme that reduces leakage current is normally: after exposing passivation layer, use oxygen or carbon tetrafluoride that this passivation layer is carried out ashing treatment, with the reduction leakage current, thereby improve performance of integrated circuits.
But since with other passivating material for example PI and BCB etc. compare, PBO is stronger to the adsorption capacity of metal electron, it is excessive that the scheme that therefore above-mentioned ashing treatment reduces leakage current can't solve PBO passivation layer 11 leakage currents, reduces the problem of performance of integrated circuits.
Summary of the invention
The invention provides the PBO surface treatment method,, improve performance of integrated circuits to reduce the surface via the leakage current among the PBO of metal sputtering.
The present invention proposes the PBO surface treatment method, the method comprising the steps of: the PBO surface of using the argon ion etching metal sputtering to cross, etch period is 10 seconds～30 seconds, the thickness of the Poly-p-phenylene benzobisthiazole that etching is removed is 100 dusts～400 dusts, to reduce the surface via the leakage current among the PBO of metal sputtering.
Optionally, described PBO is as the passivation layer in the stud bump making technology, and sputter has metal level on this PBO surface; And remove the described metal level of part and form ubm layer or re-wiring layer in etching, expose PBO after, use the described PBO of argon ion etching surface.
Optionally, when the metal level of described sputter is ubm layer, before described argon ion etching step, also comprise: Semiconductor substrate is provided; Form metal bed course and PBO passivation layer on Semiconductor substrate, described metal bed course is embedded in the PBO passivation layer, and exposes the metal bed course by first opening of PBO passivation layer; Sputter forms described metal level in the PBO passivation layer and first opening; On metal level, form photoresist, define metal bed course shape, form second opening, expose metal level; In second opening, form successively on the metal level and electroplate inculating crystal layer and salient point layer; Remove photoresist; And etching removal part metals layer, form ubm layer, expose the PBO passivation layer.
The present invention is by adopting the PBO surface of argon ion etching surface via metal sputtering, can remove certain thickness PBO passivation layer, make the order of magnitude of the leakage current numerical value in the PBO passivation layer be reduced to the skin peace, even receive the peace level, reduced the leakage current in the PBO passivation layer greatly by microampere order.
The present invention is also by being used as the passivation layer in the stud bump making technology as described PBO, when sputter has metal level on this PBO surface, remove the described metal level of part and form ubm layer or re-wiring layer in etching, after exposing PBO, use the described PBO of argon ion etching surface, thereby avoided the excessive problem of PBO passivation layer leakage current in the existing stud bump making technology, improved performance of integrated circuits.
Description of drawings
Figure 1A～1C for the structural representation that existing PBO is used as passivation layer is;
Fig. 2 is the flow chart of the PBO surface treatment method of embodiment of the invention proposition;
The structural representation of Fig. 3 when PBO being carried out surface treatment in the embodiment of the invention;
Fig. 4 A～4I is the structural representation in the first embodiment of the invention salient point treatment process.
Embodiment
Cross the leakage problem of the PBO of metal for solving surface sputtering, the embodiment of the invention proposes following PBO surface treatment method.
Fig. 2 is the flow chart of the PBO surface treatment method of embodiment of the invention proposition, and in conjunction with this figure, the method comprising the steps of: the PBO surface of using the argon ion etching metal sputtering to cross.Described etch period preferable at 10 seconds～30 seconds; Wherein when etch period is 10～20 seconds, leakage current numerical value among the PBO can be reduced to skin peace (pA) level approximately, when etch period is 25～30 seconds, described numerical value can be reduced to approximately and receives peace (nA) grade; When this external etch period was 10～25 seconds, the effect that reduces leakage current was more stable.
The metal of described sputter can have multiple, for example a kind of in titanium, copper, nickel and the aluminium or their combination.By said method, the leakage current among the PBO reduces greatly, has improved the performance of integrated circuit.
Below with reference to accompanying drawings the present invention is described in more detail, has wherein represented the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, the unnecessary details because they can be the present invention and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Is example with the described PBO of background technology as the concise and to the point model of passivation layer, implement above-mentioned PBO surface treatment method process can for:
The structural representation of Fig. 3 when PBO being carried out surface treatment in the first embodiment of the invention, in conjunction with this figure, this implementation process comprises:
Step a1, at first deposition PBO layer 21 on matrix 20;
Step a2 forms splash-proofing sputtering metal layer 22 on PBO layer 21;
Step a3, this splash-proofing sputtering metal layer 22 of etched portions exposes the PBO layer 21 that is not covered by this splash-proofing sputtering metal layer 22;
Step a4, the PBO layer 21 that adopts argon ion etching to expose obtains new PBO layer 21a.
Based on different technology, may there be other technological processes between above-mentioned steps a2 and a3.
Embodiment one
With the splash-proofing sputtering metal layer after the etching 22 is that the UBM layer is an example, forms in the technology at the salient point that does not contain the RDL layer, with reference to Fig. 4 A～4I, is the structural representation in the first embodiment of the invention salient point treatment process.The implementation process of step a1～a4 can but be not limited to:
With reference to Fig. 4 A, Semiconductor substrate 40 is provided, formed metal bed course 41 on this Semiconductor substrate;
With reference to Fig. 4 B, on Semiconductor substrate 40 and metal bed course 41, form PBO passivation layer 42, described metal bed course 41 is embedded in the PBO passivation layer 42, and exposes metal bed course 41 by first opening 43 of PBO passivation layer 42;
Described formation metal bed course 41 and PBO passivation layer 42 are techniques well known, as an embodiment of the invention, at first form the first metal layer on Semiconductor substrate 40, described the first metal layer is by aluminium, copper or its alloy composition, and its thickness range is 100～400nm; Described the first metal layer adopts the physical vapor deposition (PVD) preparation, adopts existing photoetching and the graphical the first metal layer of etching technique then, forms metal bed course 41;
Then on Semiconductor substrate 40 and metal bed course 41, form PBO passivation layer 42; Described PBO passivation layer 42 adopts the spin coating mode to prepare, and thickness range is 2～10 microns, adopts existing photoetching and developing technique then, forms first opening on PBO passivation layer 42, and described first opening exposes metal bed course 41;
With reference to Fig. 4 C, on PBO passivation layer 42 and metal bed course 41, form metal level 44, described metal level 44 constitutes for a kind of among Al, Ni, Cu, Ti, the Cr or they, and thickness is 200～1500nm.
With reference to Fig. 4 D, on metal level 44, form photoresist layer 45, define the shape of backing metal 41 by existing light section technology, expose then, the photoresist in metal bed course 41 zones that are exposed becomes water-soluble substances, directly remove, in photoresist layer 45, form the metal level 44 on the metal bed course 41 that second opening exposes lower floor.
With reference to Fig. 4 E, be mask with photoresist layer 45, in second opening, form on the metal level 44 and electroplate inculating crystal layer 46, described plating inculating crystal layer 46 constitutes for Cu, Ni or its, and described plating inculating crystal layer 46 is as electroplating the inculating crystal layer that forms salient point layers 24, and thickness range is 1～10 micron.
With reference to Fig. 4 F, continuing with photoresist layer 45 is mask, is electroplating formation salient point layer 47 on the inculating crystal layer 46.Forming salient point layer 47 is technology as well known to those skilled in the art, as an embodiment of the invention, form salient point layer 47 by plating mode, described salient point layer 47 is that tin (Sn), tin lead (SnPb), Xi Yin (SnAg) or high plumbous (high lead) alloy constitute, and the thickness range of described salient point layer 47 is 50～400 microns.
With reference to Fig. 4 G, remove photoresist layer 45, removing photoresist layer 45 is technology as well known to those skilled in the art.
With reference to Fig. 4 H, etching sheet metal 44 forms ubm layer 44a.Behind etching sheet metal 44, at PBO passivation layer 42 remained on surface metal ions, cause leakage current easily.
With reference to Fig. 4 I, adopt argon ion etching PBO passivation layer 42, PBO passivation layer 42 etchings that do not covered by ubm layer 44a are removed 100～400 dusts, form PBO passivation layer 42a, its etch period is 15～40 seconds.
Carry out follow-up flow process then, finally form salient point.
Present embodiment forms in the technology at salient point, adopts argon ion etching to remove the metal ion on PBO passivation layer 42 surfaces, has reduced the leakage current in the PBO passivation layer 42 greatly, has improved performance of integrated circuits.
Embodiment two
If salient point forms the formation that comprises the RDL layer in the technology, when forming the PBO passivation layer, the metal of sputter RDL layer correspondence on the PBO passivation layer again, then can be in technological processes such as the follow-up photoetching of process, the RDL layer is carried out etching, after exposing the PBO passivation layer under the RDL layer, adopt argon ion to carry out etching to the PBO passivation layer that exposes, to reduce the leakage current in this PBO passivation layer.Described etch period can be with reference to the data of the foregoing description one.In conjunction with the existing disclosed technology that comprises the RDL layer process flow, infer the implementing procedure of embodiment two easily, repeat no more herein.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. a Poly-p-phenylene benzobisthiazole surface treatment method is characterized in that, comprising:
The Poly-p-phenylene benzobisthiazole surface of using the argon ion etching metal sputtering to cross; Described Poly-p-phenylene benzobisthiazole is as the passivation layer in the stud bump making technology, and sputter has metal level on this Poly-p-phenylene benzobisthiazole surface; And remove the described metal level of part and form ubm layer or re-wiring layer in etching, after exposing Poly-p-phenylene benzobisthiazole, use the described Poly-p-phenylene benzobisthiazole of argon ion etching surface, etch period is 10 seconds～30 seconds, the thickness of the Poly-p-phenylene benzobisthiazole that etching is removed is 100 dusts～400 dusts, to reduce the surface via the leakage current among the PBO of metal sputtering.
2. the method for claim 1 is characterized in that, when the metal level of described sputter is ubm layer, before described argon ion etching step, also comprises:
Semiconductor substrate is provided;
On Semiconductor substrate, form metal bed course and Poly-p-phenylene benzobisthiazole passivation layer, described metal bed course is embedded in the Poly-p-phenylene benzobisthiazole passivation layer, and exposes the metal bed course by first opening of Poly-p-phenylene benzobisthiazole passivation layer;
Sputter forms described metal level in the Poly-p-phenylene benzobisthiazole passivation layer and first opening;
On metal level, form photoresist, define metal bed course shape, form second opening, expose metal level;
In second opening, form successively on the metal level and electroplate inculating crystal layer and salient point layer;
Remove photoresist; And
Etching is removed the part metals layer, forms ubm layer, exposes the Poly-p-phenylene benzobisthiazole passivation layer.
3. method as claimed in claim 1 or 2 is characterized in that, described etch period is 15 seconds～30 seconds.
4. the method for claim 1 is characterized in that, described etch period is 10 seconds～20 seconds.
5. the method for claim 1 is characterized in that, described etch period is 25 seconds～30 seconds.
6. the method for claim 1 is characterized in that, described metal is a kind of in titanium, copper, nickel and the aluminium or their combination.
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| CN106952832B (en) * | 2016-01-06 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor structure |
| CN108962774B (en) * | 2017-05-27 | 2020-08-04 | 中芯国际集成电路制造(上海)有限公司 | Method for improving surface uniformity of redistribution layer |
| CN107968056B (en) * | 2017-11-23 | 2019-12-06 | 长江存储科技有限责任公司 | Preparation process of welding pad structure |
| CN110729269A (en) * | 2018-07-17 | 2020-01-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| EP0305268A1 (en) * | 1987-08-18 | 1989-03-01 | L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Process for reactive ion etching at a low self-biasing voltage using additives of inert gases |
| CN1288592A (en) * | 1998-01-22 | 2001-03-21 | 时至准钟表股份有限公司 | Method of fabricating semiconductor device |
| CN101026204A (en) * | 2006-02-24 | 2007-08-29 | 中国科学院半导体研究所 | Method for preparing power-micro structure LED tube core utilizing flip chip technology |
| CN101207046A (en) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Bump formation method |
| CN101235590A (en) * | 2008-02-25 | 2008-08-06 | 北京科技大学 | Ultrasonic chemistry surface modifying method for PBO fiber |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0305268A1 (en) * | 1987-08-18 | 1989-03-01 | L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Process for reactive ion etching at a low self-biasing voltage using additives of inert gases |
| CN1288592A (en) * | 1998-01-22 | 2001-03-21 | 时至准钟表股份有限公司 | Method of fabricating semiconductor device |
| CN101026204A (en) * | 2006-02-24 | 2007-08-29 | 中国科学院半导体研究所 | Method for preparing power-micro structure LED tube core utilizing flip chip technology |
| CN101207046A (en) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Bump formation method |
| CN101235590A (en) * | 2008-02-25 | 2008-08-06 | 北京科技大学 | Ultrasonic chemistry surface modifying method for PBO fiber |
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