CN101764614B

CN101764614B - V-shaped sampling method of AD converter based on FPGA

Info

Publication number: CN101764614B
Application number: CN200910263115A
Authority: CN
Inventors: 李从飞
Original assignee: NANJING HONGYI ELECTRIC AUTOMATION CO Ltd
Current assignee: NANJING HONGYI ELECTRIC AUTOMATION CO Ltd
Priority date: 2009-12-16
Filing date: 2009-12-16
Publication date: 2012-09-26
Anticipated expiration: 2029-12-16
Also published as: CN101764614A

Abstract

The invention relates to a V-shaped sampling method of an AD converter based on FPGA, and the method comprises the following steps: analogue switches are accessed to the AD converter, and the AD converter is connected with the FPGA. The FPGA sampling process comprises the following steps: the FPGA selects a first channel of all analogue switches, then the AD converter is started to carry out conversion, data after conversion are read and then stored in an RAM inside the FPGA, and then the FPGA selects a second channel of the analogue switches, and so on; after the last channel of the analogue switches is selected, the FPGA selects the last channel, the last but one until the first channel again; after the data is collected, the FPGA reads the data from the RAM, and corresponding data of a channel which are collected in step 1) and step 2) are averaged to obtain one sampling value of the channel.

Description

The AD converter V-arrangement method of sampling based on FPGA

Technical field

The invention belongs to the signal controlling field, the method that the particularly a kind of FPGA of utilization control AD converter carries out the V-arrangement sampling.

Background technology

Along with the development of automatic technology, it is essential that multichannel data acquisition is used, and AD converter is to realize the Primary Component of analog signal to digital signal.It is asynchronous that translation function when a slice AD conversion chip can be realized multichannel analog signals, but along with the increasing of sampling channel, the use of multi-disc AD converter must cause sampling, and the sampling instant between the different AD converters has deviation.For some automation equipment, the asynchronous phase difference that will produce collection capacity of sampling, serious meeting produces ill effect, and like the electric power system microcomputer protecting device, the phase difference of acquired signal just possibly cause protecting malfunction.

Summary of the invention

The present invention proposes a kind of AD converter V-arrangement method of sampling, utilize FPGA control AD converter and multiway analog switch, repeatedly start the AD conversion, read the data after the conversion based on FPGA, and through supplying CPU to read after the simple Filtering Processing.

Technical scheme of the present invention is: based on the AD converter V-arrangement method of sampling of FPGA; This method comprises the following steps: analog switch is inserted AD converter; AD converter conversion multi-analog, a slice analog switch is inserted on every road, and a plurality of analog switches insert AD converter; AD converter is connected with FPGA, and said FPGA sampling process is:

1) FPGA at first selects the first passage of all analog switches, restarts AD converter conversion, reads the data after the commentaries on classics, deposits the FPGA internal RAM in, and FPGA selects the second channel of analog switch more then, and the rest may be inferred;

2) selected after last passage of analog switch, FPGA selects last passage once more, and penult then is until first passage;

3) after all data acquisitions finished, FPGA is reading of data from RAM, step 1) and step 2) the respective channel data of gathering average, and obtain a sampled value of this passage.

The above-mentioned method of sampling, promptly FPGA gathers the analog quantity of all passages in order, gathers the analog quantity of all passages then once more according to backward, and all results of gained deposit the internal RAM of FPGA in, V-arrangement sampling promptly of the present invention.

As further improvement of the present invention, FPGA is repeating step 1 repeatedly) and step 2) sampling process, and then carry out step 3), to obtain higher sampling precision.

The invention has the advantages that:

1, reduce the cpu load rate, give FPGA with the demanding sampling work of real-time and accomplish, because FPGA is the concurrent working device, all working carries out simultaneously, has improved the speed of sampling and the precision of sampling instant control.

2, improve the sampled data precision, have FPGA control AD converter repeatedly to sample after, averaging processing, improved the precision of data, filtering the interference signal in the data.

3, reduced time difference between multi-channel sampling.Utilize minimum hardware resource to realize multichannel data acquisition, the utilization of V-arrangement sampling makes and reaches unanimity for interchannel average sample constantly, has reduced each interchannel phase error that sampling causes.

4, reduced the hardware cost of system, adopted the V-arrangement method of sampling can improve the utilance of AD converter greatly, the function with less hardware resource realization multichannel collecting has reduced hardware cost.

Description of drawings

Fig. 1 is a V-arrangement controlling of sampling structure chart in the embodiment of the invention 1.

Fig. 2 is the FPGA cut-away view of the embodiment of the invention 1.

Embodiment

Provide practical implementation method of the present invention below in conjunction with accompanying drawing.

Embodiment 1

Fig. 1 is an example with 6 road AD converters and 8 path analoging switch, has provided the hardware structure diagram of the AD converter V-arrangement method of sampling based on FPGA according to the invention.For fear of the interference between each road analog quantity, every analog switch the 8 road input grounding all switches to this road of ground connection with analog switch after each the switching and discharges.Fig. 2 is the FPGA cut-away view.

During FPGA work, at first all electronic switches are switched to the 1st passage, at this moment, the 1st, 8,15,22,29,36 road signals get into the ALT-CH alternate channel of AD converter.After AD samples to this signal sampled data deposited in the internal RAM of FPGA.FPGA switches to ground connection with the input of electronic switch earlier then, switches to the 2nd passage again, starts the AD sampling.The rest may be inferred until the 7th passage, after the 7th passage finishing collecting, FPGA again according to from height to low order, from the 7th passage to the 1 passage image data.If sampling interval and AD conversion speed allow, FPGA can also carry out the V-arrangement sampling of next round.But for convenience of calculation, general sampling number is decided to be 4 times or 8 times 2 times.

After all V-arrangement sampled data finishing collecting, the mean value calculation module is taken out the value of averaging with corresponding all data of each passage and is calculated, and obtains the final sampled value of this passage.

Claims

1. AD converter V-arrangement method of sampling based on FPGA; This method comprises the following steps: analog switch is inserted AD converter, AD converter conversion multi-analog, and a slice analog switch is inserted on every road; A plurality of analog switches insert AD converter; AD converter is connected with FPGA, it is characterized in that, said FPGA sampling process is:

2. the method for sampling according to claim 1 is characterized in that, said step 1) and step 2) the sampling process repetitive cycling repeatedly, and then carry out step 3).

3. the method for sampling according to claim 2 is characterized in that, said step 1) and step 2) sampling process repetitive cycling 4-8 time.