CN101741455A - Equalizer and method applying same - Google Patents
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- CN101741455A CN101741455A CN200810176822A CN200810176822A CN101741455A CN 101741455 A CN101741455 A CN 101741455A CN 200810176822 A CN200810176822 A CN 200810176822A CN 200810176822 A CN200810176822 A CN 200810176822A CN 101741455 A CN101741455 A CN 101741455A
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Abstract
The invention discloses an equalizer and a method applying the same. The equalizer comprises a first feed forward equalizing module, a second feed forward equalizing module and a phase error corrector. The first feed forward equalizing module and the second feed forward equalizing module respectively receive an input real part component signal and an input imaginary part component signal of a plurality of input signals and respectively equalize the input real part component signal and the input imaginary part component signal to generate a first real part component signal and a first imaginary part component signal. The phase error corrector is coupled to the first feed forward equalizing module and the second feed forward equalizing module and used for adjusting the plural phase corresponding to the first real part component signal and the first imaginary part component signal according to phase error information so as to generate a second real part component signal and a second imaginary part component signal.
Description
Technical field
The present invention relates to a kind of eqalizing cricuit and correlation technique thereof, relate in particular to and a kind of eqalizing cricuit and phase-error corrector are done the better apparatus and method that combine with the usefulness that promotes eqalizing cricuit.
Background technology
In communication system; disturb (Inter Symbol Interference between Fu Yuan; ISI) be a kind of suitable common phenomena; its main reason is multi-path transmission (multipath propagation); therefore, signal receiving end can add when eqalizing cricuit (equalizer) solves the signal transmission usually because the influence that the multi-path transmission is caused.
And utilize eqalizing cricuit to handle complex signal (vestigial sideband signal for example, VSB) time, if when only using single eqalizing cricuit to come,, can limit the usefulness of eqalizing cricuit because the signal of eqalizing cricuit still exists phase error to the processing such as real part composition grade in the complex signal.And, still can adjust its phase difference though handle signal afterwards by phase-error corrector through eqalizing cricuit, because phase-error corrector has only one dimension input (the real part composition is only arranged), also can cause the usefulness of eqalizing cricuit not good.Therefore, how to promote the usefulness of eqalizing cricuit, promptly become one of the important topic in the design field.
Summary of the invention
One of purpose of the present invention is to provide a kind of eqalizing cricuit and correlation technique thereof, to solve the problem in the prior art.
Embodiments of the invention disclose a kind of eqalizing cricuit, and it includes first module such as feedforward gradeization, second feedforward etc. and changes module and phase-error corrector.Change modules such as first feedforward become sub-signal in order to the input real part that receives complex input signal, and will import real part and become processing such as sub-signal grade to become sub-signal to produce first real part.Change modules such as second feedforward become sub-signal in order to the input imaginary part that receives complex input signal, and will import imaginary part and become processing such as sub-signal grade to become sub-signal to produce first imaginary part.Phase-error corrector is coupled to the first feedforward module such as gradeization and second feedforward etc. and changes module, is used for adjusting first real part according to phase error information and becomes sub-signal to become sub-signal pairing one plural phase place to become the sub-signal and second imaginary part to become sub-signal to produce second real part with first imaginary part.Wherein, change module such as second feedforward comes to become processing such as sub-signal grade to importing imaginary part according to employed joint efficiencies of change module such as first feedforwards.
Embodiments of the invention disclose a kind of method that is applied to an eqalizing cricuit in addition, and this method includes: the input real part that receives complex input signal becomes sub-signal, and will import real part and become processing such as sub-signal grade to become sub-signal to produce first real part; The input imaginary part that receives complex input signal becomes sub-signal, and will import imaginary part and become processing such as sub-signal grade to become sub-signal to produce first imaginary part; And adjust first real part and become sub-signal to become sub-signal pairing one plural phase place to become the sub-signal and second imaginary part to become sub-signal with first imaginary part to produce second real part according to a phase error information.
Description of drawings
Fig. 1 is the schematic diagram of first embodiment of eqalizing cricuit of the present invention.
Fig. 2 is the schematic diagram of second embodiment of eqalizing cricuit of the present invention.
Fig. 3 is applied to the flow chart of an example operation of the method for eqalizing cricuit for the present invention.
Fig. 4 is applied to the flow chart of another example operation of the method for eqalizing cricuit for the present invention.
[main element symbol description]
100,200 eqalizing cricuits
110 first modules such as feedforward gradeization
120 second modules such as feedforward gradeization
130 phase-error corrector
140 first arithmetic elements
150 data slicers
160 feedback equalization modules
X[n] complex input signal
x
r[n] input real part becomes sub-signal
x
i[n] input imaginary part becomes sub-signal
y
R1[n] first real part becomes sub-signal
y
I1[n] first imaginary part becomes sub-signal
y
R2[n] second real part becomes sub-signal
y
I2[n] second imaginary part becomes sub-signal
y
R3[n] the 3rd real part becomes sub-signal
Eqo
r[n] output real part becomes sub-signal
The Sd testing result
d
r[n], d
i[n] phase error information
210 first delayers
220 filters
230 first arithmetic elements
240 second delayers
250 phase error estimation and phase error devices
y
i' [n] estimate that imaginary part becomes sub-signal
y
Di2[n] postponed second imaginary part and become sub-signal
Eqo
Di[n] postponed to export imaginary part and become sub-signal
Eqo
Dr[n] postponed to export real part and become sub-signal
Eqo
d[n] postponed plural output signal
302～314,410～450 steps
Embodiment
Please refer to Fig. 1, Fig. 1 is the schematic diagram of first embodiment of eqalizing cricuit 100 of the present invention.Eqalizing cricuit 100 comprises (but being not limited to) first module such as feedforward gradeization 110, second feedforward etc. and changes module 120, phase-error corrector 130, first arithmetic element 140, data slicer 150 and feedback equalization module 160.As shown in Figure 1,110 reception complex input signal x[n such as the first feedforward module such as gradeizations] input real part composition (real-part component) signal x
r[n], and will import real part and become sub-signal x
rProcessing such as [n] grade becomes sub-signal y to produce first real part
R1[n].X[n such as complex input signal such as 120 receptions such as the second feedforward module such as gradeizations] input imaginary part composition (imaginary-part component) signal x
i[n], and will import imaginary part and become sub-signal x
iProcessing such as [n] grade becomes sub-signal y to produce first imaginary part
I1[n].And phase-error corrector (phase error corrector) 130 is coupled to change modules 120 such as first module such as feedforward gradeization 110 and second feedforward, is used for according to phase error information d
r[n], d
i[n] adjusts first real part and becomes sub-signal y
R1[n] becomes sub-signal y with first imaginary part
I1[n] pairing plural phase place becomes sub-signal y to produce second real part
R2[n] and second imaginary part become sub-signal y
I2[n].In addition, first arithmetic element 140 is coupled to phase-error corrector 130, is used for second real part is become sub-signal y
R2[n] becomes sub-signal y with the 3rd real part
R3[n] carries out computing and becomes sub-signal eqo to produce the output real part
r[n].Data slicer (slicer) 150 is coupled to first arithmetic element 140, is used for carrying out rigid the decision-making and becomes sub-signal eqo in the output real part
rOn [n], to produce testing result Sd.Feedback equalization module 160 then is coupled to the data slicer 150 and first arithmetic element 140, is used for changes such as execution to handle on testing result Sd, becomes sub-signal y to produce the 3rd real part
R3[n].
Note that above-mentioned complex input signal x[n] (include the input real part and become sub-signal x
r[n] and input imaginary part become sub-signal x
i[n]) can be a vestigial sideband (vestigial sideband, VSB) signal, but the present invention is not limited thereto, also can be the signal of other kinds.And eqalizing cricuit 100 can be a decision feedback equalization device, and (decision feedback equalizer, DFE), but this is not a restrictive condition of the present invention, also can be the eqalizing cricuit of other kinds.
Please note again, change modules 120 such as the change module 110 such as first feedforward and second feedforward can each be implemented it by a joint delay line eqalizing cricuit (tapped delay line equalizer), and second feedforward waits and changes module 120 according to change module 110 employed joint efficiencies (tap coefficient) f such as first feedforwards
r[n] comes the input imaginary part is become sub-signal x
iProcessing such as [n] grade.In other words, the identical joint efficiency f of module 110 employings is changed in second module such as feedforward gradeization 120 and first feedforward etc.
r[n] comes respectively the input real part to be become sub-signal x
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, but this only is the preferred embodiments of the present invention, and other can reach identical purpose and the reality of spirit according to the invention is made mode, also belong to covering scope of the present invention.
In the present embodiment, first arithmetic element 140 is realized that by an adder then adder becomes sub-signal y with second real part
R2[n] deducts the 3rd real part and becomes sub-signal y
R3[n] becomes sub-signal eqo to produce the output real part
r[n], but the present invention is not limited thereto, also can adopt the arithmetic unit of other kinds to implement.
As shown in Figure 1, by change modules 120 such as change module 110 such as first feedforward and second feedforwards input real part is become sub-signal x respectively
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, the signal packet that then inputs to phase-error corrector 130 contains the two dimension input, and (that is first real part becomes sub-signal y
R1[n] becomes sub-signal y with first imaginary part
I1[n]), thus, not only the effect of phase-error corrector 130 adjustment phase differences can improve, and can also further promote the usefulness of eqalizing cricuit 100.In addition, second real part exported of phase-error corrector 130 becomes sub-signal y
R2[n] via the processing of decision feedback fraction (that is first arithmetic element 140, data slicer 150 and feedback equalization module 160), the output real part that can obtain eqalizing cricuit 100 becomes sub-signal eqo again
r[n].
Certainly, above-mentioned eqalizing cricuit 100 only is one of feasible embodiment of the present invention, and in other embodiment, can design more function promotes eqalizing cricuit in eqalizing cricuit usefulness.Please refer to Fig. 2, Fig. 2 is the schematic diagram of second embodiment of eqalizing cricuit 200 of the present invention.The eqalizing cricuit 200 of Fig. 2 is similar with eqalizing cricuit 100 shown in Figure 1, and both are described below difference.Eqalizing cricuit 200 also comprises first delayer 210, filter 220, second arithmetic element 230, second delayer 240 and to bit error estimator 250.First delayer 210 is coupled to phase-error corrector 130, becomes sub-signal y in order to postpone second imaginary part
I2[n] postponed second imaginary part with generation and become sub-signal y
Di2[n].Filter 220 is coupled to feedback equalization module 160, becomes sub-signal y in order to receive the 3rd real part
R3[n], and become sub-signal y according to the 3rd real part
R3[n] produces and estimates that imaginary part becomes sub-signal y
i' [n].Afterwards, second arithmetic element 230 will postpone second imaginary part more and become sub-signal y
Di2[n] becomes sub-signal y with the estimation imaginary part
i' [n] carry out computing (for example subtracting each other) and postponed to export imaginary part and become sub-signal eqo to produce
Di[n].240 of second delayers are coupled to first arithmetic element 140, become sub-signal eqo in order to postpone the output real part
r[n] postponed to export real part with generation and become sub-signal eqo
Dr[n] wherein postponed to export real part and become sub-signal eqo
Dr[n] with postpone to export imaginary part and become sub-signal eqo
Di[n] constitutes one and postponed plural output signal e qo
d[n].In addition, phase error estimation and phase error device 250 is coupled to phase-error corrector 130, and becomes sub-signal eqo according to testing result Sd, output real part
r[n], postpone to export real part and become sub-signal eqo
Dr[n] and postponed to export imaginary part and become sub-signal eqo
DiIn [n] at least one come estimating phase error information d
r[n], d
i[n].
In the present embodiment, filter 220 can be Hilbert conversion (Hilbert Transform) circuit or its approximator, but this is not a restrictive condition of the present invention.Then the 3rd real part becomes sub-signal y
R3[n] through after the filter 220, the estimated value that can produce the imaginary part composition (that is estimates that imaginary part becomes sub-signal y
i' [n]).About known to those skilled in the art the knowing of characteristic of Hilbert conversion (Hilbert Transform), for for purpose of brevity, detail section does not repeat them here.In addition, second arithmetic element 230 can realize by an adder, and then adder will postpone second real part and become sub-signal y
Dr2[n] deducts and estimates that imaginary part becomes sub-signal y
i' [n], the output of the delay imaginary part that then can obtain eqalizing cricuit 200 becomes sub-signal eqo
Di[n], but the present invention is not limited thereto, also can adopt the arithmetic unit of other kinds to implement.
Note that phase error information d
r[n], d
i[n] constitutes one group of complex signal, and can represent by following formula:
d
r[n]＝cosΔθ(1)
d
i[n]＝sinΔθ(2)
In complex signal was handled, what phase-error corrector 130 performed actions were represented was with (y
R1[n]+j*y
I1[n]) change the result after the angle delta θ, can following formula represent:
y
r2[n]＝y
r1[n]*d
r[n]-y
i1[n]*d
i[n](3)
y
i2[n]＝y
r1[n]*d
i[n]+y
i1[n]*d
r[n](4)
Can learn by Fig. 2, because phase error estimation and phase error device 250 can become sub-signal eqo according to testing result Sd, output real part
r[n], postpone to export real part and become sub-signal eqo
Dr[n] and postponed to export imaginary part and become sub-signal eqo
DiIn [n] at least one come estimating phase error information d
r[n], d
i[n] thus, can significantly improve first real part and become sub-signal y
R1[n] becomes sub-signal y with first imaginary part
I1The phase difference of [n] is with the usefulness of further lifting eqalizing cricuit.
Please refer to Fig. 3, Fig. 3 is applied to the flow chart of one of the method for eqalizing cricuit example operation for the present invention, it comprises (but being not limited to) following step (if note that and can obtain identical in fact result, then these steps might not be abideed by execution order shown in Figure 3 and carry out):
Step 302: beginning.
Step 304: the input real part that receives complex input signal becomes sub-signal, and will import real part and become processing such as sub-signal grade to become sub-signal to produce first real part.
Step 306: the input imaginary part that receives complex input signal becomes sub-signal, and will import imaginary part and become processing such as sub-signal grade to become sub-signal to produce first imaginary part.
Step 308: adjust first real part according to phase error information and become sub-signal to become sub-signal pairing one plural phase place with first imaginary part, become the sub-signal and second imaginary part to become sub-signal to produce second real part.
Step 310: become sub-signal to become sub-signal to carry out computing second real part, become sub-signal to produce the output real part with the 3rd real part.
Step 312: carry out rigid the decision-making and become on the sub-signal, to produce testing result in the output real part.
Step 314: changes such as execution are handled on this testing result, become sub-signal to produce the 3rd real part.
About each element that each step shown in Figure 3 please be arranged in pairs or groups shown in Figure 1, can understand each element and how to operate, so do not repeat them here.
Please refer to Fig. 4, Fig. 4 is applied to the flow chart of another example operation of the method for eqalizing cricuit for the present invention, and it comprises (but being not limited to) following steps:
Step 302: beginning.
Step 304: the input real part that receives complex input signal becomes sub-signal, and will import real part and become processing such as sub-signal grade to become sub-signal to produce first real part.
Step 306: the input imaginary part that receives complex input signal becomes sub-signal, and will import imaginary part and become processing such as sub-signal grade to become sub-signal to produce first imaginary part.
Step 308: adjust first real part according to phase error information and become sub-signal to become sub-signal pairing one plural phase place with first imaginary part, become the sub-signal and second imaginary part to become sub-signal to produce second real part.Execution in step 310,410.
Step 310: become sub-signal to become sub-signal to carry out computing with the 3rd real part second real part and become sub-signal to produce the output real part.Execution in step 312,440.
Step 312: carry out rigid the decision-making and become on the sub-signal, to produce testing result in the output real part.
Step 314: changes such as execution are handled on this testing result, become sub-signal to produce the 3rd real part.Execution in step 420.
Step 410: postpone second imaginary part and become sub-signal postponed second imaginary part and become sub-signal to produce.
Step 420: receive the 3rd real part and become sub-signal, and become the sub-signal generation to estimate that imaginary part becomes sub-signal according to the 3rd real part.
Step 430: will postpone second imaginary part and become sub-signal and estimate that imaginary part becomes sub-signal to carry out computing, and postpone to export imaginary part with generation and become sub-signal.
Step 440: postpone this output real part and become sub-signal to postpone to export real part and become sub-signal to produce one.
Step 450: become sub-signal, postpone to export real part and become sub-signal and postponed to export imaginary part to become the one at least in the sub-signal to estimate that corresponding real part becomes sub-signal to become the phase error information of sub-signal with imaginary part according to testing result, output real part.
The step of Fig. 4 and the step of Fig. 3 are similar, it is the alternate embodiment of Fig. 3, both differences are that the flow process of Fig. 4 has increased the operation and the function (that is step 410～450) of first delayer 210, filter 220, second arithmetic element 230, second delayer 240 and phase error estimation and phase error device 250 in addition, can further improve first real part and become sub-signal y
R1[n] becomes sub-signal y with first imaginary part
I1The phase difference of [n].About each element that each step shown in Figure 4 please be arranged in pairs or groups shown in Figure 2, can understand each element and how to operate, so do not repeat them here.
The step of above-mentioned flow process only for the present invention for feasible embodiment, and unrestricted restrictive condition of the present invention, and under the situation of spirit of the present invention, the method can also comprise other intermediate steps or several steps can be merged into one step, to do suitable variation.
Above-described embodiment only is used for technical characterictic of the present invention is described, is not to be used for limiting to scope of the present invention.As from the foregoing, the invention provides a kind of eqalizing cricuit and correlation technique thereof.By change modules 120 such as change module 110 such as first feedforward and second feedforwards input real part is become sub-signal x respectively
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, the signal packet that then inputs to phase-error corrector 130 contains the two dimension input, and thus, not only the effect change of phase-error corrector 130 adjustment phase differences is better, further the usefulness of lifting eqalizing cricuit.And second real part that phase-error corrector 130 is exported becomes sub-signal y
R2After [n] processing via the decision feedback fraction, the output real part that can obtain eqalizing cricuit 100 becomes sub-signal eqo
r[n].Filter 220 then can become sub-signal y according to the 3rd real part
R3[n] produces and estimates that imaginary part becomes sub-signal y
i' [n], become sub-signal y by adder with postponing second imaginary part more afterwards
Di2[n] becomes sub-signal y with the estimation imaginary part
i' [n] subtract each other, then can be postponed to export imaginary part and become sub-signal eqo
Di[n].At last, (for example testing result Sd, output real part become sub-signal eqo with above-mentioned resulting signal
r[n], postpone to export real part and become sub-signal eqo
Dr[n] and postponed to export imaginary part and become sub-signal eqo
DiAt least one in [n]) input to phase error estimation and phase error device 250 for its estimating phase error information d
r[n], d
i[n] thus, can significantly improve first real part and become sub-signal y
R1[n] becomes sub-signal y with first imaginary part
I1The phase difference of [n] is further to promote the usefulness of eqalizing cricuit.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. eqalizing cricuit includes:
One first feedforward module such as gradeizations is imported real part and is become sub-signal in order to receive one of complex input signal, and should import real part and become processing such as sub-signal grade to become sub-signal to produce one first real part;
One second feedforward module such as gradeizations is imported imaginary part and is become sub-signal in order to receive one of this complex input signal, and should import imaginary part and become processing such as sub-signal grade to become sub-signal to produce one first imaginary part; And
One phase-error corrector, be coupled to this first feedforward module such as gradeization and this second feedforward etc. and change module, be used for adjusting this first real part and become sub-signal to become sub-signal pairing one plural phase place to become sub-signal and one second imaginary part to become sub-signal with this first imaginary part to produce one second real part according to a phase error information.
2. eqalizing cricuit as claimed in claim 1, wherein change module such as this second feedforward comes this input imaginary part is become processing such as sub-signal grade according to employed joint efficiencies of change module such as this first feedforwards.
3. eqalizing cricuit as claimed in claim 1, wherein this complex input signal is a vestigial sideband signal.
4. eqalizing cricuit as claimed in claim 1, it also comprises:
One first arithmetic element is coupled to this phase-error corrector, is used for becoming sub-signal to become sub-signal to carry out computing with one the 3rd real part this second real part and becomes sub-signal to produce an output real part;
One data slicer is coupled to this first arithmetic element, is used for carrying out rigid a decision-making and becomes on the sub-signal to produce a testing result in this output real part; And
One feedback equalization module is coupled to this data slicer and this first arithmetic element, is used for carrying out first-classization and handles on this testing result and become sub-signal to produce the 3rd real part.
5. eqalizing cricuit as claimed in claim 4, wherein this first arithmetic element is an adder, is used for becoming sub-signal to deduct the 3rd real part this second real part and becomes sub-signal to become sub-signal to produce this output real part.
6. eqalizing cricuit as claimed in claim 4, it also comprises:
One first delayer is coupled to this phase-error corrector, becomes sub-signal to postpone second imaginary part and become sub-signal to produce one in order to postpone this second imaginary part;
One filter is coupled to this feedback equalization module, becomes sub-signal in order to receive the 3rd real part, and becomes sub-signal generation one to estimate that imaginary part becomes sub-signal according to the 3rd real part; And
One second arithmetic element is coupled to this filter and this first delayer, is used for that this has been postponed second imaginary part and becomes sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become sub-signal to produce one.
7. eqalizing cricuit as claimed in claim 6, wherein this second arithmetic element is an adder, is used for that this has been postponed second imaginary part and becomes sub-signal to deduct this estimation imaginary part to become sub-signal to postpone to export imaginary part and become sub-signal to produce this.
8. eqalizing cricuit as claimed in claim 6, it also comprises:
One second delayer is coupled to this first arithmetic element, becomes sub-signal to postpone to export real part and become sub-signal to produce one in order to postpone this output real part;
Wherein this has postponed to export real part and becomes sub-signal and this to postpone to export imaginary part to become sub-signal to constitute one to have postponed plural output signal.
9. eqalizing cricuit as claimed in claim 8, it also comprises a phase error estimation and phase error device, be coupled to this phase-error corrector, in order to become sub-signal according to this testing result, this output real part, this has postponed to export real part and has become sub-signal and this to postpone to export imaginary part to become in the sub-signal at least one to estimate to become sub-signal to become this phase error information of sub-signal with this input imaginary part to importing real part.
10. eqalizing cricuit as claimed in claim 1, wherein change module such as this first module such as grade and this second respectively is a joint delay line eqalizing cricuit.
11. eqalizing cricuit as claimed in claim 1, it is a decision feedback equalization device.
12. a method that is applied to an eqalizing cricuit includes:
Receive one of complex input signal input real part and become sub-signal, and should import real part and become processing such as sub-signal grade to become sub-signal to produce one first real part;
Receive one of this complex input signal input imaginary part and become sub-signal, and should import imaginary part and become processing such as sub-signal grade to become sub-signal to produce one first imaginary part; And
Adjusting this first real part according to a phase error information becomes sub-signal to become sub-signal pairing one plural phase place to become sub-signal and one second imaginary part to become sub-signal to produce one second real part with this first imaginary part.
13. method as claimed in claim 12 wherein will be imported real part and become the step of processing such as sub-signal grade to comprise:
Come this input real part is become processing such as sub-signal grade according to employed joint efficiencies of change module such as one first feedforwards; And
Become the step of processing such as sub-signal grade to comprise this input imaginary part:
Come this input imaginary part is become processing such as sub-signal grade according to employed joint efficiencies of change module such as this first feedforwards.
14. method as claimed in claim 12, wherein this complex input signal is a vestigial sideband signal.
15. method as claimed in claim 12, it also comprises:
Become sub-signal to become sub-signal to carry out computing with one the 3rd real part this second real part and become sub-signal to produce an output real part;
Carrying out rigid a decision-making becomes sub-signal to produce a testing result in this output real part; And
Execution first-classization is handled on this testing result and is become sub-signal to produce the 3rd real part.
16. method as claimed in claim 15 wherein becomes this second real part sub-signal to become sub-signal to carry out computing with the 3rd real part and becomes the step of sub-signal to comprise to produce this output real part:
Becoming sub-signal to deduct the 3rd real part this second real part becomes sub-signal to become sub-signal to produce this output real part.
17. method as claimed in claim 15, it also comprises:
Postponing this second imaginary part becomes sub-signal to postpone second imaginary part and become sub-signal to produce one;
Receive the 3rd real part and become sub-signal, and become sub-signal generation one to estimate that imaginary part becomes sub-signal according to the 3rd real part; And
This has been postponed second imaginary part becomes sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become sub-signal to produce one.
18. method as claimed in claim 17 has wherein postponed this second imaginary part and has become sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become the step of sub-signal to comprise to produce this:
This has been postponed second imaginary part becomes sub-signal to deduct this estimation imaginary part to become sub-signal to postpone to export imaginary part and become sub-signal to produce this.
19. method as claimed in claim 17, it also comprises:
Postponing this output real part becomes sub-signal to postpone to export real part and become sub-signal to produce one;
Wherein this has postponed to export real part and becomes sub-signal and this to postpone to export imaginary part to become sub-signal to constitute one to have postponed plural output signal.
20. method as claimed in claim 19, it also comprises:
According to this testing result, this output real part become sub-signal, this has postponed to export real part and has become sub-signal and this to postpone to export imaginary part to become the one at least in the sub-signal to estimate becoming sub-signal to become this phase error information of sub-signal with this imaginary part by real part.
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| CN101388879A (en) * | 2003-06-06 | 2009-03-18 | 美商内数位科技公司 | Method and system for continuously compensating for phase variations introduced into a communication signal by automatic gain control adjustments |
| CN1688146A (en) * | 2005-04-28 | 2005-10-26 | 上海微科集成电路有限公司 | Adaptive equalizing and carrier recovering method suitable for high-order QAM and circuit thereof |
| CN1852278A (en) * | 2006-04-24 | 2006-10-25 | 上海交通大学 | Phase tracking loop with NR decoding |
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