CN101740383B

CN101740383B - Method for manufacturing integrated PNP differential pair tube

Info

Publication number: CN101740383B
Application number: CN2009102486422A
Authority: CN
Inventors: ***; 罗志勇; 李书艳; 刘芝连
Original assignee: JINZHOU 777 MICROELECTRONICS CO Ltd
Current assignee: JINZHOU 777 MICROELECTRONICS CO Ltd
Priority date: 2009-12-20
Filing date: 2009-12-20
Publication date: 2011-07-20
Anticipated expiration: 2029-12-20
Also published as: CN101740383A

Abstract

The invention relates to a method for manufacturing an integrated PNP differential pair tube. The method comprises the following steps: selecting a one-side polishing P+ silicon substrate with specific resistance ranging between 0.001 and 0.008ohm-centimeter; growing an epitaxial layer serving as an N base region on the silicon substrate, wherein the specific resistance of the epitaxial layer is between 0.2 and 2.0ohm-centimeter and the thickness is between 10 and 20 mu m, and growing an oxidation layer through thermal oxidation; diffusing boron on the surface of the N base region and connecting a diffused boron agglomeration with the P+ silicon substrate to form a common P+ collecting zone, and separating the epitaxial layer into two separate base regions; diffusing the boron on the surface of the N base region to form an emitter region and controlling the effective width of the N base region between 5 and 10 mu m; diffusing phosphorus on the surface of the N base region to form a contact zone of the N+ base region; leading metal electrodes out from the surface of the contact zone of the N+ base region, the P+ collecting zone surface and the emitter region surface; and leading the metal electrodes out from the surface of the P+ collecting zone or the back side of the P+ silicon substrate. The method has the advantages that the method can effectively reduce saturation voltage drop to ensure that base-emitter reverse voltage reaches 30-100V; and devices not only have a large forward DC amplification coefficient Beta, but also have a reverse DC amplification coefficient Beta reaching 8 to 15.

Description

The manufacture method of integrated PNP differential pair tube

Technical field

The present invention relates to the manufacture method of integrated PNP differential pair tube.

Background technology

Common differential pair tube is because symmetry is good, and the frequency height is much larger than hundreds of million Hz, can be used in the input utmost point and preamplifier of instrument, instrument, lower but its base-emitter reverse breakdown voltage is worn the BVcbo scope, generally at 5～12V, and oppositely amplification coefficient is very low, levels off to zero.Therefore, common differential pair tube is not suitable for some and need stands high voltage and the application scenario of not damaging, need bigger reverse dc amplification factor β.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of manufacture method of integrated PNP differential pair tube, its base-emitter reverse voltage height, and oppositely amplification coefficient can reach 8～15, reliability height, applied range.

Technical solution of the present invention is:

A kind of manufacture method of integrated PNP differential pair tube, its special character is:

1, selects＜111〉crystal orientation single-sided polishing P+ silicon substrates, its resistivity is 0.001～0.008 ohm-cm, and as the N base, resistivity is 0.2～2.0 ohm-cm at described P+ silicon substrate growing epitaxial layers, thickness 10～20 μ m, the thermal oxide growth layer of oxide layer;

2, corrode in described N base region surface diffused with boron by masking; the diffused with boron knot is connected as public P+ collector region and forms guard ring with described P+ silicon substrate; described epitaxial loayer is separated into two independent bases, the surface impurity concentration of described P+ collector region (4～10) * 10 ¹⁹/ cm ³

3, form the emitter region by the masking corrosion in described N base region surface diffused with boron, controlling described N base effective width is 5～10 μ m, and impurity concentration is (5～10) * 10 ¹⁹/ cm ³

4, to described N base region surface masking corrosion, diffusion phosphorus forms contact zone, N+ base, and diffusion temperature is 1000～1100 ℃ again, and impurity concentration is (10～50) * 10 ¹⁹/ cm ³

5, draw metal electrode or draw metal electrode on contact zone, described N+ base, P+ collector region and surface, emitter region on surface, contact zone, described N+ base, the P+ silicon substrate back side and surface, emitter region.

The manufacture method of above-mentioned integrated PNP differential pair tube when drawing metal electrode at the described P+ silicon substrate back side, is drawn P+ silicon substrate back side abrasive disc, steaming titanium nickeline earlier again.

Advantage of the present invention is: component structure is with common triode chip, but owing to introduce the P+ substrate, can effectively reduce saturation voltage drop on the one hand, its base-emitter reverse voltage is very high, can reach 30～100V, much larger than common triode base-emitter-base bandgap grading reverse breakdown voltage.Except having big forward dc magnificationfactor,, also improved reverse dc amplification factor β greatly on the other hand, made reverse dc amplification factor β can reach 8～15 by selecting low-resistivity silicon substrate, control base effective width and N base resistance rate.Circuit is had preferably use, especially in the circuit of anti-high voltages such as modulation, copped wave, have high reliability.

Description of drawings

Fig. 1 is the differential pair tube schematic surface that the present invention makes;

Fig. 2 is the A-A cutaway view (corresponding embodiment 1～embodiment 3) of Fig. 1;

Fig. 3 is the A-A cutaway view (corresponding embodiment 4) of Fig. 1.

Among the figure: P+ silicon substrate 1, N base 2, oxide layer 3, P+ collector region 4, emitter region 5, contact zone, N+ base 6, metal electrode 7, metal electrode 8, metal electrode 9, passivation layer 10, metal electrode 11, base effective width W.

Embodiment

Embodiment 1

1, as depicted in figs. 1 and 2, select crystal orientation＜111〉single-sided polishing P+ silicon substrate 1, its resistivity is 0.001 ohm-cm, at silicon substrate 1 growing epitaxial layers as N base 2, resistivity is 0.2 ohm-cm, thickness 20 μ m, thermal oxide growth layer of oxide layer 3;

2, corrode in the N base 2 diffusion into the surface boron by masking; Kuo San temperature is 1160 ℃ again; the diffused with boron knot is connected as public P+ collector region 4 and forms guard ring with P+ silicon substrate 1, epitaxial loayer is separated into two independent bases, the surface impurity concentration 10 of P+ collector region 4 ²⁰/ cm ³

3,2 diffusion into the surface boron form discrete emitter region 5 in the N base by the masking corrosion, and diffusion temperature is 1000 ℃ again, and control N base effective width W is 10 μ m, and impurity concentration is 5 * 10 ¹⁹/ cm ³

4, to the 2 photomask surface mask etches of N base, diffusion phosphorus forms contact zone, N+ base 6, and diffusion temperature is 1000 ℃ again, and impurity concentration is 50 * 10 ¹⁹/ cm ³

5, in contact zone, N+ base 6, emitter region 5 and P+ collector region 4 surface evaporation metals, draw

metal electrode

7,8,9 (being base stage b, emitter e and collector electrode c) after etching metal, the passivation (forming passivation layer 10).

Embodiment 2

1, as depicted in figs. 1 and 2, select＜111〉crystal orientation single-sided polishing P+ silicon substrates 1, its resistivity is 0.008 ohm-cm, at silicon substrate 1 growing epitaxial layers as N base 2, resistivity is 2.0 ohm-cms, thickness 10 μ m, thermal oxide growth layer of oxide layer 3;

2, corrode in the N base 2 diffusion into the surface boron by masking; Kuo San temperature is 1200 ℃ again; the diffused with boron knot is connected as public P+ collector region 4 and forms guard ring with P+ silicon substrate 1, epitaxial loayer is separated into two independent bases, the surface impurity concentration 4 * 10 of P+ collector region 4 ¹⁹/ cm ³

3,3 diffusion into the surface boron form emitter region 5 in the N base by the masking corrosion, and diffusion temperature is 1160 ℃ again, and control N base effective width W is 5 μ m, and impurity concentration is 10 * 10 ¹⁹/ cm ³

4, to the 2 photomask surface mask etches of N base, diffusion phosphorus forms contact zone, N+ base 6, and diffusion temperature is 1100 ℃ again, and impurity concentration is 10 * 10 ¹⁹/ cm ³

metal electrode

Embodiment 3

1, as depicted in figs. 1 and 2, select＜111〉crystal orientation single-sided polishing P+ silicon substrates 1, its resistivity is 0.005 ohm-cm, at silicon substrate 1 growing epitaxial layers as N base 2, resistivity is 1.0 ohm-cms, thickness 15 μ m, thermal oxide growth layer of oxide layer 3;

2, corrode in the N base 2 diffusion into the surface boron by masking; Kuo San temperature is 1190 ℃ again; the diffused with boron knot is connected as public P+ collector region 4 and forms guard ring with P+ silicon substrate 1, epitaxial loayer is separated into two independent bases, the surface impurity concentration 6 * 10 of P+ collector region 4 ¹⁹/ cm ³

3,3 diffusion into the surface boron form emitter region 5 in the N base by the masking corrosion, and diffusion temperature is 1030 ℃ again, and control N base effective width W is 7 μ m, and impurity concentration is 8 * 10 ¹⁹/ cm ³

4, to the 2 photomask surface mask etches of N base, diffusion phosphorus forms contact zone, N+ base 6, and diffusion temperature is 1050 ℃ again, and impurity concentration is 30 * 10 ¹⁹/ cm ³

metal electrode

Embodiment 4

As shown in figures 1 and 3, the first step～4th step is as embodiment 1～embodiment 3, in contact zone, N+ base 6, emitter region 5 surface evaporation metals, draws metal electrode 7,8 (being base stage b, emitter e) after etching metal, the passivation (formation passivation layer 10); With P+ silicon substrate back side abrasive disc, steam the titanium nickeline and draw metal electrode 11 (being collector electrode c).

Claims

1. the manufacture method of an integrated PNP differential pair tube is characterized in that:

1.1, select＜111〉crystal orientation single-sided polishing P+ silicon substrates, its resistivity is 0.001～0.008 ohm-cm, and as the N base, resistivity is the 0.2-2.0 ohm-cm at described P+ silicon substrate growing epitaxial layers, thickness 10～20 μ m, the thermal oxide growth layer of oxide layer;

1.2, by masking corrosion in described N base region surface diffused with boron; the diffused with boron knot is connected as public P+ collector region and forms guard ring with described P+ silicon substrate; epitaxial loayer is separated into two independent bases, the surface impurity concentration of described P+ collector region (4～10) * 10 ¹⁹/ cm ³

1.3, form the emitter region by masking corrosion in described N base region surface diffused with boron, controlling described N base effective width is 5～10 μ m, impurity concentration is (5～10) * 10 ¹⁹/ cm ³

1.4, to the corrosion of described N base region surface masking, diffusion phosphorus forms contact zone, N+ base, impurity concentration is (10～50) * 10 ¹⁹/ cm ³

1.5, draw metal electrode on contact zone, described N+ base, P+ collector region and surface, emitter region or draw metal electrode on surface, contact zone, described N+ base, the P+ silicon substrate back side and surface, emitter region.

2. the manufacture method of integrated PNP differential pair tube according to claim 1 is characterized in that: when drawing metal electrode at the described P+ silicon substrate back side, earlier described P+ silicon substrate back side abrasive disc, steaming titanium nickeline are drawn again.