CN101736375B - Plating method - Google Patents
Plating method Download PDFInfo
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- CN101736375B CN101736375B CN2008102271765A CN200810227176A CN101736375B CN 101736375 B CN101736375 B CN 101736375B CN 2008102271765 A CN2008102271765 A CN 2008102271765A CN 200810227176 A CN200810227176 A CN 200810227176A CN 101736375 B CN101736375 B CN 101736375B
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Abstract
The invention relates to a plating method comprising the following steps of: determining the thickness of a plating layer, and providing a base, wherein the surface of the base is provided with a seed crystal layer; and sequentially executing an operation of forming at least two plating sublayers on the seed crystal layer and an annealing operation after the operation of forming the plating sublayers, wherein the thickness of each plating sublayer is equal to that of the plating layer. The invention has fewer holes in the formed plating layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of electro-plating method.
Background technology
In the traditional technology, use electroplating technology usually and form the interconnecting metal layer (like copper) between device and external circuit.The step of utilizing traditional technology to carry out electroplating operations comprises step 11: as shown in Figure 1, confirm electrolytic coating thickness and substrate 10 be provided that said substrate 10 surfaces are formed with crystal seed layer 20; Step 12: as shown in Figure 2, on said crystal seed layer 20, form electrolytic coating 30.
For improving the effect of subsequent chemistry mechanical mill (CMP) and wafer acceptability test (WAT) and reliability testing, usually, after forming electrolytic coating 30, need to carry out annealing operation.As an example, the processing condition of carrying out said annealing operation comprise: annealing temperature is 200 degrees centigrade, and the annealing time length is 90 seconds.
Yet actual production finds, like Fig. 3, shown in Figure 4, experience above-mentioned annealing operation after, in the interconnecting metal layer (electrolytic coating 30) that forms, be prone to exist hole (void) 32, for thicker (as, thickness is above 3 microns) interconnecting metal layer, especially serious.How to reduce the generation of described hole, become the subject matter that those skilled in the art endeavour to solve.
For reducing the generation of described hole; Many trials have been carried out in the industry; Like the publication number of announcing on February 7th, 2007 is the method for manufacture that internal connection-wire structure in a kind of semiconductor element is provided in the one Chinese patent application of " CN1909206A "; Through in internal connection-wire structure, having one or more stress release layer, retract hole to offset the caused stress of electro-conductive material and to help to prevent or reduce to produce.And; The publication number of announcing on January 30th, 2008 is for providing a kind of method that can avoid copper dual-damascene structure when flatening process, to produce defective in the one Chinese patent application of " CN101114607A "; Through after accomplishing the copper conductor layer deposition; Utilize a plasma body that copper conductor layer is carried out surperficial pre-treatment; Carry out annealing process again, making the copper conductor layer stress tendency behind annealing process is stress under compression, causes at the issuable anomalad of flatening process because of the tension stress of self to avoid common copper conductor layer.
But, when using the generation of aforesaid method minimizing described hole, all need in original technology, add new technology, particularly,, need grope the formation technology of said stress release layer for the former, and, the degree of integration of said formation technology and current technology; And, need grope the concrete operations of said surperficial pre-treatment for the latter, all need drop into huge R&D costs.
Summary of the invention
The invention provides a kind of electro-plating method, can in the electrolytic coating that forms, have less hole.
A kind of electro-plating method provided by the invention comprises:
Confirm electrolytic coating thickness and substrate is provided, said substrate surface is formed with crystal seed layer;
Order carry out to form the stratified operation of two-layer at least plating and places the annealing operation that respectively forms after the stratified operation of said plating on said crystal seed layer, the stratified thickness of each said plating and equal said electrolytic coating thickness.
Compared with prior art, technique scheme has the following advantages:
The electro-plating method that technique scheme provides; Be decomposed into the stratified step of the two-layer at least said plating of formation through the step that will form said electrolytic coating; And after forming the stratified operation of said plating, carry out annealing operation; The stress that can make the said annealing operation of experience and in each said plating layering, increase is discharged by substep in forming the stratified step of each said plating interval, can make said electrolytic coating have less hole through the stress of the said electrolytic coating of minimizing; In addition; Through reducing the continuous electrolytic coating that forms (promptly; Each electroplates layering) thickness, can be after via annealing operation, the hole that said plating layering has is easier to arrive respectively electroplates the layering surface; Thereby make described hole that bigger possibly being filled by follow-up plated layered materials arranged, with the generation of further minimizing described hole.
Description of drawings
Fig. 1-Fig. 2 is the structural representation of electroplating operations flow process in the explanation prior art;
Fig. 3 is for existing the structural representation of the electrolytic coating of hole in the explanation prior art;
Fig. 4 is for existing the structure picture of the electrolytic coating of hole in the explanation prior art;
Fig. 5 is the schematic flow sheet of the execution electroplating operations of explanation first embodiment of the invention;
Fig. 6-Fig. 7 is the structural representation of the electroplating operations flow process of explanation first embodiment of the invention;
Stress improved the effect comparison synoptic diagram after Fig. 8 used the preferred embodiment of the present invention and uses prior art for explanation;
Fig. 9 uses the structure picture of the electrolytic coating of preferred embodiment of the present invention acquisition for explanation;
Figure 10 is an electrical effect comparison synoptic diagram after explanation is used the preferred embodiment of the present invention and used prior art.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that broad to those skilled in the art, and not as limitation of the present invention.
For clear, whole characteristics of practical embodiments are not described.In following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize pioneer's specific objective.In addition, will be understood that this development possibly be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer based on description and claims advantage of the present invention and characteristic.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 5, as the first embodiment of the present invention, the step of carrying out electroplating operations comprises step 501: confirm electrolytic coating thickness and substrate is provided, said substrate surface is formed with crystal seed layer; Step 502: order carry out to form the stratified operation of two-layer at least plating and places the annealing operation that respectively forms after the stratified operation of said plating on said crystal seed layer, the stratified thickness of each said plating and equal said electrolytic coating thickness.
In presents, said electrolytic coating thickness mean for the electrolytic coating thickness a that obtains to satisfy the product design requirement in actual production preformed electrolytic coating thickness b (b is greater than a).Particularly, if according to design requirements, a certain thickness of plating layer in the product should be 2 microns; So; In the actual processing procedure, be 2 microns electrolytic coating, need be pre-formed the electrolytic coating of thickness greater than 2 microns (as 3 microns) for obtaining this thickness; Remove unnecessary electrolytic coating through subsequent steps such as grindings again, to obtain to satisfy the electrolytic coating of product design requirement.At this moment, said electrolytic coating thickness refers to above-mentioned electrolytic coating greater than 2 microns (as 3 microns).
On the substrate definition device active region and accomplish shallow trench isolation from, then form grid structure and source region and drain region after; And then to deposit first interlayer dielectric layer (be before-metal medium layer; PMD); Continuation forms the first layer through hole (via) and groove (trench) in said first interlayer dielectric layer, behind the crystal seed layer of diapire that forms said through hole of covering and groove and sidewall, can form substrate 100.Can expand ground, behind deposition N-1 interlayer dielectric layer, continue to form N-1 layer through hole and groove, behind the crystal seed layer of diapire that forms said through hole of covering and groove and sidewall, still can form substrate 100.Obviously, the number N of said interlayer dielectric layer can be any natural number, and as 1,3,5,7 or 9 etc., the concrete number of said interlayer dielectric layer is confirmed according to product requirement.Said before-metal medium layer covers said grid structure and source region and drain region and fills up the linear slit that is positioned between said grid structure; Said grid structure comprises the side wall and the gate oxide of grid, all around gate.Said grid structure also can comprise the blocking layer that covers said grid and side wall.Said substrate comprises but is not limited to comprise the silicon materials of element, and for example the silicon of monocrystalline, polycrystalline or non-crystal structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).It is as shown in Figure 6 that the surface that forms has the said substrate 100 of said crystal seed layer 120.
In the step that forms said through hole and groove with form between the step of said crystal seed layer, also comprise: form and cover said through hole and the bottom of groove and the adhesive linkage of sidewall.Said adhesive linkage is in order to the bottom that strengthens said crystal seed layer and said through hole and groove and the degree of engagement of sidewall, to reduce owing to the increase that engages the bad contact resistance that causes of effect.Said adhesive linkage can comprise the rhythmo structure of TaN/Ta or TiN/Ti.Said adhesive linkage chemical vapor deposition method capable of using obtains.
Said crystal seed layer physical vapor deposition (PVD) technology capable of using forms.When the interconnection material of filling said through hole and groove was metallic copper, said crystal seed layer was a copper.In the practice, said crystal seed layer is in order to being connected to external power as electronegative flat board or cathodic electricity when forming electrolytic coating, is reduced and the metallic copper atom that forms to carry by the metal copper ion in the electroplating solution.
But actual production is found, is prone to form hole in the electrolytic coating that on above-mentioned crystal seed layer, forms.
Contriver of the present invention thinks after analyzing that the reason that forms described hole is: in the conventional art, after forming said crystal seed layer, form the electrolytic coating with above-mentioned electrolytic coating thickness continuously; Here, said meaning continuously after formation has the electrolytic coating of above-mentioned electrolytic coating thickness just carried out annealing operation, is proceed step by step even form the operation of said electrolytic coating, as, in the process that forms said electrolytic coating, electric current increases gradually; So operation is prone to cause: since carry out the electrolytic coating of said annealing operation too thick (as, above 1 micron), and after experiencing said annealing operation; Crystal grain in said crystal seed layer and the electrolytic coating all will be grown up, and cause stress to increase (after usually, stress increases; To cause substrate deformation, that is, around the substrate with the center not in one plane); Excessive stress will cause intercrystalline space to increase, and then cause the generation of described hole.
Thus, contriver of the present invention proposes, and reduces to carry out the thickness of plating layer of said annealing operation, becomes the direction that reduces the generation of electroplating the hole phenomenon.
Particularly; As shown in Figure 7; Be decomposed into the step of the two-layer at least said plating layering of formation (being merely shown in Fig. 7 the example that said electrolytic coating 140 is decomposed into two-layer plating layering 142 and at 144 o'clock) through the step that will form said electrolytic coating; And after forming the stratified operation of said plating, carry out annealing operation; The stress that can make the said annealing operation of experience and in each said plating layering, increase is discharged by substep in forming the stratified step of each said plating interval, can make said electrolytic coating have less hole through the stress of the said electrolytic coating of minimizing.
In the practice, after confirming required electrolytic coating thickness, according to arts demand; With said electrolytic coating thickness be decomposed at least two electroplate stratified thickness with, order forms each said plating layering, after forming each said plating layering, carries out annealing operation respectively; Because under identical annealing conditions; The STRESS VARIATION of electrolytic coating is relevant with its thickness, and the thickness of plating layer of carrying out arbitrary said annealing operation diminishes, and the stratified stress of plating of the said annealing operation of experience is reduced; And then, the stress of electrolytic coating is reduced.
In addition, because in annealing process, described hole is in dynamically; And the characteristic with the lower interface of trend energy, but process is slow, if thickness of plating layer is blocked up; Then in annealing process; Described hole is not enough to arrive the surface of said electrolytic coating, with the inside that only rests on said electrolytic coating, causes defective; If but formation is to electroplate layering; Its thinner thickness then can be after via annealing operation, and described hole is easier to arrive respectively electroplates the layering surface; Thereby make described hole that bigger possibly being filled by follow-up plated layered materials arranged, with the generation of further minimizing described hole.
Can adopt any traditional technology when carrying out annealing operation, the processing condition as in the current technology comprise: annealing temperature is 200 degrees centigrade, and the annealing time length is 90 seconds.
In addition, be to repair established plating layering owing to carry out the benefit of said annealing operation, the increase of said annealing operation time length is beneficial to the improvement of above-mentioned finishing effect; But owing to carry out the increase of the plating layering internal stress that said annealing operation also will cause forming, therefore, usually, the time length of said annealing operation can be not oversize, and particularly, annealing temperature is 200 degrees centigrade, and the annealing time length can be 90 seconds; Yet, as previously mentioned, in the technical scheme provided by the invention; Because the stratified thickness of plating of the arbitrary annealing operation of experience is less, it is relevant with its thickness again that each electroplates stratified STRESS VARIATION, makes the increased value of the plating layering internal stress that the said annealing operation of execution causes reduce; In other words; Experience arbitrary annealing operation respectively to electroplate stratified thickness less, can after prolonging the annealing time length, still can obtain the electrolytic coating that layer internal stress satisfies product requirement.
Thus, if the processing condition in the current technology, comprising: annealing temperature is 200 degrees centigrade, and the annealing time length is 90 seconds; Then as other embodiment of the present invention, form arbitrary plating layering after, when carrying out said annealing operation, processing parameter comprises: TR is 150 degrees centigrade-250 degrees centigrade, as 150 degrees centigrade, 200 degrees centigrade or 250 degrees centigrade; Time length was 120 seconds-200 seconds, as 120 seconds, 150 seconds or 200 seconds.Through prolonging the annealing time length, can further improve the performance that forms electrolytic coating, like smoothness, density etc.
In addition; The side washing operation (edge bevel remove, EBR is in order to remove the electrolytic coating material of said basal edge) that comprises in the traditional technology is in technical scheme provided by the invention; Be placed in and form the said plating layering of last one deck and place between the annealing operation thereafter; Need not the side washing operation all to be set forming arbitrary said plating layering and place between the annealing operation thereafter, can be in reducing electrolytic coating after the hole, as far as possible little to the change of traditional technology.
What need explanation is that preferably, each said plating lift height equates; The stratified performance of each said plating of formation is reached unanimity, then, when the experience annealing operation, each improvement effect of electroplating the layering inside aperture is reached unanimity.At this moment, each said plated layered materials is identical.In the presents, term " equates ", " identical " all represented can be left in the basket under comparison condition by difference between the two relatively, perhaps, because the variation of the caused processing parameter of said difference is allowed by the processing procedure requirement.
As an example, said electrolytic coating comprises two when electroplating layerings, and the thickness ratio between two said plating layerings can be 2/3-3/2.This be because, if two stratified thickness of said plating have big difference,,, weakened with the effect of improving stress through the thickness of plating layer that reduces to experience annealing operation by aforementioned analysis for thicker plating layering, and then, will weaken the effect that hole improves.
As an example, if the said electrolytic coating thickness of confirming is 1.55 microns, then two stratified thickness of said plating can be respectively 0.8 micron and 0.75 micron.
Be the improve effect of checking technique scheme to described hole, contriver of the present invention is corresponding to be detected with the wafer behind the execution electroplating operations of above-mentioned preferred version and the acquisition of application traditional scheme:
The processing condition of using traditional scheme execution electroplating operations comprise: the electric current of using 4.5 amperes was electroplated 5.5 seconds; Then, the electric current of using 6.75 amperes was electroplated 45 seconds; Using 40.5 amperes electric current again electroplated 210 seconds; Then, carry out the side washing operation; Under 200 degrees centigrade condition, carry out 90 seconds annealing operations again;
The processing condition of using above-mentioned preferred version execution electroplating operations comprise: at first, form first and electroplate layering, particularly, use 4.5 amperes electric current and electroplated 5.5 seconds; Then, the electric current of using 6.75 amperes was electroplated 45 seconds; Using 40.5 amperes electric current again electroplated 84 seconds; Then, under 200 degrees centigrade condition, carry out 150 seconds annealing operations; Subsequently, form second and electroplate layering, particularly, use 4.5 amperes electric current and electroplated 5.5 seconds; Then, the electric current of using 6.75 amperes was electroplated 45 seconds; Using 40.5 amperes electric current again electroplated 126 seconds; Then, carry out the side washing operation; Under 200 degrees centigrade condition, carry out 150 seconds annealing operations again.(said " first " and " second " table order at this moment)
Because; The variation of said electrolytic coating internal stress will cause carrying the substrate generation deformation of said electrolytic coating; Therefore; The deformation of substrate after contriver of the present invention uses above-mentioned preferred version respectively through detection and uses traditional scheme execution electroplating operations with the variation of said electrolytic coating internal stress after the checking application technical scheme provided by the invention, reaches the improvement effect of electrolytic coating inside aperture defective.
As shown in Figure 8, the result shows, use above-mentioned preferred version after, can make the deformation of wafer reduce to about 200 microns by about 500 microns, it is remarkable to improve effect.The structure picture of using the electrolytic coating that above-mentioned preferred version obtains is as shown in Figure 9.
In addition, (it is qualified to have detected) wafer that contriver's correspondence of the present invention obtains when carrying out electroplating operations with above-mentioned preferred version with the application traditional scheme has carried out wafer acceptability test (WAT), has specifically tested the contact resistance (Rc) of the through hole after filling; Shown in figure 10; The result shows, compares when traditional scheme is carried out electroplating operations with using, after using above-mentioned preferred version and carrying out electroplating operations; The variation of the contact resistance of the through hole after the filling can be left in the basket; That is, when the application technique scheme is improved described hole, can not produce detrimentally affect to the electric property of wafer.
What need stress is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is confirmed based on product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe through the embodiment at this, the applicant does not hope by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, these details be can depart from and the spirit and the scope of the total inventive concept of applicant do not broken away from.
Claims (6)
1. an electro-plating method is characterized in that, comprising:
Confirm electrolytic coating thickness and substrate is provided, said substrate surface is formed with crystal seed layer;
Order carry out to form the stratified operation of two-layer at least plating and places the annealing operation that respectively forms after the stratified operation of said plating on said crystal seed layer, the stratified thickness of each said plating and equal said electrolytic coating thickness; Wherein, the processing parameter of carrying out said annealing operation comprises: TR is 150 degrees centigrade-250 degrees centigrade; Time length is 120 seconds-200 seconds; Forming the said plating layering of last one deck and placing between the annealing operation thereafter, also comprise, carry out the side washing operation, to remove the electrolytic coating material of said basal edge.
2. electro-plating method according to claim 1 is characterized in that: each said plated layered materials is identical.
3. electro-plating method according to claim 2 is characterized in that: said electrolytic coating material is a copper.
4. electro-plating method according to claim 1 is characterized in that: each said plating lift height equates.
5. electro-plating method according to claim 1 is characterized in that: said electrolytic coating comprises two when electroplating layerings, and the thickness between two said plating layerings is than being 2/3-3/2.
6. electro-plating method according to claim 1 is characterized in that: said electrolytic coating thickness is greater than 1 micron.
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| CN2008102271765A CN101736375B (en) | 2008-11-24 | 2008-11-24 | Plating method |
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| CN2008102271765A CN101736375B (en) | 2008-11-24 | 2008-11-24 | Plating method |
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| CN101736375B true CN101736375B (en) | 2012-05-23 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1449015A (en) * | 2002-04-01 | 2003-10-15 | 海力士半导体有限公司 | Method for forming metal interconnecting layers in semiconductor device |
| CN1590597A (en) * | 2003-08-29 | 2005-03-09 | 中芯国际集成电路制造(上海)有限公司 | Copper electroplating film method |
| CN1790663A (en) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | Semiconductor component and method for manufacture copper lead |
| US7300866B2 (en) * | 2004-07-08 | 2007-11-27 | Dongbu Electronics Co., Ltd. | Method for fabricating metal line in a semiconductor |
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2008
- 2008-11-24 CN CN2008102271765A patent/CN101736375B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1449015A (en) * | 2002-04-01 | 2003-10-15 | 海力士半导体有限公司 | Method for forming metal interconnecting layers in semiconductor device |
| CN1590597A (en) * | 2003-08-29 | 2005-03-09 | 中芯国际集成电路制造(上海)有限公司 | Copper electroplating film method |
| US7300866B2 (en) * | 2004-07-08 | 2007-11-27 | Dongbu Electronics Co., Ltd. | Method for fabricating metal line in a semiconductor |
| CN1790663A (en) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | Semiconductor component and method for manufacture copper lead |
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