CN101729485B - Single-carrier and ultra-wideband sending method and device - Google Patents

Abstract

The invention discloses single-carrier and ultra-wideband sending method and device. A physical layer data frame structure used in the method is characterized in that a leader sequence comprises a trapping/channel estimation sequence, a frame start delimiter and a block length; a training sequence field is used for coefficient training of a self-adapting filter; the frame head comprises a physical frame head and an MAC frame head; a data field bears metadata; after scrambled, encoded and interlaced, bits of the frame heads and the data are named as information bits; the information bits are divided into N blocks; the value of each frame N can be different, and then the frames of different lengths can be transmitted. A tracking sequence is inserted into the front of each block or behind each block to perform timing tracking. The invention enhances the dissociative diffusion signal-to-noise ratio so that the trapping probability is enhanced; the channel estimation accuracy is increased, the receiving and converting time is shortened, and thus the invention can meet high-speed requirement and is convenient for processing by blocks; and the data auxiliary timing tracking function can be performed.

Description

Single-carrier ultra-wideband transmitting method and device

Technical Field

The invention relates to the technical field of wireless communication, in particular to a single carrier ultra-wideband transmitting method and a single carrier ultra-wideband transmitting device.

Background

Ultra-wideband is a communication technology with an absolute bandwidth greater than 500MHz or a relative bandwidth greater than 20%, which can provide communication rates above the 100Mbps rate. Ultra-wideband has attracted much attention in the industry due to its superior characteristics of high capacity and low power consumption. Ultra-wideband technology will find wide application in various short-range Wireless networks, such as WPAN (Wireless Personal Area Network), WBAN (Wireless Body Area Network), Ad-hoc networks. In addition, the ultra wideband technology is also applied to home multimedia interconnection, such as Wireless hd (high definition) and WHDI (Wireless home digital Interface). In addition, in high-speed short-range wireless interfaces such as wireless USB and wireless 1394, attention is focused on ultra-wideband technology.

There are two major types of currently accepted Ultra-Wideband technologies, the first is direct Sequence-Ultra Wideband (DS-UWB) [ please refer to r.fisher, r.kohno, m.mclaughlin, m.welbough, "DS-UWB physical layer transmission to 802.15 task group 3 a", IEEE P802.15-04/0137r4, jan.2005 ], and the second is Multi-Band Orthogonal frequency division Multiplexing (MB-OFDM) [ please refer to Standard ECMA-368(ISO/IEC 26907), "High Rate Ultra Wideband PHY and MAC Standard", international (ISO/IEC 2005), and dc.

DS-UWB is a narrow pulse based ultra-wideband technology that uses very high speed chip sequences (above 1.3Gcps) to meet instantaneous bandwidth requirements. The physical layer frame structure of DS-UWB is shown in FIG. 1. The Acquisition Sequence (Acquisition Sequence) is a repeated Acquisition code Sequence used for spread spectrum Acquisition, and the SFD is a 32-bit start of frame Delimiter (StartFrame limiter). DATA Field is used to carry some important DATA, Training Sequence (Training Sequence) is used to carry Training Sequence, and the Header (Header) includes a physical Header (PHY Header) and a MAC Header (MAC Header). Data carries payload Data (metadata). The Header transmission rate is lower than the Data (Data) transmission rate, so that better transmission performance can be obtained. The other parts except the Data section are 24 chips/symbol.

MB-OFDM is an OFDM-based ultra-wideband technique. The frequency band of 7.5GHz, which is the total frequency band of 3.1 GHz-10.6 GHz, is divided into 14 frequency bands, and each frequency band is 528 MHz. OFDM modulation of 128 subcarriers is performed on each frequency band. The physical layer frame structure of MB-OFDM is shown in FIG. 2. A Packet/frame synchronization Sequence (Packet/frame synchronization Sequence) is used for initial synchronization of OFDM and frame synchronization, and a Channel Estimation Sequence (Channel Estimation Sequence) is used for Channel Estimation. The frame Header (Header) includes a physical frame Header (PHYHeader) and a MAC frame Header (MAC Header). Data carries payload Data. The Header transmission rate is lower than the Data transmission rate, so that better transmission performance can be obtained.

The DS-UWB instantaneous bandwidth exceeds 1.3GHz, which means that the receiver requires an ADC (Analog to Digital Converter) with a very high sampling rate, e.g., up to about 6 GSPS. Such a high speed ADC would make the receiver very expensive and the power consumption would be significant, and would not be able to meet the low cost and low power consumption requirements well. The MB-OFDM uses OFDM modulation, and the inherent PAR (Peak to Average Ratio) disadvantage will make the rf module face a larger pressure. In addition, the OFDM technique has a high requirement on the accuracy of the ADC and is sensitive to carrier frequency offset. It is these drawbacks that have not led to the widespread use of both DS-UWB and MB-OFDM.

Disclosure of Invention

Aiming at the defects and shortcomings in the prior art, the invention aims to provide a technical scheme which is suitable for a single-carrier ultra-wideband system and is used for transmitting data by utilizing a physical layer data frame structure, wherein the physical layer data frame structure can improve the capture probability, increase the channel estimation accuracy, shorten the transceiving conversion time and realize the data-assisted timing tracking effect.

In order to achieve the above object, the invention provides a single carrier ultra-wideband transmission method, comprising the steps of:

s1, generating a preamble symbol: before sending a data frame, setting block number, and generating a leader sequence symbol according to the block number: $[{\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="1"\; label="B\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="2"\; label="C\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}],$ at the moment, the state machine is in an idle state; wherein, B₁，B₂，...，B_N1、C₁，C₂，...，C_N2、D₁，D₂，...，D_N3Acquisition/channel estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/Channel Estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or 0, j ═ 1, 2, …, N₂，k＝1，2，…，N₃；

S2, transmitting the preamble chip sequence: when starting to send data frame, the state machine changes from idle state to sending leading state; in the preamble sending state, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a preamble chip sequence according to the preamble sequence symbol generated in the step S1, and controls the multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence; enabling a training sequence generator to generate a training sequence by a state machine in a plurality of clock cycles before the preamble chip sequence is sent out, and inputting the training sequence into an asynchronous first-in first-out structure, so that when the preamble chip sequence is sent out, the training sequence data are already stored in the asynchronous first-in first-out structure, and when the preamble chip sequence is sent out, the state machine is switched to a state of sending the training sequence;

s3, outputting training sequence chips: when the training sequence state is sent, the state machine enables the short spread spectrum sequence generator and the short code spread spectrum modulation module, reads the training sequence from the asynchronous first-in first-out structure and carries out short code spread spectrum to generate an information chip sequence, and simultaneously, the state machine controls the multi-path selector to select an information chip sequence branch to output the training sequence chip; wherein, the training sequence is a field of a data frame;

s4, generating payload bit data: the method comprises the steps that a state machine enables scrambling, coding and interweaving processing of a frame Header and Data to generate load bit Data after a period of time before a training sequence is sent out, the obtained load bit Data are input into an asynchronous first-in first-out structure, so that when the training sequence is sent out, the processed load bit Data are stored in the asynchronous first-in first-out structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into N block blocks, the block is a field of a data frame, and a Tracking Sequence field is inserted before or after each block; n is a positive integer;

s5, outputting payload bit data: in a load sending state, a state machine enables a short spread spectrum sequence generator and a short code spread spectrum modulation module, load bit data are read from an asynchronous first-in first-out structure and short code spread spectrum is carried out to generate an information chip sequence, and meanwhile, the state machine controls a multi-path selector to select an information chip sequence branch to output the load bit data; after the information chip of one block is sent, the state is switched to a tracking sequence sending state;

s6, outputting tracking chip sequence: when the tracking sequence state is sent, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a tracking sequence according to a tracking symbol, and controls the multiplexer to select a tracking chip sequence branch to output the tracking chip sequence; wherein the tracking symbol is

E₁，E₂，...，E_N1Tracking Sequence, N, for a data frame₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄；

S7, repeating the steps S5 and S6, and sending the next block: and ending the sending of the data frame until the preset block number is sent, and returning the state machine to an idle state.

And the number N of the block of each data frame is different in value.

The invention also provides a single carrier ultra-wideband transmitting device, which comprises:

a leading sequence symbol generating module, configured to set block number before sending the data frame, and generate a leading sequence symbol according to the block number: $[{\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="1"\; label="B\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="2"\; label="C\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}],$ at the moment, the state machine is in an idle state; wherein, B₁，B₂，...，B_N1、C₁，C₂，...，C_N2、D₁，D₂，...，D_N3Acquisition/Channel Estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/channel estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or 0, j ═ 1, 2, …, N₂，k＝1，2，…，N₃；

A preamble chip sequence sending module, configured to switch a state machine from an idle state to a sending preamble state when starting sending a data frame; in the preamble sending state, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a preamble chip sequence according to the preamble sequence symbol generated in the step S1, and controls the multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence; enabling a training sequence generator to generate a training sequence by a state machine in a plurality of clock cycles before the preamble chip sequence is sent out, and inputting the training sequence into an asynchronous first-in first-out structure, so that when the preamble chip sequence is sent out, the training sequence data are already stored in the asynchronous first-in first-out structure, and when the preamble chip sequence is sent out, the state machine is switched to a state of sending the training sequence;

a training sequence chip output module, which is used for reading the training sequence from the asynchronous first-in first-out structure and carrying out short code spread spectrum to generate an information chip sequence by using a state machine to enable a short spread spectrum sequence generator and a short code spread spectrum modulation module when the training sequence is sent, and meanwhile, the state machine controls a multi-path selector to select an information chip sequence branch to carry out training sequence chip output; wherein, the training sequence is a field of a data frame;

a load bit Data generation module, which is used for scrambling, coding and interweaving a frame Header and Data by a state machine for a period of time before the training sequence is sent out, generating load bit Data, and inputting the obtained load bit Data into an asynchronous first-in first-out structure, so that when the training sequence is sent out, the processed load bit Data is stored in the asynchronous first-in first-out structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into a plurality of block blocks, each block is a field of a data frame, and a Tracking Sequence field is inserted before or after each block;

the load bit data output module is used for enabling the short spread spectrum sequence generator and the short code spread spectrum modulation module by the state machine in a load sending state, reading the load bit data from the asynchronous first-in first-out structure and carrying out short code spread spectrum to generate an information chip sequence, and meanwhile, the state machine controls the multi-path selector to select an information chip sequence branch to carry out load bit data output; after the information chip of one block is sent, the state is switched to a tracking sequence sending state;

a tracking chip sequence output module, which is used for enabling the long spread spectrum sequence generator and the long code spread spectrum modulation module by the state machine when the tracking sequence state is sent, generating the tracking sequence according to the tracking symbol, and simultaneously controlling the multiplexer to select a tracking chip sequence branch by the state machine to output the tracking chip sequence; wherein the tracking symbol is

E₁，E₂，...，E_N1Tracking Sequence, N, for a data frame₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄。

The technical scheme of the invention has the following advantages:

1) the auxiliary long spread spectrum sequence is adopted to carry out spread spectrum modulation through the leader sequence field, and the despreading signal-to-noise ratio is improved, so that the capture probability is improved, the accuracy of channel estimation is improved, and the frame delimitation and the Block Length field correct demodulation probability are also improved;

2) by setting the Block Length field, the end time of the frame can be accurately known according to the field during receiving, so that the receiving and transmitting conversion time is shortened, and the method has important significance for a packet switching network;

3) the Training Sequence and the information bit are modulated by a short spread spectrum Sequence, and the high-speed rate requirement can be met by adopting the short spread spectrum Sequence;

4) the load field is divided into a plurality of blocks, so that block-based transmission is realized, and block-based processing is facilitated;

5) a Tracking Sequence is inserted before or after each block. The Tracking Sequence can be used for performing a data-assisted timing Tracking function, and the Tracking performance is improved compared with the timing Tracking without data assistance;

6) the method and the device have the advantages that variable speed rate operations such as short code spread spectrum and Tracking Sequence insertion are realized by using the asynchronous FIFO, the realization is simple and convenient, and the expansibility is good.

Drawings

FIG. 1 is a prior art DS-UWB physical layer frame structure;

FIG. 2 is a physical layer frame structure of MB-OFDM in the prior art;

FIG. 3 is a physical layer frame structure used in a method of an embodiment of the invention;

FIG. 4 is a flow chart of a method of an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating the connection relationship between entity modules used in the apparatus according to the embodiment of the present invention;

fig. 6 is a state transition diagram of a state machine used in the apparatus of the embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.

According to the single-carrier ultra-wideband transmission method of the embodiment of the invention, the method uses the following physical layer data frame structure for transmission, as shown in fig. 3: the Preamble Sequence (Preamble) part comprises three fields of Acquisition/Channel Estimation Sequence, SFD and Block Length, wherein the Acquisition/Channel Estimation Sequence is used for spread spectrum Acquisition and Channel Estimation, SFD is a start of frame delimiter, and the Block Length is the Block number of the physical frame data segment. The Training Sequence is used for adaptive filter coefficient Training, and the Header includes a physical frame Header (PHY Header) and a MAC frame Header (MAC Header). Data carries payload Data. The bits after the Header and Data are scrambled, encoded, and interleaved are called information bits. The information bits are divided into N blocks. The value of each frame N may be different, so that frames of different lengths may be transmitted. In this embodiment, a Tracking Sequence is inserted behind each block for timing Tracking, and the Tracking Sequence may also be inserted in front of each block. As shown in fig. 4, the method includes the steps of:

s1, generating preamble sequence symbol step: before sending a data frame, setting block number, and generating a Preamble sequence (Preamble) symbol according to the block number: $[{\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="1"\; label="B\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="2"\; label="C\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}],$ at the moment, the state machine is in an idle state; wherein,

Acquisition/Channel Estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/channel estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or 0, j ═ 1, 2, …, N₂，k＝1，2，…，N₃；

Is N of block number₃Bit binary representation, e.g. assuming a block number of 7, the corresponding 4 bits are represented as $[{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}]=\left[\mathrm{0,1,1,1}\right],$ Of course the reverse order is also possible. Further, the tracking symbol is

Wherein,

trackingsequence, N, for data frames₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄。

S2, transmitting preamble chip sequence step: when starting to send data frame, the state machine changes from idle state to sending leading state; in the preamble sending state, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a preamble chip sequence according to the preamble sequence symbol generated in the step S1, and controls the multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence; in a few clock cycles before the preamble chip sequence is sent, the state machine enables the training sequence generator to generate a training sequence, and the training sequence is input into an asynchronous FIFO (First In First Out) structure, so that when the preamble chip sequence is sent, the training sequence data is already stored In the asynchronous FIFO structure, and when the preamble chip sequence is sent, the state machine is switched to a state of sending the training sequence.

S3, step of outputting training sequence chips: in a state of transmitting a training sequence, a state machine enables a short spread spectrum sequence generator and a short code spread spectrum modulation module, reads the training sequence from an asynchronous FIFO structure and carries out short code spread spectrum to generate an information chip sequence, and simultaneously, the state machine controls a multi-path selector to select an information chip sequence branch to carry out training sequence chip output; wherein the training sequence is a field of a data frame.

S4, generating payload bit data: the method comprises the steps that a state machine enables scrambling, coding and interweaving processing of a frame Header and Data to generate load bit Data after a period of time before a training sequence is sent out, the obtained load bit Data are input into an asynchronous FIFO structure, so that when the training sequence is sent out, the processed load bit Data are stored in the asynchronous FIFO structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into a plurality of block blocks, the block blocks are fields of a data frame, and a Tracking Sequence field is inserted before or after each block.

S5, outputting payload bit data: in a load sending state, a state machine enables a short spread spectrum sequence generator and a short code spread spectrum modulation module, load bit data are read from an asynchronous FIFO structure and short code spread spectrum is carried out to generate an information chip sequence, and meanwhile, the state machine controls a multi-path selector to select an information chip sequence branch to output the load bit data; after the information chip of one block is sent, the state is switched to a tracking sequence sending state.

S6, outputting tracking chip sequence: in the state of transmitting the tracking sequence, the state machine enables the long-spread spectrum sequence generator and the long-code spread spectrum modulation module, generates the tracking sequence according to the tracking symbol generated in the step S1, and controls the multiplexer to select a tracking chip sequence branch to output the tracking chip sequence.

S7, repeating steps S5 and S6: and ending the sending of the data frame until the preset block number is sent, and returning the state machine to an idle state.

An embodiment of the present invention further provides a single-carrier ultra-wideband transmitting apparatus, and referring to fig. 5 to 6, the apparatus includes:

a leading sequence symbol generating module, configured to set block number before sending the data frame, and generate a leading sequence symbol according to the block number: $[{\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="1"\; label="B\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">B</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_2,...,{\mathrm{<figure-callout\; id="2"\; label="C\; N"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">C</figure-callout>}}_{N_{}},{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}],$ at the moment, the state machine is in an idle state; wherein,

Acquisition/Channel Estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/channel estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or 0, j ═ 1, 2, …, N₂，k＝1，2，…，N₃；Is N of block number₃Bit binary representation, e.g. assuming a block number of 7, the corresponding 4 bits are represented as $[{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009102381825E00013.png"\; state="\{\{state\}\}">D</figure-callout>}}_2,...,D_{N_3}]=\left[\mathrm{0,1,1,1}\right],$ Of course the reverse order is also possible. Further, the tracking symbol is

Wherein,

trackingsequence, N, for data frames₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄。

A preamble chip sequence sending module, configured to switch a state machine from an idle state to a sending preamble state when starting sending a data frame; in the preamble sending state, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a preamble chip sequence according to the preamble sequence symbol generated in the step S1, and controls the multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence; and enabling the training sequence generator to generate a training sequence by the state machine in a plurality of clock cycles before the preamble chip sequence is sent, and inputting the training sequence into the asynchronous FIFO structure, so that when the preamble chip sequence is sent, the training sequence data are stored in the asynchronous FIFO structure, and when the preamble chip sequence is sent, the state machine is switched to a state of sending the training sequence.

A training sequence chip output module, which is used for enabling a short spread spectrum sequence generator and a short code spread spectrum modulation module by a state machine in a state of transmitting a training sequence, reading the training sequence from an asynchronous FIFO structure and carrying out short code spread spectrum to generate an information chip sequence, and simultaneously, controlling a multi-path selector to select an information chip sequence branch to carry out training sequence chip output by the state machine; wherein the training sequence is a field of a data frame.

A load bit Data generating module, which is used for scrambling, coding and interweaving a frame Header and Data by a state machine for a period of time before the training sequence is sent out, generating load bit Data, and inputting the obtained load bit Data into an asynchronous FIFO structure, so that when the training sequence is sent out, the processed load bit Data is stored in the asynchronous FIFO structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into a plurality of block blocks, the block blocks are fields of a data frame, and a Tracking Sequence field is inserted before or after each block.

A load bit data output module, which is used for reading load bit data from an asynchronous FIFO structure and performing short code spread spectrum to generate an information chip sequence by enabling a short spread spectrum sequence generator and a short code spread spectrum modulation module by a state machine in a load sending state, and meanwhile, the state machine controls a multiplexer to select an information chip sequence branch to output the load bit data; after the information chip of one block is sent, the state is switched to a tracking sequence sending state.

And the tracking chip sequence output module is used for enabling the long spread spectrum sequence generator and the long code spread spectrum modulation module by the state machine in a tracking sequence transmitting state, generating a tracking sequence according to the tracking symbol, and simultaneously controlling the multiplexer to select a tracking chip sequence branch by the state machine so as to output the tracking chip sequence. Wherein the tracking symbol is

Tracking Sequence, N, for a data frame₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄。

The following examples are given. The method of the embodiment of the invention uses the following parameters to complete the sending step:

long spreading sequence: [1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1 ];

short spreading sequence: [0, 1 ];

SFD sequence: [0, 1, 0, 1 ];

N₁＝24；N₂＝4；N₃＝4；N₄＝2；

one block information bit number: 2000.

the above description is only an embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (3)

1. A single-carrier ultra-wideband transmission method, comprising the steps of:

s1, generating a preamble symbol: before sending a data frame, setting block number, and generating a leader sequence symbol according to the block number:

at the moment, the state machine is in an idle state; wherein,Acquisition/Channel Estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/Channel Estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or O, j ═ 1, 2, …, N₂，k=1，2，…，N₃；

S2, transmitting the preamble chip sequence: when starting to send data frame, the state machine changes from idle state to sending leading state; in the preamble sending state, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a preamble chip sequence according to the preamble sequence symbol generated in the step S1, and controls the multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence; enabling a training sequence generator to generate a training sequence by a state machine in a plurality of clock cycles before the preamble chip sequence is sent out, and inputting the training sequence into an asynchronous first-in first-out structure, so that when the preamble chip sequence is sent out, the training sequence data are already stored in the asynchronous first-in first-out structure, and when the preamble chip sequence is sent out, the state machine is switched to a state of sending the training sequence;

s3, outputting training sequence chips: when the training sequence state is sent, the state machine enables the short spread spectrum sequence generator and the short code spread spectrum modulation module, reads the training sequence from the asynchronous first-in first-out structure and carries out short code spread spectrum to generate an information chip sequence, and simultaneously, the state machine controls the multi-path selector to select an information chip sequence branch to output the training sequence chip; wherein, the training sequence is a field of a data frame;

s4, generating payload bit data: the method comprises the steps that a state machine enables scrambling, coding and interweaving processing of a frame Header and Data to generate load bit Data after a period of time before a training sequence is sent out, the obtained load bit Data are input into an asynchronous first-in first-out structure, so that when the training sequence is sent out, the processed load bit Data are stored in the asynchronous first-in first-out structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into N block blocks, the block blocks are fields of a data frame, and a Tracking Sequence field is inserted before or after each block; n is a positive integer;

s5, outputting payload bit data: in a load sending state, a state machine enables a short spread spectrum sequence generator and a short code spread spectrum modulation module, load bit data are read from an asynchronous first-in first-out structure and short code spread spectrum is carried out to generate an information chip sequence, and meanwhile, the state machine controls a multi-path selector to select an information chip sequence branch to output the load bit data; after the information chip of one block is sent, the state is switched to a tracking sequence sending state;

s6, outputting tracking chip sequence: when the tracking sequence state is sent, the state machine enables the long spread spectrum sequence generator and the long code spread spectrum modulation module, generates a tracking sequence according to a tracking symbol, and controls the multiplexer to select a tracking chip sequence branch to output the tracking chip sequence; wherein the tracking symbol is [ E₁，E₂，…，

]，E₁，E₂，...，

Tracking Sequence, N, for a data frame₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄；

S7, repeating the steps S5 and S6, and sending the next block: and ending the sending of the data frame until the preset block number is sent, and returning the state machine to an idle state.

2. The single-carrier ultra-wideband transmission method of claim 1, wherein a number N of block of each data frame is different in value.

3. A single-carrier ultra-wideband transmitting apparatus, the apparatus comprising:

a leading sequence symbol generating module, configured to set block number before sending the data frame, and generate a leading sequence symbol according to the block number: [ B ]₁，B₂，…，

C₁，C₂，…，

D₁，D₂，…，]At this time, the state machine is in an idle state; wherein, B₁，B₂，...，、C₁，C₂，...，

、D₁，D₂，...，

Acquisition/Channel Estimation Sequence, frame start delimiter SFD and Block Length fields of the data frame are respectively used; n is a radical of₁，N₂And N₃Denotes the number of symbols, symbol B, of Acquisition/Channel Estimation Sequence, SFD and Block Length, respectively_i＝1，i＝1，2，…，N₁；C_jAnd D_kValues of 1 or 0, j ═ 1, 2, …, N₂，k＝1，2，…，N₃；

A preamble chip sequence sending module, configured to switch a state machine from an idle state to a sending preamble state when starting sending a data frame; in a preamble sending state, enabling a long spread spectrum sequence generator and a long code spread spectrum modulation module by a state machine, generating a preamble chip sequence according to a preamble sequence symbol generated by the preamble sequence symbol generating module, and simultaneously controlling a multi-path selector to select a preamble chip sequence branch to output the preamble chip sequence by the state machine; enabling a training sequence generator to generate a training sequence by a state machine in a plurality of clock cycles before the preamble chip sequence is sent out, and inputting the training sequence into an asynchronous first-in first-out structure, so that when the preamble chip sequence is sent out, the training sequence data are already stored in the asynchronous first-in first-out structure, and when the preamble chip sequence is sent out, the state machine is switched to a state of sending the training sequence;

a training sequence chip output module, which is used for reading the training sequence from the asynchronous first-in first-out structure and carrying out short code spread spectrum to generate an information chip sequence by using a state machine to enable a short spread spectrum sequence generator and a short code spread spectrum modulation module when the training sequence is sent, and meanwhile, the state machine controls a multi-path selector to select an information chip sequence branch to carry out training sequence chip output; wherein, the training sequence is a field of a data frame;

a load bit Data generation module, which is used for scrambling, coding and interweaving a frame Header and Data by a state machine for a period of time before the training sequence is sent out, generating load bit Data, and inputting the obtained load bit Data into an asynchronous first-in first-out structure, so that when the training sequence is sent out, the processed load bit Data is stored in the asynchronous first-in first-out structure, and when the training sequence is sent out, the state machine is switched to a load sending state; the load bit data is divided into a plurality of block blocks, each block is a field of a data frame, and a Tracking Sequence field is inserted before or after each block;

the load bit data output module is used for enabling the short spread spectrum sequence generator and the short code spread spectrum modulation module by the state machine in a load sending state, reading load bit data from the asynchronous first-in first-out structure and performing short code spread spectrum to generate an information chip sequence, and meanwhile, the state machine controls the multi-path selector to select an information chip sequence branch to output the load bit data; after the information chip of one block is sent, the state is switched to a tracking sequence sending state;

a tracking chip sequence output module, which is used for enabling the long spread spectrum sequence generator and the long code spread spectrum modulation module by the state machine when the tracking sequence state is sent, generating the tracking sequence according to the tracking symbol, and simultaneously controlling the multiplexer to select a tracking chip sequence branch by the state machine to output the tracking chip sequence; wherein the tracking symbol is [ E₁，E₂，…，]，E₁，E₂，...

Tracking Sequence, N, for a data frame₄Number of symbols for Tracking Sequence, symbol E_m＝1，m＝1，2，…，N₄。

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