CN101720485A - High forward current diodes for reverse write 3d cell and method of making thereof - Google Patents
High forward current diodes for reverse write 3d cell and method of making thereof Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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Abstract
A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read / write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
Description
Background technology
The sequence number that the application requires on June 25th, 2007 to submit to is the rights and interests of 11/819,078 and 11/819,079 U. S. application, and the full content of described U. S. application is incorporated herein by reference.
The present invention relates to nonvolatile memory array.
Even nonvolatile memory array also can keep the data of its storage when the power supply that disconnects device.In the One Time Programmable array, each memory cell is formed initial not programming state, and can be switched to programming state.This change is nonvolatil, and this unit can not be wiped.In the storer of other types, memory cell is erasable, and can be write repeatedly by heavy.
Unit further changes the quantity of the data mode that can realize each unit.Data mode can by change described unit can be detected some characteristics be stored, described characteristic for example for apply under the voltage in appointment or transistorized threshold voltage in the described unit under the flow through electric current of described unit.Data mode is the uniqueness value of unit, for example data ' 0 ' or data ' 1 '.
Some are used to obtain to wipe or the scheme of multi-mode unit is complicated.For example, floating boom and SONOS (silicon-oxide-nitride--oxide-silicon) memory cell is operated by stored charge, and the wherein existence of charge stored, disappearance or quantity change transistor threshold voltage.These memory cells are three end devices, and it is difficult to relatively make and is to operate under the required very little size of competitive power at contemporary integrated circuit.
Other memory cells are operated by the resistivity of Change Example such as chalkogenide relevant foreign materials such as (chalcogenide).Chalkogenide uses difficulty and may all be challenge to most of semiconductor production facilities.
Have and can wipe or the nonvolatile memory array of multi-mode memory cell will provide substantial advantage, described wipe or multi-mode memory cell uses conventional semiconductor material to form, its structure is easy to reduced to very little size.
Summary of the invention
The present invention is defined by the following claims, and this part content should be as the restriction to described claim.
An embodiment provides a kind of non-volatile memory device, and it comprises: at least one memory cell, described at least one memory cell comprise diode and the anti-fuse dielectric layer of metal oxide (antifuse dielectric layer); And first electrode and second electrode that electrically contact at least one memory cell.In use, diode is by switching to second resistivity states and as the read/write element of memory cell, wherein said second resistivity states is different with described first resistivity states in response to the biasing that is applied or bias voltage from first resistivity states.
Another embodiment provides a kind of non-volatile memory device, and it comprises: a plurality of memory cells, and first electrode and second electrode that electrically contact a plurality of memory cells.Each memory cell in described a plurality of memory cell comprises diode and the anti-fuse dielectric layer of metal oxide that is disposed in series between described first electrode and described second electrode, and described diode comprises polysilicon, germanium or the silicon-germanium p-i-r cylindricality diode with substantial cylindrical shape.
Each aspect of invention as herein described and each embodiment use that can be used alone or mutually combine.
Referring now to preferred aspect of description of drawings and embodiment.
Description of drawings
Fig. 1 is that the electricity between each memory cell that has illustrated in memory array is isolated the circuit diagram that needs.
Fig. 2 and Figure 16 a are according to the multimode of embodiments of the invention formation or the skeleton view of rewriteable memory cell, and Figure 16 b is its sectional view.
Fig. 3 is the skeleton view of a part that comprises the storage level of the memory cell among Fig. 2.
Fig. 4 shows along with the increase at the back-biased voltage at diode two ends, the figure of the change of the read current of memory cell of the present invention.
Fig. 5 shows from the V state to the P state, from the P state to the R state with the probability graph of memory cell from the R state to the S state transformation.
Fig. 6 shows from the V state to the P state, from the P state to the S state with the probability graph of memory cell from the S state to the R state transformation.
Fig. 7 shows from the V state to the R state, from the R state to the S state with the probability graph of memory cell from the S state to the P state transformation.
Fig. 8 is the skeleton view that can use vertically-oriented p-i-n diode in an embodiment of the present invention.
Fig. 9 shows from the V state to the P state and the probability graph of the memory cell from the P state to the M state transformation.
Figure 10 is the flow through electric current of diode and the graph of a relation of the voltage that is used to be applied to various diode states illustrated in fig. 5.
Figure 11 shows from the V state to the P state, from the P state to the R state with from the R state to the S state transformation, the probability graph of the memory cell of conversion repeatedly between S state and R state afterwards.
Figure 12 shows with the setover circuit diagram of bias scheme of S unit of forward bias.
Figure 13 shows with the setover circuit diagram of bias scheme of S unit of reverse bias.
Figure 14 has illustrated the unit has been moved into the reading of iteration in the data mode-verification-write circulation.
Figure 15 a-15c has illustrated the cut-open view that forms the process of storage level according to embodiments of the invention.
Figure 17 a-17c is according to the probability graph of embodiments of the invention with the various memory cells of the example of comparing.
Embodiment
The resistance that is known that the resistor that is formed by doping polycrystal silicon or polysilicon can be corrected by applying electric pulse, and it is regulated between stable resistance states.This amendable resistor has been used as the element in the integrated circuit.
Yet using amendable polyresistor storing data state in Nonvolatile memery unit is not conventional method.There are many difficulties in the memory array of making polyresistor.If resistor is used as memory cell in large-scale crosspoint array, then when voltage is applied to selected unit, will in both half-selected that spreads all over described array and the unit of selecting, there be the leakage of not expecting.For example, with reference to figure 1, suppose that voltage is applied between bit line B and the word line A with the selected cell S of setting, replacement or sensing.The expectation electric current flows through selected cell S.Yet some leakage currents can flow on interchangeable path, for example unit U1, U2 and the U3 through not selecting between bit line B and word line A.Can there be many so interchangeable paths.
By each memory cell being formed two end devices or the two-terminal device that comprises diode, can greatly reduce leakage current.Diode has non-linear I-V (volt-ampere) characteristic, is allowing very little electric current to flow through under the forward voltage and is allowing roughly bigger electric current to flow through on forward voltage.Usually, diode also is used as in one direction than be easier to the retaining valve that electric current flows through on another direction.Therefore, as long as selected bias scheme is to guarantee that only selected unit bears the forward current that is higher than forward voltage, then the leakage current along non-expected path (for example U1-U2-U3 sneak path among Fig. 1) can greatly be reduced.
The U.S. Patent application No.10/955 that is called " NonvolatileMemory Cell Without a Dielectric Antifuse Having High-andLow-Impedance States " that people such as Herner submitted on September 29th, 2004,549 have described a kind of monolithic three dimensional memory array, wherein the data mode of memory cell is stored with the resistivity states of the polycrystalline semiconductor material of semiconductor junction diode, described 10/955, No. 549 patented claim abbreviates ' 549 application and incorporated herein by reference hereinafter as.The sort memory unit is the One Time Programmable unit with two data states.Described diode forms with high resistivity state; The application of program voltage or apply described diode is for good and all transformed to low resistivity state.
In an embodiment of the present invention, by applying suitable electric pulse, can realize three, four or more a plurality of stable resistivity states by the memory component (for example semiconductor diode in No. 549 application of ') that doped semiconductor materials forms.In other embodiments of the invention, semiconductor material can be transformed into low resistivity state from initial high resistivity state; Afterwards, based on the application of suitable electric pulse, can turn back to higher resistivity states.These embodiment can use or the combined memory cell that can have two or more data modes with formation independently, and this memory cell can be One Time Programmable or rewritable.
As noted, the diode that is included between the conductor in the memory cell allows it to be formed in the highdensity cross point memory array.In preferred embodiment of the present invention, polycrystalline, semiconductor memery device amorphous or crystallite form with diode and connect, or more preferably form diode itself.
In this discussion, the conversion from the higher electric resistivity state to the low resistivity state is known as conversion is set, the influence that it is provided with electric current, voltage is set or pulse is set; And the reciprocal transformation from the low resistivity state to the higher electric resistivity state is known as the replacement conversion, and it is subjected to the influence of reset current, reset voltage or replacement pulse.
In preferred One Time Programmable embodiment, poly semiconductor diode and dielectric rupture antifuse (rupture antifuse) pairing, dielectric rupture antifuse for example is the high dielectric constant material antifuse layer, as following more detailed description.
Fig. 2 has illustrated the memory cell that forms according to the preferred embodiment of the present invention.Bottom conductor 12 is formed by conductive material, and conductive material is a tungsten for example, and extends upward in first party.Restraining barrier and bonding coat can be included in the bottom conductor 12.Poly semiconductor diode 2 has: bottom heavy doping n type zone 4; Non-intrinsic region 6 of having a mind to doping; And top heavily doped regional 8; Yet the orientation of this diode can be inverted.Regardless of its orientation, this diode all is known as p-i-n type diode.Dielectric rupture antifuse 14 provides in the mode of connecting with diode 2.Top conductor 16 can the mode identical with bottom conductor 12 forms and has identical materials with bottom conductor 12, and this top conductor 16 extends in the second direction different with first direction.Poly semiconductor diode 2 is vertically placed between bottom conductor 12 and the top conductor 16.Poly semiconductor diode 2 forms with high resistivity state.The sort memory unit can be formed on the suitable substrate, for example is formed on the silicon single crystal wafer.Fig. 3 shows the part of the storage level of this device that is formed in the crosspoint array or device, and wherein diode 2 is placed in (anti-fuse 14 is omitted in this diagram) between bottom conductor 12 and the top conductor 16.A plurality of storage level can be stacked on the substrate to form highdensity monolithic three dimensional memory array.
In this discussion, the non-doped regions intentionally of semiconductor material is described to intrinsic region.Yet, it will be appreciated by those skilled in the art that in fact intrinsic region can comprise low concentration p type or n type adulterant.Adulterant can be diffused into the intrinsic region from adjacent area, perhaps owing to be presented in the deposition chambers between depositional stage from the pollutant of more early deposition.What will be further understood that is that the intrinsic material (for example silicon) of deposition can comprise and makes it show as the defective that light n type mixes.Use term " intrinsic " to describe silicon, germanium, silicon-germanium alloy or some other semiconductor materials and do not mean that this zone of hint does not comprise other adulterants, do not mean that also such zone is desirable electroneutral.
For example the polycrystalline of doping such as silicon or the resistivity of crystallite semiconductor materials can change between steady state (SS) by applying suitable electric pulse.Have been found that in a preferred embodiment, conversion be set advantageously carry out that the conversion of resetting simultaneously is easy to most be realized and control by the diode under the reverse bias by the diode under forward bias or the bias voltage.Yet in some cases, conversion is set can be realized by the diode under reverse bias or the bias voltage, and the replacement conversion is realized by the diode under the forward bias.
The semiconductor switching behavior is complicated.For diode, conversion and replacement conversion are set realize by the diode under the forward bias.Usually, the amplitude that is applied to the replacement pulse (its polycrystalline semiconductor material that is enough to constitute diode switches to higher resistivity states from the resistivity states of appointment) of the diode under the forward bias will be lower than the amplitude of corresponding setting pulse (it switches to lower resistivity states with identical polycrystalline silicon material from identical resistivity states) and will have wideer pulse width.
Switching under reverse bias has demonstrated unique behavior.Suppose that polysilicon p-i-n type diode as shown in Figure 2 bears relatively large switch pulse under reverse bias.After using switch pulse, apply the littler pulse of reading, for example 2 volts, and measure the electric current of the described diode of under this read-out voltage, flowing through, this electric current is called read current.Along with the increase of voltage in succeeding impulse of the switch pulse under the reverse bias, as shown in Figure 4 in the change of the follow-up read current of 2 volts of voltages.Can see originally increase along with the reverse voltage and the electric current of switch pulse, when read-out voltage when each switch pulse is after-applied, read current increases, and promptly the initial transformation of semiconductor material (being silicon in the case) is towards lower resistivity in direction is set.In case switch pulse reaches specific reverse bias voltage, promptly the some K among Fig. 4 is about-14.6 volts in this example, and then read current begins suddenly to descend, and realizes that simultaneously the resistivity of replacement and silicon increases.When beginning to apply the reverse bias switch pulse, make that trend is reversed and the silicon of diode begins to reset switched voltage is set to be changed based on the resistivity states of the silicon that for example constitutes diode.By selecting suitable voltage, the setting or the replacement that constitute the semiconductor material of diode can be realized by the diode under the reverse bias after can seeing.
The unique data state of memory cell of the present invention is corresponding to the polycrystalline that constitutes diode or the resistivity states of crystallite semiconductor materials, when applying read-out voltage, described unique data state and resistivity states are distinguished by the flow through electric current of memory cell (between top conductor 16 and bottom conductor 12) of detection.Preferably, the electric current that flows between any unique data state unique data state different with any one differs from two times at least, to allow to be easy to detect the difference between each state.
Described memory cell can be used as One Time Programmable unit or rewriteable memory cell, and can have two, three, four or more a plurality of unique data state.Described unit can be under biasing forward or backwards with random order from its arbitrary data state exchange to its any other data modes.In use, diode is by switching to second resistivity states different with first resistivity states and as the read/write element of memory cell in response to the biasing that applies from first resistivity states.
The read current of the diode of having programmed in one embodiment of the invention, can increase by the anti-fuse that uses high-k (k).With SiO than low-k
2Anti-fuse is compared, and these anti-fuses are shown as and make the read current of having programmed specify (for example under the 2V read-out voltage) increase 50% under the read-out voltage.This causes the electric current of programming state of reverse write store unit and the more big difference between the Reset Status electric current.
Preferably, anti-fuse comprises the anti-fuse dielectric layer of metal oxide, for example has the layer that is higher than 3.9 specific inductive capacity, and this specific inductive capacity for example is about 4.5 to about 8.Can also use other dielectric layers that have greater than 3.9 specific inductive capacity.Metal oxide materials can be stoichiometric or non-stoichiometric material.For example, metal oxide can be selected from the following material a kind of material or more than a kind of mixing of material: hafnia, aluminium oxide, titanium dioxide, lanthana, tantalum oxide, ruthenium-oxide, zirconium Si oxide, aluminium-silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxides of nitrogen, zirconium sieve and silica-sesquioxide, hafnium aluminium-silicon oxide, hafnium aluminium silicon oxides of nitrogen or zirconium sial oxides of nitrogen.These materials can have following chemical formula: HfO
2, Al
2O
3, ZrO
2, TiO
2, La
2O
3, Ta
2O
5, RuO
2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON and ZrSiAlON, and can with SiO
2And/or SiNx combination or combination.Hafnia or aluminium oxide are preferred.
Preferably, the p type zone of anti-fuse dielectric layer of metal oxide and diode is adjacent.Described anti-fuse dielectric layer is preferably has the thickness of about 10 dusts to about 100 dusts, and for example about 30 dusts are to about 40 dusts.
The example of some preferred embodiments will be provided.Yet, should be appreciated that these examples are not intended to as restriction.The additive method of clearly two-terminal device (two-terminal device) that comprises diode and polycrystalline or crystallite semiconductor materials being programmed will fall within the scope of the present invention to those skilled in the art.
The One Time Programmable multi-level unit
In a preferred embodiment of the invention, diode and the dielectric rupture antifuse that is formed by polycrystalline semiconductor material placed between top conductor and the bottom conductor by series connection.Two-terminal device is used as the One Time Programmable multi-level unit, has three or four unique data states in a preferred embodiment.
Preferred memory cell is presented among Fig. 2.Diode 2 is preferably formed by polycrystalline or crystallite semiconductor materials, for example the alloy of silicon, germanium or silicon and/or germanium.Diode 2 most preferably is polysilicon.In this example, bottom heavily doped region 4 be the n type and top-heavy doped region 8 is p types, though the polarity of diode can be inverted.Memory cell comprises the part of top conductor, a part and the diode of bottom conductor, and described diode places between the conductor.
When forming, polysilicon diode 2 is in high resistivity state, and dielectric rupture antifuse 14 is intact.Fig. 5 shows the probability graph of the electric current of a plurality of memory cells under different conditions that comprises the silicon dioxide antifuse dielectric layer.With reference to figure 5, when for example 2 volts read-out voltage is applied between top conductor 16 and the bottom conductor 12 (diode 2 is in forward bias), be preferably at the read current that flows between top conductor 16 and the bottom conductor 12 and receiving in the scope of peace, for example receive peace less than about 5.Regional V among Fig. 5 is corresponding to first data mode of memory cell.For some memory cells in the array, this unit will not bear and be provided with or the replacement pulse, and this state will be read the data mode as memory cell.This first data mode will be called as the V state.
Being preferably first electric pulse that is under the forward bias at diode 2 is applied between top conductor 16 and the bottom conductor 12.This pulse for example between about 8 volts to about 12 volts, for example is about 10 volts.Described electric current is for example between about 80 microamperes and about 200 microamperes.Pulse width was preferably between about 100 nanoseconds and about 500 nanoseconds.This first electric pulse cuts off dielectric rupture antifuse 14 and the semiconductor material of diode 2 is switched to second resistivity states from first resistivity states, and the resistivity of described second state is lower than the resistivity of first state.Described second data mode will be called as the P state, and this conversion is marked as " V → P " in Fig. 5.At the electric current that flows between top conductor 16 and bottom conductor 12 under 2 volts the read-out voltage is about 10 microamperes or more.The resistivity that constitutes the semiconductor material of diode 2 is reduced to about 1/1000 to about 1/2000 of former resistivity.In other embodiments, the change of resistivity is less, but any data mode and arbitrarily between other data modes near looking younger differ from two times, be preferably and differ three times or five times at least, and more typically differ 100 times or bigger.Some memory cells in the array will read under this data mode, and will not bear extra setting or replacement pulse.This second data mode will be called as the P state.
For example, 1 * 10 under the programming state never of the read current under the 2V voltage
-8A increases at least 1 * 10 behind the programming pulse
-5A.Following form demonstrates the increase program voltage and causes higher read current.Last row in the form demonstrate the standard deviation of read current.
It should be noted that the read current that shows in the form is used for the unit with interconnection and silicon dioxide antifuse shown in Fig. 2 in the above.If remove interconnection and use the anti-fuse of metal oxide, then read current can be higher.For example, for the program voltage of 8.4V, the unit that does not have an interconnection at least+read-out voltage of 1.5V (for example is at least 3.5 * 10 for+1.5V to+read current under 2V)
-5A.What expect is further to increase program voltage the read current of increase will further be provided.For example, program voltage is increased to the increment that 10V is desirably in generation about 70% read current from 8.4V, thereby make the read current of unit under the 2V read-out voltage be about 6 * 10 with interconnection
-5A.As mentioned above, a plurality of programming pulses (for example 2 to 10 pulses, 3-5 pulse for another example) can be applied to diode.In addition, the use of the anti-fuse dielectric layer of metal oxide has further increased read current, and this will discussed below with reference to Figure 17 a-17c.
Second electric pulse preferably is at diode 2 and is applied under the reverse bias between top conductor 16 and the bottom conductor 12.For example, this pulse is preferably between-10 volts of peace treaties-12 approximately volt between about-8 volts of peace treaties-14 volt, is preferably-11 volts approximately.Described electric current for example about 80 receive the peace and about 200 receive the peace between.Described pulse width for example between about 100 nanoseconds and about 10 microseconds, is preferably between about 100 nanoseconds and about 1 microsecond, the most preferably between about 200 nanoseconds and about 800 nanoseconds.This second electric pulse switches to the 3rd resistivity states with the diode 2 of semiconductor material from second resistivity states, and the resistivity of described the 3rd resistivity states is higher than the resistivity of second resistivity states.Flow through under 2 volts the read-out voltage between top conductor 16 and the bottom conductor 12 electric current about 10 receive the peace and about 500 receive the peace between, be preferably about 100 receive the peace and about 500 receive the peace between.Some memory cells in the array will read under this data mode, and will not bear extra setting or replacement pulse.This 3rd data mode will be called as the R state, and this conversion is marked as " P → R " in Fig. 5.
Figure 10 is the read current of various diode states and the figure of read-out voltage relation of being used for illustrated in fig. 5.Originally diode starts from low read current state V (being called not programming or " original " state).Described diode is advanced to programming state P by high forward bias pulse, preferably carries out in product is made the factory of this diode by before sales, does not need to consider power supply this moment.In case product is sold, then diode is advanced among the Reset Status R by the reverse bias programming pulse subsequently.Difference between the read current of the read current of programming state P and Reset Status R has been formed " window " of memory cell, as shown in figure 10.Big program voltage and/or a plurality of programming pulse allow this window big as far as possible so that make firm.
In order to realize the 4th data mode, the 3rd electric pulse preferably is at diode 2 and is applied under the forward bias between top conductor 16 and the bottom conductor 12.This pulse for example between about 8 volts and about 12 volts, for example is about 10 volts, and wherein electric current is between about 5 microamperes and about 20 microamperes.This 3rd electric pulse switches to the 4th resistivity states with the diode 2 of semiconductor material from the 3rd resistivity states, and the resistivity of described the 4th resistivity states is lower than the resistivity of the 3rd resistivity states, and preferably is higher than the resistivity of second resistivity states.Electric current between top conductor 16 and the bottom conductor 12 flowing through under 2 volts the read-out voltage between about 1.5 microamperes and about 4.5 microamperes.Some memory cells in the array will be read under this data mode, and this state is called as the S state, and this conversion is marked as " R → S " in Fig. 5.
Electric current between any two the adjacent data states under the described read-out voltage (for example being 2 volts) preferably differs two times at least.For example, the read current of any unit under the data mode R is preferably the read current that is twice in any unit under the data mode V at least, the read current of any unit under the data mode S is preferably the read current that is twice in any unit under the data mode R at least, and the read current under the data mode P is preferably the read current that is twice in any unit under the data mode S at least.For example, read current under the data mode R can be twice in the read current under the data mode V, read current under the data mode S can be twice in the read current under the data mode R, and the read current under the data mode P can be twice in the read current under the data mode S.If scope is defined lessly, then difference can be quite big.For example, if maximum current V state cell can have 5 receive the peace read current and minimum current R state cell can have 100 receive the peace read current, then the difference of electric current reaches 20 times at least.By selecting other restrictions, can guarantee that the difference of the read current between adjacent memory state will reach three times at least.
As described below, can carry out the reading of iteration-verification-write processing with guarantee memory cell be provided with or the replacement pulse after be in the data state in the data mode of a plurality of definition, rather than be between the data mode of described a plurality of definition.
So far, maximum current in the data state and the difference between the minimum current in the next the highest adjacent data state have been discussed.The difference of the read current under adjacent data mode in most of unit will be bigger, for example the memory cell under the V state can have 1 receive the peace read current, unit under the R state can have 100 receive the peace read current, unit under the S state can have the read current of 2 microamperes (2000 receive peace), and the unit under the P state can have 20 microamperes read current.These electric currents under each adjacent states differ 10 times or more.
Memory cell with four unique data states has been described.In order to help to distinguish each data mode, preferably select three data states rather than four data states.For example, the three condition memory cell can form data mode V, is set to data mode P, resets to data mode R afterwards.This unit will not have the 4th data mode S.In this case, the difference between the adjacent data state, for example the difference between R data mode and the P data mode can be quite big.
The memory array of foregoing one-time programmable memory cell can be programmed as previously mentioned, and each unit is programmed into the data state (in one embodiment) in three unique data states or is programmed into a data state (in interchangeable embodiment) in four unique data states.These only are examples, obviously can have unique resistivity states and corresponding data mode more than three or four.
Yet in the memory array of one-time programmable memory cell, can programme in a variety of forms in described unit.For example, with reference to figure 6, the memory cell among Fig. 2 can form first state, i.e. the V state.First electric pulse preferably cuts off anti-fuse 14 and polysilicon diode is switched to second resistivity states that is lower than described first resistivity states from first resistivity states under forward bias, memory cell is placed the P state, and this P state is minimum resistivity states in this example.Second electric pulse preferably switches to the 3rd resistivity states with polysilicon diode from second resistivity states under reverse bias, the resistivity of described the 3rd resistivity states is higher than the resistivity of second resistivity states, and memory cell is placed the S state.The 3rd electric pulse equally preferably switches to the 4th resistivity states with polysilicon diode from the 3rd resistivity states under reverse bias, the resistivity of described the 3rd resistivity states is higher than the resistivity of second resistivity states, and memory cell is placed the R state.For any specified memory cells, the arbitrary data state promptly: V state, R state, S state and P state can be read the data mode as memory cell.Each conversion all is marked among Fig. 6.Shown four peculiaries, can have three or on demand more than four state.
In other embodiments, each continuous electric pulse all can switch to the diode of semiconductor material and continue lower resistivity states.For example, as shown in Figure 7, memory cell can proceed to the R state from initial V state, proceed to the S state from the R state, and proceed to the P state from the S state, wherein for each state, read current is twice in the read current of state before at least, and each state is corresponding to the data mode of a uniqueness.In this example, pulse can apply under the biasing forward or backwards.In interchangeable embodiment, can have three data states or more than four data states.
In one embodiment, memory cell comprises polysilicon diode 2 shown in Fig. 8 or crystallite diode 2, and this diode 2 comprises bottom heavy doping p type zone 4, middle part intrinsic-OR lightly doped region 6 and top-heavy Doped n-type zone 8.As in the aforementioned embodiment, this diode 2 can with the dielectric rupture antifuse arranged in series, they are disposed between top conductor and the bottom conductor.Bottom heavy doping p type zone 4 can be in-situ doped, promptly provides the gas of p type adulterant (for example boron) to mix by flowing during polysilicon deposition, thereby dopant atom is attached in the film of its formation.
With reference to figure 9, found that the sort memory unit forms the V state, wherein the electric current between top conductor under 2 volts the read-out voltage 16 and bottom conductor 12 is received peace less than about 80.First electric pulse is preferably under for example about 8 volts forward bias and applies, thereby cut off dielectric rupture antifuse 14, and polysilicon diode 2 is switched to second resistivity states from first resistivity states, the resistivity of described second resistivity states is lower than the resistivity of first resistivity states, and memory cell is placed data mode P.In data mode P, at the electric current between top conductor under the described read-out voltage 16 and the bottom conductor 12 between about 1 microampere and about 4 microamperes.Second electric pulse preferably applies under reverse bias, thereby polysilicon diode 2 is switched to the 3rd resistivity states from second resistivity states, and the resistivity of described the 3rd resistivity states is lower than the resistivity of first resistivity states.The 3rd resistivity states is corresponding to data mode M.In data mode M, the electric current between top conductor under the described read-out voltage 16 and the bottom conductor 12 about 10 receive the peace on.As described in embodiment before, between any unit in the adjacent data state (between the state V of maximum current unit and the state P of minimum current unit, or between the state M of the state P of maximum current unit and minimum current unit) the difference of electric current preferably differ at least and reach two times, preferably differ and reach three times or more.Arbitrary data state V, P or M can be detected as the data mode of memory cell.
Fig. 4 shows when semiconductor diode bears reverse bias, and usually, originally semiconductor material is exposed to the conversion that is provided with of lower resistivity, afterwards, along with the increase of voltage, is exposed to the replacement conversion of higher resistivity.For this specific diode, it has top-heavy Doped n-type zone 8 and preferably has the bottom heavily doped region 4 that is formed by in-situ doped p type adulterant, the unexpected or generation hastily from setting transforms to the diode of switching unlike other embodiment of replacement conversion by increasing reverse bias voltage.This means that for this diode the conversion that is provided with under the reverse bias is easier to control.
Rewriteable memory cell
In other of embodiment were provided with, memory cell showed as rewriteable memory cell, and it can switch between two or three data states repeatedly.
With reference to Figure 11, in one embodiment, memory cell forms high resistivity state V, wherein the electric current of depressing at 2 voltaisms be about 5 receive the peace or littler.Curve shown in Figure 11 is about the unit with silicon dioxide antifuse.For most of rewritable embodiment, the data mode of initial V state it goes without doing memory cell.First electric pulse preferably is applied between top conductor 16 and the bottom conductor 12 under by forward biased situation at diode 2.This pulse for example between about 8 volts and about 12 volts, is preferably about 10 volts.This first electric pulse switches to the second resistivity states P with the diode 2 of semiconductor material from first resistivity states, and the resistivity of described second state is lower than the resistivity of first state.In a preferred embodiment, the P state is not equally as the data mode of memory cell.In other embodiments, the P state will be as the data mode of memory cell.
Second electric pulse preferably is being applied under the situation that diode 2 is reverse biased between top conductor 16 and the bottom conductor 12.This pulse is preferably between-9 volts of peace treaties-13 approximately volt more preferably about-10 volts or-11 volts for example between about-8 volts of peace treaties-14 volt.Required voltage will change with the thickness of intrinsic region.This second electric pulse switches to the 3rd resistivity states R with the diode 2 of semiconductor material from second resistivity states, and the resistivity of the described third state is higher than the resistivity of second state.In a preferred embodiment, the R state is corresponding to a data mode of memory cell.
The 3rd electric pulse can be applied between top conductor 16 and the bottom conductor 12, and it preferably applies under by forward biased situation at diode 2.This pulse for example between about 5.5 volts and about 9 volts, is preferably about 6.5 volts, and wherein electric current is preferably between about 50 microamperes and about 100 microamperes between about 10 microamperes and about 200 microamperes.This 3rd electric pulse switches to the 4th resistivity states S with the diode 2 of semiconductor material from the 3rd resistivity states R, and the resistivity of described four condition is lower than the resistivity of the third state.In a preferred embodiment, the S state is corresponding to the data mode of memory cell.
In the embodiment of this rewritable two condition, R state and S state are sensed or be read as data mode.Memory cell can switch between these two states repeatedly.For example, the 4th electric pulse preferably switches to the 5th resistivity states R with the diode of semiconductor material from the 4th resistivity states S under the situation that diode 2 is reverse biased, and the 5th resistivity states R and the 3rd resistivity states R are basic identical.The 5th electric pulse preferably switches to the 6th resistivity states S with the diode of semiconductor material from the 5th resistivity states R at diode 2 under by forward biased situation, and the 6th resistivity states S and the 4th resistivity states S are basic identical, by that analogy.May be more difficult be that memory cell is returned to the initial V state and the second state P.Therefore, these states can not be used as data mode in rewriteable memory cell.May preferably make the unit is switched to first electric pulse of P state and the unit is performed before memory array incoming terminal user from second electric pulse that the P state switches to the R state from initial V state, for example, carry out in factory or testing apparatus, perhaps the dealer by before sales carries out.In other embodiments, may preferably only make the unit is performed before memory array incoming terminal user from first electric pulse that initial V state switches to the P state.
As from seen in fig. 11, in the example that is provided, under 2 volts read-out voltage for example, the difference between the electric current that flows between top conductor 16 and the bottom conductor 12 between any unit in data state and any unit in the adjacent data state differs three times at least, in this case, be (receiving peace and about 500 about 10 receives between the peace) R data mode and (between about 1.5 microamperes and about 4.5 microamperes) S data mode.Be based upon the selected scope of each data mode, difference can differ and reach two times, three times, five times or more.
In interchangeable embodiment, rewriteable memory cell can switch between three or more data states with random order.Conversion or replacement conversion are set can be carried out by the diode under forward bias or reverse bias.
Attention is at described One Time Programmable and can rewriteeing among the embodiment, and data mode is all corresponding to the polycrystalline that constitutes diode or the resistivity states of crystallite semiconductor materials.Described data mode does not correspond to the resistivity states of resistivity-switching metal oxide or nitride, as the U.S. Patent application No.11/395 of people such as Herner in " the Nonvolatile Memory CellComprising a Diode and a Resistance-Switching Material " by name of submission on March 31st, 2006, described in 995, this patented claim return assignee of the present invention all and incorporated herein by reference.
Setting under the reverse bias and replacement
In array of memory cells according to so far described embodiment formation and programming, to compare with the forward bias step, the arbitrary steps that makes the unit bear big reverse bias voltage all has the leakage current that reduces.
With reference to Figure 12, (the actual voltage that uses will depend on many factors to suppose 10 volts voltage to be applied to selected cell S two ends in forward bias, comprise structure, the adulterant grade of described unit, height of intrinsic region etc., 10 volts only as example).Bit line B0 is set to 10 volts and word line W0 and is set to ground connection.All the time be lower than the forward voltage of diode in order to ensure the unit F (itself and selected cell S share bit lines B0) of both half-selected, word line W1 is set to be lower than but quite near the voltage of bit line B0, for example word line W1 can be set to 9.3 volts, thereby make 0.7 volt to be applied to two ends, F unit (only show a F unit, but can have hundreds of, thousands of or more a plurality of F unit).Similarly, all the time be lower than the forward voltage of diode in order to ensure the unit H (itself and selected cell S shared word line W0) of both half-selected, bit line B1 is set to be higher than but quite approaches the voltage of word line W0, for example bit line B1 can be set to 0.7 volt, thereby make 0.7 volt to be applied to H two ends, unit (same, as can to have thousands of H unit).The selected unit U with cell S shared word line W0 that selectes or bit line B0 does not bear-8.6 volts voltage.Owing to can have numerous not selected unit U, so this causes significant leakage current in the array.
Figure 13 shows the favourable bias scheme that bigger reverse bias (for example as the replacement pulse) is applied to the memory cell two ends.Bit line B0 is set to-5 volts and word line W0 and is set to 5 volts, thereby makes-10 volts to be applied to selected cell S two ends, and described diode is reverse biased.Under the reverse bias that is low to moderate the accident setting that is enough to not cause these unit or replacement, word line W1 and bit line B1 are set to ground connection makes the unit F of both half-selected and H bear-5 volts of voltages.As if the setting under the reverse bias or reset generally occurs in or is reversed the voltage of puncture near diode, and this voltage generally is higher than-5 volts.By this scheme, there is not voltage in Xuan Ding U two ends, unit, thereby can not cause reverse leakage.
Bias scheme among Figure 13 only is an example, obviously can use many other schemes.For example, bit line B0 can be set to 0 volt, and word line W0 is set to 10 volts, and bit line B1 and word line W1 all are set to-5 volts.Identical in the scheme of voltage in Figure 13 at the voltage at selected cell S two ends, the unit H of both half-selected and the voltage at F two ends and the U two ends of not selecting, unit.In other examples, bit line B0 is set to ground connection, and word line W0 is set to 10 volts, and bit line B1 and word line W1 all are set to 5 volts.
The setting of iteration and replacement
So far discussed applying suitable electric pulse and switch to different resistivity states from a resistivity states with diode with semiconductor material, thus between two unique data states the switchable memory unit.In the practice, these settings and replacement step can be the processing of iteration.
As described, the difference between the electric current during reading the adjacent data state is preferably to differ at least and reaches two times, in many examples, can be preferably each data mode and set up range of current, and these range of current are separated by three times, five times, ten times or more.
With reference to Figure 14, as described, under 2 volts read-out voltage, data mode V can be defined as read current be 5 receive the peace or littler, data mode R be defined as read current about 10 receive the peace and about 500 receive the peace between, data mode S is defined as read current between about 1.5 microamperes and about 4.5 microamperes, and data mode P is defined as read current on about 10 microamperes.Those skilled in the art will recognize that these only are examples.In other embodiments, for example, during data mode V can be defined within more among a small circle, wherein under 2 volts read-out voltage, read current was about 5 and receives peace or littler.Actual read current will be along with the structure of the characteristic of unit, array, selected read-out voltage and many other factor and is changed.
Suppose that one-time programmable memory cell is among the data mode P.Back-biased electric pulse is applied to memory cell so that described unit is switched among the data mode S.Yet, in some cases, may be after applying electric pulse, read current is not in the expected range, and promptly the resistivity states of the diode of semiconductor material is higher or lower than expectation value.For example, suppose after applying electric pulse that the read current of memory cell is in the Q point between S state and P state current scope shown in the figure.
Be applied in after memory cell is switched to the expected data state at electric pulse, memory cell can be read to determine whether to have reached the desired data state.If do not reach the desired data state, then apply extra pulse.For example, when electric current Q was sensed, extra replacement pulse was applied in increasing the resistivity of semiconductor material, thereby read current is reduced in the scope corresponding to the S data mode.As previously mentioned, this set pulse can be applied under forward bias or back-biased situation.Extra one or more pulses can have amplitude or amplitude (voltage or electric current) or the longer or shorter pulse width higher than original pulse.After additionally pulse being set, described unit is read once more, and setting or replacement pulse afterwards suitably applied until read current and be in the expected range.
In described two-terminal devices such as memory cell that comprise diode for example, particularly advantageous is to read so that verification setting on demand or replacement and regulate.Therefore apply bigger reverse bias at the diode two ends and may damage this diode, when when being in diode reverse bias under and carrying out setting or replacement, advantageously minimize reverse bias voltage.
Make Consideration
The U.S. Patent application No.11/148 that is called " Nonvolatile MemoryCell Operating by Increasing Order in Polycrystalline SemiconductorMaterial " that people such as Herner submitted on June 8th, 2006,530 and the U.S. Patent application No.10/954 of Herner " the Memory Cell Comprising a Semiconductor JunctionDiode Crystallized Adjacent to a Silicide " by name that submit on September 29th, 2004,510 be assignee of the present invention all and incorporated herein by reference, the polysilicon crystal that contiguous suitable silicide has been described in these applications influences the characteristic of polysilicon.Specific metal silicide, for example cobalt silicide and titanium silicide have the crystalline network very approaching with the structure of silicon.When amorphous silicon or microcrystal silicon in these silicides of contact a kind of silicide and during crystallization, the crystal lattices of silicide provides template for silicon during crystallization.The polysilicon that produces will be high-sequential and defective quite few.When strengthening the adulterant doping with conductivity, this high-quality polysilicon has quite high electric conductivity after formation.
On the contrary, when amorphous silicon or microcrystal silicon material do not contact with silicon (described silicon has the silicide that has good lattice matched with it) and during crystallization, when for example only contacting with materials such as titanium nitrides with for example silicon dioxide with tangible lattice mismatch, the polysilicon that produces will have more defects, and the polysilicon of the doping of crystallization by this way has much lower electric conductivity after formation.
In aspect of the present invention, the semiconductor material that forms diode switches between two or more resistivity states, change the electric current of the diode of flowing through under the read-out voltage of appointment, different electric current (and resistivity states) is corresponding to each unique data mode.Find the also contiguous silicide that forms by the silicon (or other suitable semiconductor materials, for example germanium or sige alloy) of high defective or provide the similar material of crystallization template and the diode of crystallization shows the most favourable switching behavior or performance.
Do not expecting under the situation about being retrained by any particular theory, believe in the change of the resistivity that observes a kind of feasible mechanism behind it is that the pulse that is provided with on threshold amplitude makes dopant atom shift out crystal boundary, said dopant atom is a non-activity, enter then in the main body of crystal, will increase conductance this its and reduce the resistance of semiconductor material.On the contrary, the replacement pulse can be so that dopant atom be moved back into crystal boundary, thereby reduces conductivity and increase resistance.Yet, may there be other mechanism, for example carry out or be substituted by the degree of order (degree of order) of carrying out increase and reducing polycrystalline material simultaneously.
Found contiguous suitable silicide and the resistivity states of the silicon of the very low defective of crystallization easily is switched can not have higher defect rank as semiconductor material the time.Possible reason is that the existence of the crystal boundary of the existence of defective or larger amt allows easier switching.In a preferred embodiment, form the contiguous material that has less lattice mismatch with it of the polycrystalline of diode or micro crystal material afterwards and crystallization.Less lattice mismatch is for example about 3% or littler lattice mismatch.
Proposed to concentrate on evidence in the change in the intrinsic region about switching behavior.In resistor and p-n junction diode, observe switching behavior, and be not limited to p-i-n type diode, but believe that the use of p-i-n type diode can be particularly advantageous.So far described embodiment comprises p-i-n type diode.Yet in other embodiments, described diode can replace by having p-n junction diode very little or that do not have intrinsic region.
The detailed example of the making of the preferred embodiments of the present invention will be provided a description.From the U.S. Patent application No.10/320 of people such as Herner in " the An Improved Method forMaking High Density Nonvolatile Memory " by name of submission on Dec 19th, 2002,470 manufacturing details will have use in the formation of the diode of these embodiment, as described in the information of ' 549 from U.S. Patent application, and owing to this patented claim is abandoned, so it is incorporated herein by reference.The U.S. Patent application No.11/015 of " Nonvolatile Memory Cell Comprising aReduced Height Vertical Diode " by name that Useful Information can also be submitted to from people such as Herner on Dec 17th, 2004, obtain in 824, it is transferred to assignee of the present invention and incorporated herein by reference.For fear of obscuring the present invention, this paper does not write the full details from these applications, but is understandable that this paper is not intended to get rid of any information from these applications.
Example
The manufacturing of single memory level will be illustrated in greater detail.Extra storage level can be stacked, and each storage level is monolithically formed in its lower section the storage level.In the present embodiment, the poly semiconductor diode will be as switchable memory component.
With reference to figure 15a, the making of storer starts from substrate 100.This substrate 100 can be any Semiconductor substrate as known in the art, monocrystalline silicon for example, IV-IV such as SiGe or Germanium carbon compounds of group for example, III-V compounds of group, II-VII compounds of group, the epitaxial loayer on described substrate or other any semiconductor materials.Described substrate can comprise the integrated circuit that is made in wherein.
With the following one deck that is deposited is conductive layer 106.Conductive layer 106 can comprise any conductive material well known in the art, and for example tungsten or other materials comprise tantalum, titanium, copper, cobalt or their alloy.
In case will form whole layers of conductor rail (conductor rail) all is deposited, then described layer will use suitable arbitrarily mask and etch process is patterned and etching, with form almost parallel, the conductor 200 of coplane roughly, shown in the cut-open view among Figure 15 a.In one embodiment, photoresist or photoresist are deposited, by photoetching technique be patterned and these layers etched, and use standard process techniques to remove photoresist afterwards.Alternatively, conductor 200 can use inlaying process (Damascene) to form.
At last, the unnecessary dielectric material 108 on the top of removal conductor rail 200 exposes the top of the conductor rail 200 that is separated by dielectric material 108, and stays the surface 109 of general planar.The structure that is produced is shown in Figure 15 a.The dielectric material that this removal is overflowed can be carried out by any technology well known in the art with the technology that forms flat surfaces 109, for example chemical-mechanical planarization (CMP) or etch-back technics.The etch-back techniques that can advantageously use is described in the U. S. application No.10/883417 of " Nonselective Unpatterned Etchbackto Expose Buried Patterned Features " by name that people such as Raghuram submitted on June 30th, 2004 and is incorporated herein by reference.In this stage, a plurality of first substantially parallel conductors highly are formed on the substrate 100 with first.
Secondly, with reference to figure 15b, column will be formed on the conductor rail of finishing 200 and (in order to save the space, not show substrate 100 in Figure 15 b, but suppose that this substrate 100 exists).Preferably, restraining barrier 110 deposits as ground floor after the conductor rail complanation.Suitable material all can be used in the restraining barrier arbitrarily, comprises the combination of tungsten nitride, tantalum nitride, titanium nitride or these materials.In a preferred embodiment, titanium nitride is used as the restraining barrier.On the restraining barrier is under the situation of titanium nitride, and it can the mode identical with the aforementioned adhesion layer be deposited.
Afterwards, deposition will be patterned as the semiconductor material of post.This semiconductor material can be silicon, germanium, sige alloy or other suitable semiconductor or semiconducting alloy.In order to simplify, this instructions is called silicon with semiconductor material, but is appreciated that those skilled in the art can select other suitable materials arbitrarily with replacing.
In a preferred embodiment, post comprises semiconductor junction diode.Term junction diode used herein refers to have the semiconductor devices of property of non-ohmic conduction, and it has two end electrodes, and by being the p type at an electrode place and being the n type at another electrode place semiconductor material is made.Example comprises: p-n junction diode and n-p type diode, and it has contacted p N-type semiconductor N material and n N-type semiconductor N material, for example Zener diode; With p-i-n type diode, in p-i-n type diode, intrinsic (not mixing) semiconductor material is between p N-type semiconductor N material and n N-type semiconductor N material.
Bottom heavily doped region 112 can be formed by any deposition known in the art and doping method.Silicon can be deposited and be doped afterwards, provides the donor gas of n type dopant atom (for example phosphorus) to carry out in-situ doped but be preferably by flowing into during siliceous deposits.The thickness of heavily doped region 112 is preferably at about 100 dusts between about 800 dusts.
With reference to figure 15b, semiconductor layer 114 that has just deposited and 112 restraining barriers 110 together with lower floor are patterned and are etched with formation post 300.Post 300 should have pitch or spacing (pitch) and the roughly the same width roughly the same with following conductor 200, thereby each post 300 all is formed on the top of conductor 200.Can allow certain misalignment or error.
The photoetching technique that Chen describes in the U. S. application No.10/815312 that is called " PhotomaskFeatures with Chromeless Nonprinting Phase Shifting Window " that submitted on April 1st, 2004 in U. S. application No.10/728436 or the Chen of " the Photomask Features withInterior Nonprinting Window Using Alternating Phase Shifting " by name of submission on December 5th, 2003 can be advantageously used in to be carried out in order to any lithography step of formation according to memory array of the present invention; These two applications are owned by assignee of the present invention, and its content is incorporated herein by reference.
Next, remove the dielectric material on post 300 tops, expose the top of the post 300 that is separated by dielectric material 108, and reserve the surface of general planar.Dielectric technology that this removal is overflowed can be carried out by any technology known in the art, for example CMP or etch-back technics.At CMP or after eat-backing, carry out ion and inject, form heavy doping p type top area 116.P type adulterant is preferably boron or BCl
3This implantation step is finished the formation of diode 111.The structure that produces is shown in Figure 15 b.In the diode that has just formed, bottom heavily doped region 112 is n types, and top-heavy doped region 116 is p types, and obviously polarity can be put upside down.
With reference to figure 15c, anti-fuse dielectric layer 118 is formed on the top of each heavily doped region 116.Anti-fuse 118 is preferably the thickness that formed by any suitable deposition process metal oxide layer at 10 dust to 100 dusts, is for example formed by sputter.If desired, post 300 patterning step can replacedly occur in after the deposition of anti-fuse dielectric layer 118 deposition steps, thereby make layer 118 become the part of post 300.
Next, the dielectric material (not shown) is deposited on the conductor rail and between conductor rail 400.Described dielectric material can be any known electrically insulating material, for example monox, silicon nitride or silicon oxynitride.In a preferred embodiment, monox is used as this dielectric material.
The formation of first memory level has been described.Extra storage level can be formed on this first memory level to form monolithic three dimensional memory array.In certain embodiments, conductor can be shared between each storage level, and promptly top conductor 400 will be as the bottom conductor of next storage level.In other embodiments, form the interlayer dielectric (not shown) on the first memory level in Figure 15 c, this interlayer dielectric surperficial flattened, and the structure of second memory level starts from the interlayer dielectric of this complanation and shared conductor.
Monolithic three dimensional memory array is that a kind of a plurality of storage level is formed on the array on the single substrate, and does not have intermediate substrate, and described substrate for example is a wafer.The layer that forms a storage level is deposited or is grown directly upon on the layer of an existing level or a plurality of grades.On the contrary, the storer that piles up is by formation storage level on the substrate that separates and with bonding structure of each storage level stacked mutually (atop), as the U.S. Patent No. 5,915 of Leedy by name " Three dimensional structuremermory ", described in 167 like that.Described substrate can be before joint attenuate or from storage level, remove, but because storage level initially is formed on the substrate of separation, so sort memory is not real monolithic three dimensional memory array.
Be formed on monolithic three dimensional memory array on the substrate be included on the substrate with first level of first memory at least that highly forms with the first highly different second second memory level of formation highly.In this multistage array, on substrate, can form three, four, eight or the storage level of any amount in fact.
Be used to form the U.S. Patent application No.11/444 that be called " Conductive HardMask to Protect Patterned Features During Trench Etch " that 2006 year May 31 day submit of the interchangeable method of the similar array that uses inlaid structure to form conductor people such as Radigan, be illustrated in 936, this application is transferred to assignee of the present invention and incorporated herein by reference.People's such as Radigan method can be used to form according to array of the present invention replacedly.
Except these contents of having described, the many interchangeable embodiment that has with the memory cell of the resistivity states form stored data states of polycrystalline or crystallite semiconductor materials is feasible and falls within the scope of the present invention.For example, thus the position in the p type in the diode 2 zone 8 and n type zone 4 can be reversed on the bottom that makes p type zone 8 be positioned at vertical diode and make n type zone 4 be positioned at the top of diode 2.
This paper has described the detailed method of making, but any additive method that forms same structure also can be used, and its result also falls within the scope of the present invention.
Figure 16 a has illustrated two kinds of different exemplary memory cell with 16b.Figure 16 a has illustrated that the anti-fuse dielectric layer 14 of metal oxide is positioned at the unit on the diode.Particularly, anti-fuse dielectric layer 14 is positioned on the p type zone 8 of diode.
In Figure 16 b, anti-fuse dielectric layer 14 is positioned under the diode 2.Particularly, metal oxide (Al
2O
3) anti-fuse dielectric layer 14 separates with the n type silicon area 4 of diode by titanium nitride layer 110.Therefore, in MIM (metal-insulator-metal type) structure below the diode in the unit shown in Figure 16 b, Al
2O
3Anti-fuse dielectric layer 14 is between W layer 106 and TiN layer 110.Titanium layer 124 is between the titanium nitride layer 120 on the p of diode 2 type zone and top.
Figure 17 a is the probability graph that the read current of the similar memory cell of silicon dioxide antifuse dielectric layer (circle) that the read current of the memory cell that comprises the anti-fuse dielectric layer of the thick aluminium oxide of 10 dusts (square) shown in Figure 16 a is thick with comprising 16 dusts is compared.These two unit are by+8V pulse program.Seen in from Figure 17 a, under the 2V read-out voltage, the read current with programming unit of the anti-fuse dielectric layer of aluminium oxide is 30 microamperes, and under the 2V read-out voltage, the read current with programming unit of silicon dioxide antifuse dielectric layer is 20 microamperes.Therefore, the use with the anti-fuse dielectric layer of the anti-fuse dielectric layer replacement monox of aluminium oxide makes read current increase 50%.
Figure 17 b shows and comprises the thick hafnia (HfO of 30 dusts shown in Figure 16 a
2) probability graph of read current of memory cell of anti-fuse dielectric layer.Described unit is with+10V pulse program.Seen in from Figure 17 b, under the 2V read-out voltage, the read current of programming unit is 30 microamperes.
Figure 17 c is the probability graph that the read current of the program memory cells shown in Figure 16 a is compared with the read current of the program memory cells shown in Figure 16 b.Though two unit all have the Al of similar thickness
2O
3Anti-fuse, but Al among Figure 16 a
2O
3Structure on the top of the diode that contacts p+ doped silicon regions 8 has demonstrated the forward current more much higher than the structure among Figure 16 b.The anti-fuse dielectric in MIM configuration shown in Figure 16 b causes the read current that reduces, shown in Figure 17 c, and is not preferred in the application of the high read current of expectation.
Do not wishing under the situation about being retrained that the inventor believes can make Al during programming by particular theory
2O
3Al diffusion in the layer also is mixed in the p type silicon area 8 of diode, thereby causes higher forward current.Therefore, the p type zone of diode comprises aluminium, and after the unit was programmed and passes dielectric layer formation electrically conductive links, this Al spread from anti-fuse dielectric layer.Because Al is a p type adulterant in the silicon, therefore, make this p type adulterant will increase the forward current of diode because p type zone 8 has good Ohmic contact because of the higher concentration of p type adulterant wherein with adjacent electrode.This represents Al
2O
3Can be set to contact with the p type zone of diode in the memory cell.Therefore, if p type zone 8 is positioned at the bottom of diode, then Al
2O
3Layer 14 can be positioned under the diode.If p type zone 8 is positioned at the top of diode, then Al
2O
3Layer can be positioned on the diode.On the contrary, owing to the p type adulterant in the p type zone 8 of having diluted diode, from SiO
2In fact the Si that anti-fuse dielectric layer is diffused in the diode can make diode degenerate.Therefore, this is why the anti-fuse of aluminium oxide provides a kind of possible explanation of the read current higher than silicon dioxide antifuse, shown in Figure 17 a.
Hafnium is the p type adulterant in the silicon equally and can works in the mode identical with aluminium, causes the result shown in Figure 17 b probably.Yet, more much lower than the solubleness that in aluminium, has from the solubleness that the dielectric metal except that aluminium of the anti-fuse of metal oxide generally has in silicon.Therefore, if these metals diffuse into silicon from anti-fuse dielectric layer, then they should produce in silicon than p type carrier concentration lower in aluminium.For example, though under 700 ℃, the solubleness that Al has in Si is greater than 1 * 10
20Cm
-3, and at elevated temperatures, estimate solubleness that Hf has in Si less than 1ppm (less than 1 * 10
17Cm
-3).
Detailed description has before only been described some forms in many forms that the present invention can adopt.For this reason, the purpose of this detailed description is to illustrate for example, and unintentionally invention is limited.Have only and appended comprise that what is claimed is of whole equivalents is used to limit the scope of the invention.
Claims (40)
1. non-volatile memory device, it comprises:
At least one memory cell that comprises the anti-fuse dielectric layer of diode and metal oxide; And
Electrically contact first electrode and second electrode of described at least one memory cell;
Wherein, in use, described diode is by switching to the read/write element that second resistivity states is used as described memory cell in response to the biasing that is applied from first resistivity states, and described second resistivity states is different with described first resistivity states.
2. device according to claim 1, the anti-fuse dielectric layer of wherein said diode and described metal oxide is arranged in series between described first electrode and described second electrode.
3. device according to claim 2, the anti-fuse dielectric layer of wherein said metal oxide have and are higher than 3.9 specific inductive capacity.
4. device according to claim 2, the anti-fuse dielectric layer of wherein said metal oxide comprise at least a in hafnia, aluminium oxide, titanium dioxide, lanthana, tantalum oxide, ruthenium-oxide, zirconium Si oxide, aluminium-silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxides of nitrogen, zirconium sieve and silica-sesquioxide, hafnium aluminium-silicon oxide, hafnium aluminium silicon oxides of nitrogen or the zirconium sial oxides of nitrogen or have SiO
2Or SiN
XAt least the combination of one of above-mentioned substance.
5. device according to claim 4, the anti-fuse dielectric layer of wherein said metal oxide comprises hafnia or aluminium oxide.
6. device according to claim 5, the p type zone of the contiguous described diode of the anti-alkene silk of wherein said metal oxide dielectric layer is provided with.
7. device according to claim 6, wherein:
Described diode comprises polysilicon, germanium or the SiGe p-i-n type cylindricality diode with substantial cylindrical shape, and
The p type zone of described diode is included in described unit and is programmed aluminium or the hafnium that the back is come from described anti-fuse dielectric layer diffusion.
8. device according to claim 1, wherein:
Described memory cell comprises the read/writable memory device unit; And
Described diode comprises the p-i-n N-type semiconductor N diode as the read/write element of described memory cell.
9. device according to claim 8, wherein said memory cell comprises rewriteable memory cell.
10. device according to claim 9, wherein:
Apply between described first electrode and described second electrode that forward bias is suitable for forming electrically conductive links and the described diode that is suitable for programming, described electrically conductive links cuts off the anti-fuse dielectric layer of described metal oxide;
The diode of having programmed is suitable for by reverse bias being applied to the not programming state that described diode is set to have high resistivity; And
The described diode that is in the not programming state of described high resistivity is suitable for by forward bias being applied to the programming state that described diode turns back to low-resistivity.
11. device according to claim 1, wherein said device comprise the monolithic three dimensional array of the memory cell that is positioned on the described diode.
12. a non-volatile memory device, it comprises:
A plurality of memory cells; And
Electrically contact first electrode and second electrode of described a plurality of memory cells;
Each memory cell in wherein said a plurality of memory cell comprises diode and the anti-fuse dielectric layer of metal oxide that is disposed in series between described first electrode and described second electrode, and described diode comprises polysilicon, germanium or the SiGe p-i-n type cylindricality diode with substantial cylindrical shape.
13. device according to claim 12, the anti-fuse dielectric layer of wherein said metal oxide comprise at least a in hafnia, aluminium oxide, titanium dioxide, lanthana, tantalum oxide, ruthenium-oxide, zirconium Si oxide, aluminium-silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxides of nitrogen, zirconium sieve and silica-sesquioxide, hafnium aluminium-silicon oxide, hafnium aluminium silicon oxides of nitrogen or the zirconium sial oxides of nitrogen or have SiO
2Or SiN
XAt least the combination of one of above-mentioned substance.
14. device according to claim 13, the anti-fuse dielectric layer of wherein said metal oxide comprises hafnia or aluminium oxide.
15. device according to claim 14, the p type zone of wherein said diode are included in described unit and are programmed aluminium or the hafnium that the back is come from described anti-fuse dielectric layer diffusion.
16. device according to claim 14, wherein each memory cell is providing at least 3.5 * 10 under the 1.5V read-out voltage at least
-5The read current of A.
17. device according to claim 12, the anti-fuse dielectric layer of wherein said metal oxide has the thickness of 10-100 dust.
18. device according to claim 12, wherein:
Described a plurality of memory cell comprises the read/writable memory device unit; And
Described diode in each memory cell in described a plurality of memory cells comprises the p-i-n N-type semiconductor N diode as the read/write element of each memory cell in described a plurality of memory cells.
19. device according to claim 18, wherein, in use, described diode in each memory cell in described a plurality of memory cells is by switching to the read/write element that second resistivity states is used as each memory cell described a plurality of memory cell in response to the biasing that is applied from first resistivity states, described second resistivity states is different with described first resistivity states.
20. device according to claim 19, wherein:
Described a plurality of memory cell comprises rewriteable memory cell;
Apply forward bias and be suitable for forming electrically conductive links and be suitable for being programmed in described diode in each memory cell in described a plurality of memory cell between described first electrode and described second electrode, described electrically conductive links cuts off the anti-fuse dielectric layer of described metal oxide;
The diode of having programmed is suitable for by reverse bias being applied to the not programming state that described diode is set to have high resistivity; And
The described diode that is in the not programming state of described high resistivity is suitable for by forward bias being applied to the programming state that described diode turns back to low-resistivity;
The anti-fuse dielectric layer of described metal oxide is suitable for being cut off to programme described diode by electrically conductive links by apply forward bias between described first electrode and described second electrode;
The diode of having programmed is suitable for by reverse bias being applied to the not programming state that described diode is set to high resistivity, and described back-biased value is greater than predetermined critical voltage value; And
Bian Cheng diode is not suitable for by forward bias being applied to the programming state that described diode is restored to described low-resistivity.
21. a method of making non-volatile memory device, it comprises:
Form first electrode;
Form at least one Nonvolatile memery unit, it comprises diode and the anti-fuse dielectric layer of the metal oxide on described first electrode; And
On described at least one Nonvolatile memery unit, form second electrode;
Wherein, in use, described diode is by switching to the read/write element that second resistivity states is used as described Nonvolatile memery unit in response to the biasing that is applied from first resistivity states, and described second resistivity states is different with described first resistivity states.
22. method according to claim 21, the anti-fuse dielectric layer of wherein said diode and described metal oxide is arranged in series between described first electrode and described second electrode.
23. method according to claim 22, the anti-fuse dielectric layer of wherein said metal oxide comprise at least a in hafnia, aluminium oxide, titanium dioxide, lanthana, tantalum oxide, ruthenium-oxide, zirconium Si oxide, aluminium-silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxides of nitrogen, zirconium sieve and silica-sesquioxide, hafnium aluminium-silicon oxide, hafnium aluminium silicon oxides of nitrogen or the zirconium sial oxides of nitrogen or have SiO
2Or SiN
XAt least the combination of one of above-mentioned substance.
24. method according to claim 23, the anti-fuse dielectric layer of wherein said metal oxide comprises hafnia or aluminium oxide.
25. method according to claim 24, the p type zone of the contiguous described diode of the anti-fuse dielectric layer of wherein said metal oxide is provided with.
26. method according to claim 21 further comprises the anti-fuse dielectric layer of described diode of patterning and described metal oxide, thereby makes described diode and the anti-fuse dielectric layer of described metal oxide form the post with substantial cylindrical shape.
27. method according to claim 21, further comprise forward bias is applied to described diode so that this diode is switched to the programming state with second resistivity from the not programming state with first resistivity, wherein said second resistivity states is lower than described first resistivity states.
28. method according to claim 27, wherein said forward biased applying formed the electrically conductive links that passes the anti-fuse dielectric layer of described metal oxide.
29. method according to claim 28, wherein after described electrically conductive links formed, metal dopant was diffused into the p type zone of the described diode that is close to the anti-fuse dielectric layer setting of described metal oxide from the anti-fuse dielectric layer of described metal oxide.
30. method according to claim 21, the anti-fuse dielectric layer of wherein said metal oxide has the thickness of 10-100 dust.
31. a method of operating non-volatile memory device, it comprises:
At least one memory cell of the anti-fuse dielectric layer of metal oxide that comprises diode and destroyed by electrically conductive links is provided, and wherein said diode switches to the programming state with second low resistivity from the not programming state with first higher electric resistivity; And
Reverse bias is applied to described diode this diode is switched to the not programming state with the 3rd resistivity, and wherein said the 3rd resistivity states is higher than described second resistivity states.
32. method according to claim 31 comprises further forward bias is applied to described diode this diode is switched to the programming state with the 4th resistivity that wherein said the 4th resistivity states is lower than described the 3rd resistivity states.
33. method according to claim 31 further comprises the data mode of the resistivity states of the described diode of sensing as described memory cell.
34. method according to claim 33, wherein the sensing step comprises read-out voltage is applied to described storer, thereby makes described memory cell show at least 3.5 * 10 under the 1.5V read-out voltage at least
-5The read current of A.
35. method according to claim 31, wherein:
Described diode is switched to second programming state in making the factory of described memory cell; And
Apply back-biased step and be after described memory cell leaves the factory that makes this memory cell, carry out by the user of described memory cell.
36. method according to claim 31 further comprises electrically conductive links, it cuts off the anti-fuse dielectric layer of described metal oxide.
37. method according to claim 31, wherein:
The anti-fuse dielectric layer of described diode and described metal oxide is arranged in series between described first electrode and described second electrode; And
The anti-fuse dielectric layer of described metal oxide comprises at least a in hafnia, aluminium oxide, titanium dioxide, lanthana, tantalum oxide, ruthenium-oxide, zirconium Si oxide, aluminium-silicon oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium silicon oxides of nitrogen, zirconium sieve and silica-sesquioxide, hafnium aluminium-silicon oxide, hafnium aluminium silicon oxides of nitrogen or the zirconium sial oxides of nitrogen or has SiO
2Or SiN
XAt least the combination of one of above-mentioned substance.
38. according to the described method of claim 37, the anti-fuse dielectric layer of wherein said metal oxide comprises hafnia or aluminium oxide.
39. according to the described method of claim 38, the p type zone of the contiguous described diode of the anti-fuse dielectric layer of wherein said metal oxide is provided with, thereby in the operating period of described memory cell, aluminium or hafnium are diffused into the p type zone of described diode from the anti-fuse dielectric layer of described metal oxide.
40. method according to claim 31, the anti-fuse dielectric layer of wherein said diode and described metal oxide forms the post with substantial cylindrical shape.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/819,078 | 2007-06-25 | ||
| US11/819,078 US7830697B2 (en) | 2007-06-25 | 2007-06-25 | High forward current diodes for reverse write 3D cell |
| US11/819,079 US7684226B2 (en) | 2007-06-25 | 2007-06-25 | Method of making high forward current diodes for reverse write 3D cell |
| US11/819,079 | 2007-06-25 | ||
| PCT/US2008/007802 WO2009002477A1 (en) | 2007-06-25 | 2008-06-23 | High forward current diodes for reverse write 3d cell and method of making thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101720485A true CN101720485A (en) | 2010-06-02 |
Family
ID=39745268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880021393A Pending CN101720485A (en) | 2007-06-25 | 2008-06-23 | High forward current diodes for reverse write 3d cell and method of making thereof |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP2165336A1 (en) |
| JP (1) | JP2010531543A (en) |
| KR (1) | KR20100056441A (en) |
| CN (1) | CN101720485A (en) |
| TW (1) | TW200917255A (en) |
| WO (1) | WO2009002477A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241248A (en) * | 2013-06-18 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via structure |
| CN110033817A (en) * | 2017-12-20 | 2019-07-19 | 美光科技公司 | The non-contact measurement of memory cell threshold voltage |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8488362B2 (en) | 2009-04-29 | 2013-07-16 | Macronix International Co., Ltd. | Graded metal oxide resistance based semiconductor memory device |
| US8575585B2 (en) * | 2009-07-13 | 2013-11-05 | Hewlett-Packard Development Company, L.P. | Memristive device |
| US8699258B2 (en) | 2011-01-21 | 2014-04-15 | Macronix International Co., Ltd. | Verification algorithm for metal-oxide resistive memory |
| US9117525B2 (en) | 2012-09-12 | 2015-08-25 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069276A1 (en) * | 2005-09-28 | 2007-03-29 | Scheuerlein Roy E | Multi-use memory cell and memory array |
| US20070069217A1 (en) * | 2003-12-03 | 2007-03-29 | Herner S B | P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265049B2 (en) | 2002-12-19 | 2007-09-04 | Sandisk 3D Llc | Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices |
| US20050226067A1 (en) | 2002-12-19 | 2005-10-13 | Matrix Semiconductor, Inc. | Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material |
| US8637366B2 (en) | 2002-12-19 | 2014-01-28 | Sandisk 3D Llc | Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states |
| US7453755B2 (en) | 2005-07-01 | 2008-11-18 | Sandisk 3D Llc | Memory cell with high-K antifuse for reverse bias programming |
-
2008
- 2008-06-23 CN CN200880021393A patent/CN101720485A/en active Pending
- 2008-06-23 JP JP2010513272A patent/JP2010531543A/en active Pending
- 2008-06-23 WO PCT/US2008/007802 patent/WO2009002477A1/en active Application Filing
- 2008-06-23 EP EP08768726A patent/EP2165336A1/en not_active Withdrawn
- 2008-06-23 KR KR1020107001565A patent/KR20100056441A/en not_active Application Discontinuation
- 2008-06-24 TW TW97123542A patent/TW200917255A/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069217A1 (en) * | 2003-12-03 | 2007-03-29 | Herner S B | P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse |
| US20070069276A1 (en) * | 2005-09-28 | 2007-03-29 | Scheuerlein Roy E | Multi-use memory cell and memory array |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241248A (en) * | 2013-06-18 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via structure |
| CN110033817A (en) * | 2017-12-20 | 2019-07-19 | 美光科技公司 | The non-contact measurement of memory cell threshold voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010531543A (en) | 2010-09-24 |
| EP2165336A1 (en) | 2010-03-24 |
| KR20100056441A (en) | 2010-05-27 |
| TW200917255A (en) | 2009-04-16 |
| WO2009002477A1 (en) | 2008-12-31 |
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