CN101719110B - Real-time monitoring method of multipath I2C device in optical communication device - Google Patents
Real-time monitoring method of multipath I2C device in optical communication device Download PDFInfo
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Abstract
The invention discloses a real-time monitoring method of a multipath I2C device in an optical communication device, comprising the following steps of: A10, selecting a I2C device required for operation; A20, configuring a relevant register in a I2C module corresponding to each I2C device inside FPGA; A30, carrying out data exchange with the I2C device by the FPGA according to the state of operational mode of a command register in each I2C module, wherein when the operational mode is read operation, the FPGA reads the data of the I2C device in real time and stores the data in a reception cache register in the corresponding I2C module, and when the operational mode is write operation, the FPGA transmits the data in a transmission cache register in the I2C module to the corresponding I2C device; and A40, obtaining the data updated by the I2C device by the CPU in an interruption or inquiry manner. In the invention, the I2C processing module inside the FPGA realizes data interaction with the multipath I2C device independently, thereby the allocating operation of the system device is greatly simplified.
Description
Technical field
The present invention relates to the real-time monitoring of optic communication device, be specifically related to the method for real-time monitoring of multipath I 2 C device in the optic communication device.
Background technology
I2C bus (INTER IC BUS) is simple two-way two line buses of Philips company exploitation, is used to connect microcontroller and peripheral components thereof.The topmost advantage of I2C bus is its simplicity and validity; All devices that meet the I2C bus all have interface on the sheet; Make between the device directly through the I2C bus communication; Therefore I2C bus occupation space is very little, has reduced the space of circuit board and the quantity of chip pin, has reduced interconnected cost.Another advantage of I2C bus is, it supports many master controls (multimastering), and wherein any device that can send and receive can become main bus, and this design has solved the interface problems that much when the design digital control circuit, run into.Philips provides the IC that surpasses 150 kinds of CMOS and the compatible I2C bus of bipolarity now.
The I2C bus is the universal serial bus that is made up of data line SDA and clock SCL, can transmit and receive data.Between CPU and the controlled IC, carry out two-way transmission between IC and the IC, the I2C bus has three types of signals in transmitting data procedures, and they are respectively: commencing signal, end signal and answer signal.
When commencing signal: SCL was high level, SDA to low transition, began to transmit data by high level.
When end signal: SCL was low level, SDA to the high level saltus step, finished to transmit data by low level.
Answer signal: the IC that receives data sends specific low level pulse to the IC that sends data after receiving the 8bit data, data have been received in expression.CPU waits for that controlled cell sends an answer signal after controlled cell sends a signal, after CPU receives answer signal, make whether continuing to transmit signal judgment according to actual conditions.Break down answer signal if do not receive by being judged as controlled cell.
The I2C bus is before the transmission data begin, and the master control device sends start bit, and notice is carried out to receive from device and prepared; When the transmission ED, the master control device sends position of rest, and notice stops to receive from device.The start bit sequential: when the SCL position is a high position, sda line conversion from high to low; The position of rest sequential: when the SCL position is a high position, sda line conversion from low to high.The last data of SDA must keep stable between the clock high period; Between the SCL low period, just can change; Each byte that outputs on the sda line must be 8, and the byte of each transmission is unrestricted, and each byte must have one to confirm position (claiming response bits ACK again); Produced by primary controller with confirming the corresponding time clock in position, transmitter must drag down sda line during replying.
In optic communication device, very extensive based on the device application of I2C bus, various light delivery modules, clock module, AD sample conversion module, power management module all use the I2C bus to realize the download of configuration and reporting of data.Along with development of Communication Technique, transfer rate is more and more faster, and is also increasingly high to the requirement of real time data acquisition.CPU has taken the ample resources of CPU to the behavior that the device of the various I2C of the having buses of being administered is configured and monitors, and has also reduced the real-time of data interaction simultaneously; And, cause CPU when carrying out exchanges data, to occur a lot of problems such as operation overtime easily with these devices because the temporal characteristics and the method for operating of the I2C device of each producer are had nothing in common with each other.
In addition; Because the I/O mouth resource-constrained of CPU; The I2C number of devices that can directly be linked into CPU is limited, normally through the I/O mouth of FPGA device or CPLD device extension CPU, two kinds of implementation methods is arranged specifically when solving multipath I 2 C device monitoring problem at present: first kind is that all I2C devices are shared a scl line or a sda line; Another root connects independent I/O mouth, successively each device is carried out through the method for Simulation with I 2C sequential then; Second kind is that the scl line of all I2C device is connected independent I/O mouth with sda line, successively each device is operated through the method for Simulation with I 2C sequential then.Along with the transmission apparatus complicacy improves, increasing I2C device is by practical application, because the mode of operation of above-mentioned two kinds of methods is a serial mode, and some problems below having caused:
(1) though expanded the I/O mouth, can monitor more I2C device, CPU can not in time handle certain I2C device, still can only take the method for poll I2C device, and it is too big to delay time.
(2), in optical transmission system; The data variation of I2C device often has randomness and sudden; And the read-write operation of said method all needs CPU initiatively to initiate, and once can only operate an I2C device, the easy like this CPU acquisition device changes of properties information in time that causes; Thereby can't in time make suitable response, this can affect greatly the performance of system.
Summary of the invention
Technical matters to be solved by this invention is to solve in the optic communication device, and CPU can not in time obtain the change information of I2C device performance, thereby can't in time make the problem of suitable response.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopted provides the method for real-time monitoring of multipath I 2 C device in a kind of optic communication device, may further comprise the steps:
A10, selection need the I2C device of operation;
Related register parameter in the inner I2C module corresponding of A20, configuration FPGA with each I2C device, these registers comprise:
Clock is scheduled to scalar register file, is used to select clock frequency;
Command register is used for selection operation mode and module and enables;
Send cache register, be used to store the data that mail to the I2C device;
Status register is used to obtain duty, interrupt identification and the alarm sign of module;
Receive cache register, be used for the data that buffer memory I2C device is sent here;
A30, FPGA carry out exchanges data according to the mode of operation state and the I2C device of command register in each I2C module; When mode of operation was read operation, FPGA read the data of I2C device in real time and is stored in the reception cache register in the corresponding I2C module; When mode of operation was write operation, FPGA exported the data of sending in the cache register in the I2C module to corresponding I2C device;
A40, CPU obtain I2C device data updated through interruption or inquiry mode.
In the said method, steps A 40 may further comprise the steps:
A401, know through the state of hardware interrupts mode or register interrupts zone bit whether the I2C device has Data Update;
If the A402 no datat is upgraded, then change step 301 and continue to have judged whether Data Update; Otherwise, then change 403;
A403, CPU get into interrupt service routine; Forbid the read operation of this I2C module earlier, stop data cached renewal then, read the data in the cache register; CPU accomplishes after data cached the reading; Enable the read operation of I2C module again, restart the timing data collection of FPGA, and remove interruption the I2C device.
Command register and status register carry out communication through byte transmission control unit (TCU) and bit transfer controller respectively; Send cache register and carry out communication through data shift controller and bit transfer controller respectively with the reception cache register, the bit transfer controller is through data line SDA and clock signal SCL and the communication of I2C device.
The present invention, CPU only need accomplish relevant configuration, and read and write according to the data between interrupt identification completion and the FPGA; And need not participate in the data communication with the I2C device, therefore, accomplish the monitoring of multipath I 2 C device with lower cost; Thereby simplified the debugging and the configuration operation of system device greatly, accelerated the speed of research and development, guaranteed professional accuracy of carrying out; Obtain and significantly reduce O&M cost, promote the beneficial effect of user satisfaction.
Description of drawings
Fig. 1 is the real-time monitoring system structural representation of multipath I 2 C device;
Fig. 2 is the inner I2C logic module of a FPGA functional block diagram;
Fig. 3 is the process flow diagram of the method for real-time monitoring of multipath I 2 C device in the optic communication device of the present invention.
Embodiment
The method for real-time monitoring of multipath I 2 C device in the optic communication device provided by the invention; Independently accomplish and the data interaction of multipath I 2 C device by the inner I2C processing module of FPGA; After operation is accomplished, to CPU interrupt identification is provided, software obtains to get into corresponding service routine behind the interrupt identification through the mode of interrupting or inquire about, and accomplishes reading or writing of data; With the monitoring of lower cost completion multipath I 2 C device, thus the operation of simplified system device allotment greatly.
Below in conjunction with accompanying drawing and specific embodiment the present invention is made detailed explanation.
Fig. 1 is the real-time monitoring system structural representation of multipath I 2 C device; Fig. 2 is the inner I2C logic module of a FPGA functional block diagram; Like Fig. 1, shown in Figure 2; CPU is connected with the local bus mode with FPGA, and two lines of the clock SCL of each I2C device and data SDA all are connected with the I/O mouth of FPGA separately, to reach the purpose of carrying out data communication simultaneously through between FPGA and a plurality of I2C device; FPGA gives CPU through cpu local bus with the state reporting of each I2C device, and CPU also can accomplish the configuration to each I2C device through local bus simultaneously.The SCL separately of each I2C device, sda line are linked into the inner logic module of I2C separately of FPGA respectively; Each I2C logic module possesses the byte read-write operation and the multibyte read-write operation function of I2C host mode; And the buffer memory that reads and writes data is provided; Command register and status register carry out communication through byte transmission control unit (TCU) and bit transfer controller respectively; Send cache register and carry out communication through data shift controller and bit transfer controller respectively with the reception cache register, the bit transfer controller is through data line SDA and clock signal SCL and the communication of I2C device.During write operation, the data that earlier by software needs write the I2C device write the transmission metadata cache of FPGA, and the data of being accomplished the I2C device by FPGA again after the enable operation write; During read operation, the data of being accomplished the I2C device earlier by FPGA after the enable operation read, and the deposit data that reads is received in the metadata cache, behind EO, from the reception metadata cache of FPGA, accomplish data by software again and read.When needs operations I2C device, software selections needs one or more devices of operation, the visit device the I2C module of corresponding FPGA inside; Through configuration to register; Control the work of the inner I2C module of the corresponding FPGA of each I2C device, accomplish a plurality of I2C devices are carried out read-write operation simultaneously, read operation is initiated by FPGA; FPGA accomplishes the read operation to the I2C device in some cycles, and only when data change, notifies CPU to Update Information; Write operation is initiated by CPU, and FPGA accomplishes the write operation to the I2C device according to configuration.Whether software is accomplished through interruption or inquiry mode decision operation, and carries out next step operation according to operation types.
Fig. 3 is the process flow diagram of the method for real-time monitoring of multipath I 2 C device in the optic communication device of the present invention, and as shown in Figure 3, this method may further comprise the steps:
A10, selection need the I2C device of operation;
Related register parameter in the inner I2C module corresponding of A20, configuration FPGA with each I2C device, these registers comprise:
Clock is scheduled to scalar register file, is used to select clock frequency;
Command register is used for selection operation mode and module and enables;
Send cache register, be used to store the data that mail to the I2C device;
Status register is used to obtain the duty and the interrupt identification of module;
Receive cache register, be used for the data that buffer memory I2C device is sent here;
A30, I2C module enable; FPGA carries out exchanges data according to the mode of operation state and the I2C device of command register in each I2C module; When mode of operation was read operation, FPGA read the data of I2C device in real time and is stored in the reception cache register in the corresponding I2C module; When mode of operation was write operation, FPGA exported the data of sending in the cache register in the I2C module to corresponding I2C device;
A40, CPU obtain I2C device data updated through interruption or inquiry mode.
Steps A 40 may further comprise the steps:
A401, CPU have judged whether Data Update through interruption or inquiry mode;
If the A402 no datat is upgraded, then change step 401 and continue to have judged whether Data Update; Otherwise, then change 403;
A403, CPU get into interrupt service routine; Forbid the read operation of this I2C module earlier, stop data cached renewal then, read the data in the cache register; CPU accomplishes after data cached the reading; Enable the read operation of I2C module again, restart the timing data collection of FPGA, and remove interruption the I2C device.
The read operation and the write operation of I2C device are specified method provided by the invention respectively through FPGA with CPU below:
(1) CPU read operation.
The first step: select one or more I2C devices that need operation.
Second step: dispose the related register of the inner I2C module of the corresponding FPGA of each I2C device institute, selection clock frequency, address of devices and working length.CPU is through the inner register of operation I2C logic module; Completion is to the monitoring of corresponding I2C device; Promptly select clock frequency, enable, send data through sending the cache register configuration through configuration order register selection operation mode and module through the predetermined scalar register file of configurable clock generator; Obtain module duty and interrupt identification through status register, obtain image data through receiving buffer memory.
The 3rd step: the configuration order register makes mode of operation for reading mode and enable module, and FPGA begins by the operating cycle (10 milliseconds of minimum periods, maximum cycle 60 seconds) of configuration the I2C device to be carried out read operation initiatively.
The 4th step: FPGA sends start signal, address and read-write type information to the I2C device.
The 5th step: FPGA judges whether the answer signal of I2C device is effective low level, if then carry out next step; As be not then to report error reporting and send end signal, stop this time read operation.Through the operational cycle time that has disposed, repeat this step once more, if handshake communication normally continues next procedure, otherwise still repeat this step, whether the order of waiting for software turn-offs and the communicating by letter of this I2C device.
The 6th step: FPGA begins the I2C Data Receiving, and in DRP data reception process, each byte receives and finishes the transmission answer signal of back FPGA to the I2C device, and judges whether the I2C device has received answer signal, if then carry out the reception of next byte; As be not then to report error reporting and send end signal, stop this time read operation, through the operational cycle time that has disposed, once more since the execution of the 4th step.If handshake communication normally continues next procedure, otherwise still carry out since the 4th step, whether the order of waiting for software turn-offs and the communicating by letter of this I2C device.
The 7th step: after accomplishing last byte reception, FPGA is to the transmission answer signal of I2C device.And judge whether the I2C device has received answer signal; If then send end signal to the I2C device; And when the operating cycle regularly arrives, got back to for the 4th step and restart the read operation to the I2C device,, the data that this moment, discovery was read produce look-at-me notice CPU if changing; As be not then to report error reporting and send end signal, stop this time read operation, through the operational cycle time that has disposed, once more since the execution of the 4th step.If handshake communication normally continues next procedure, otherwise still carry out since the 4th step, whether the order of waiting for software turn-offs and the communicating by letter of this I2C device.
The 8th step: all data of I2C device that FPGA reads all are stored in the inner buffer of FPGA, and CPU has judged whether Data Update through interruption or inquiry mode, and data are if upgrade; Software gets into interrupt service routine, forbids the read operation of this I2C module earlier, stops data cached renewal; Prevent that CPU data in reading data cached process from being covered by new image data; CPU accomplishes after data cached the reading, and enables the read operation of I2C module again, restarts the timing data collection of FPGA to the I2C device; Remove at last and interrupt, operation is accomplished.
The CPU write operation:
The first step: select one or more I2C devices that need operation.
Second step: the configuration order register is forbidden the read operation of these I2C devices.
The 3rd step: dispose the inner I2C module of each I2C device corresponding FPGA of institute related register, comprise and select clock frequency, address of devices, working length and configuration operation data.
The 4th step: the configuration operation mode is WriteMode and enables each module that interior each the I2C module of FPGA begins data simultaneously to the I2C device respectively and writes.
The 5th step: FPGA sends start signal, address of devices and read-write type information to the I2C device.
The 6th step: FPGA judges whether the answer signal of I2C device is effective low level, if then get into next step; As not then to report error reporting and send end signal, shut-down operation.CPU can pass through enable module once more according to the error reporting of each I2C module, restarts the write operation to this road I2C device.
The 7th step: in data transmission procedure, FPGA judged whether the answer signal of I2C device is effective low level after each byte was sent and finished, if then carry out the transmission of next byte; As not then to report error reporting and send end signal, shut-down operation.CPU can pass through enable module once more according to the error reporting of each I2C module, restarts the write operation to this road I2C device.
The 8th step: after last byte was sent and finished, FPGA judged whether the answer signal of I2C device is effective low level, if then produce look-at-me notice CPU and send end signal to the I2C device; As not then to report error reporting and send end signal, shut-down operation.CPU can pass through enable module once more according to the error reporting of each I2C module, restarts the write operation to this road I2C device.
The 9th step: software judges through interruption or inquiry mode whether write operation is accomplished, and gets into interrupt service routine, removes and interrupts, the operation completion.
The 4th of above-mentioned read operation went on foot for the 7th step, and the 5th of write operation went on foot for the 8th step and independently accomplished by FPGA, and software does not need to participate in during this, and supports while multidiameter delay execution.
The present invention has following beneficial effect:
(1), can operate a plurality of I2C devices simultaneously, monitor the data variation of I2C device in real time, thereby improved the real-time of data greatly;
(2) real-time characteristic of I2C logic module has reduced the frequency that software is participated in the FPGA, has improved the service efficiency of CPU;
(3), utilize enriching the I/O resource and supporting multiple I/O interface level characteristic of FPGA; The I2C device of different manufacturers (can be different I2C operating rates; Different power supply values) general I2C logic module driver fully be can adopt, maintenance cost and level conversion device cost reduced.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of under enlightenment of the present invention, making, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (2)
1. the method for real-time monitoring of multipath I 2 C device in the optic communication device is characterized in that may further comprise the steps:
A10, selection need the I2C device of operation;
Related register parameter in the inner I2C module corresponding of A20, configuration FPGA with each I2C device, these registers comprise:
Clock is scheduled to scalar register file, is used to select clock frequency;
Command register is used for selection operation mode and module and enables;
Send cache register, be used to store the data that mail to the I2C device;
Status register is used to obtain duty, interrupt identification and the alarm sign of module
Receive cache register, be used for the data that buffer memory I2C device is sent here;
A30, FPGA carry out exchanges data according to the mode of operation state and the I2C device of command register in each I2C module; When mode of operation was read operation, FPGA read the data of I2C device in real time and is stored in the reception cache register in the corresponding I2C module; When mode of operation was write operation, FPGA exported the data of sending in the cache register in the I2C module to corresponding I2C device;
A40, CPU obtain I2C device data updated through interruption or inquiry mode;
Steps A 40 may further comprise the steps:
A401, know through the state of hardware interrupts mode or register interrupts zone bit whether the I2C device has Data Update;
If the A402 no datat is upgraded, then change step 301 and continue to have judged whether Data Update; Otherwise, then change 403;
A403, CPU get into interrupt service routine; Forbid the read operation of this I2C module earlier, stop data cached renewal then, read the data in the cache register; CPU accomplishes after data cached the reading; Enable the read operation of I2C module again, restart the timing data collection of FPGA, and remove interruption the I2C device.
2. the method for real-time monitoring of multipath I 2 C device in the optic communication device as claimed in claim 1; It is characterized in that command register and status register carry out communication through byte transmission control unit (TCU) and bit transfer controller respectively; Send cache register and carry out communication through data shift controller and bit transfer controller respectively with the reception cache register, the bit transfer controller is through data line SDA and clock signal SCL and the communication of I2C device.
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| CN102081570B (en) * | 2011-01-21 | 2016-01-20 | 中兴通讯股份有限公司 | A kind of access method of I2C equipment and device |
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| CN103530249B (en) * | 2012-07-06 | 2016-08-03 | 鸿富锦精密工业（深圳）有限公司 | Inter-integrated circuit bus transmission system and transmission method thereof |
| CN104699526A (en) * | 2013-12-06 | 2015-06-10 | 中兴通讯股份有限公司 | Method and device for reading optical module information by utilizing software |
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| CN104142905B (en) * | 2014-07-31 | 2017-04-19 | 深圳市共进电子股份有限公司 | Method and device for extending inter-integrated circuit (IIC) |
| CN106325893A (en) * | 2015-06-15 | 2017-01-11 | 中兴通讯股份有限公司 | Logic device configuration method and device |
| CN105117319A (en) * | 2015-08-25 | 2015-12-02 | 烽火通信科技股份有限公司 | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA |
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| CN106126362B (en) * | 2016-06-17 | 2019-01-04 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module I2C bus unrest sequential diagnosis method and device |
| CN107423027B (en) * | 2017-07-24 | 2021-11-23 | 杭州迪普科技股份有限公司 | Information reading method, device and system for optical module |
| CN108228520B (en) * | 2018-01-10 | 2020-06-16 | 苏州浪潮智能科技有限公司 | BMC-oriented I2C controller fast transmission method |
| CN108287796A (en) * | 2018-01-24 | 2018-07-17 | 郑州云海信息技术有限公司 | A kind of communication means of control system and programmable logic device |
| CN108399137B (en) * | 2018-03-07 | 2021-07-23 | 广州芯德通信科技股份有限公司 | I2C switching method of PON module based on CPLD |
| CN110362524B (en) * | 2018-04-11 | 2021-04-09 | 杭州海康威视数字技术股份有限公司 | Time sequence signal generation method and device, logic circuit board and storage medium |
| CN109446130B (en) * | 2018-10-29 | 2021-01-26 | 杭州迪普科技股份有限公司 | Method and system for acquiring state information of I/O (input/output) equipment |
| CN110781127A (en) * | 2019-09-25 | 2020-02-11 | 广东宝莱特医用科技股份有限公司 | I2C communication device and method of star topology |
| CN113218050B (en) * | 2021-05-12 | 2023-03-24 | 海信空调有限公司 | Air conditioner and control method |
| CN114172433A (en) * | 2021-12-07 | 2022-03-11 | 湘潭大学 | IPMSM (intelligent power management system) rotating speed curve monitoring method combining lower computer, upper computer and driver control circuit |
| CN114443544B (en) * | 2022-04-02 | 2022-06-28 | 井芯微电子技术(天津)有限公司 | I2C module-based master-slave mode switching method and device |
| CN115100996B (en) * | 2022-07-21 | 2022-12-13 | 北京数字光芯集成电路设计有限公司 | Display configuration circuit, method, micro display panel and electronic device |
| CN115982086B (en) * | 2023-02-14 | 2023-08-01 | 井芯微电子技术(天津)有限公司 | Chip prototype verification board |
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