CN101714543B - Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof - Google Patents
Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof Download PDFInfo
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- CN101714543B CN101714543B CN2009102125528A CN200910212552A CN101714543B CN 101714543 B CN101714543 B CN 101714543B CN 2009102125528 A CN2009102125528 A CN 2009102125528A CN 200910212552 A CN200910212552 A CN 200910212552A CN 101714543 B CN101714543 B CN 101714543B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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Abstract
The invention discloses a ceramic substrate for three-dimensional packaging of a multi-chip system, which comprises laminated ceramic, wherein a first cavity for containing a first chip is formed in a horizontal plane of the laminated ceramic; a cover plate is arranged above the first cavity and seals the first cavity and the first chip; a second cavity for containing a second chip, which is vertical to the first cavity, is arranged on the side wall of the laminated ceramic; and a bonding pad interconnected with the second chip is arranged in the second cavity and is electrically interconnected with the first cavity. The invention can provide hermetic packaging for a multi-chip module and simultaneously can provide vertical surface attaching for chips, thereby realizing vertical attaching of IC chips or MEMS chips, forming a three-dimensional packaged system module with high reliability, and enabling the chips to be capable of detecting variations of physical quantities in X, Y and Z directions.
Description
Technical field
The present invention relates to a kind of ceramic substrate that is used for multi-chip module system three-dimension packaging, also relate to a kind of ceramic substrate that utilizes and carry out the multichip system three-dimension packaging method.
Background technology
Along with the progress of integrated circuit technique and the high speed development of novel electron encapsulation technology, for condition has been created in the raising of electronic product performance, abundant and the reduction perfect, cost of function.Microelectronics Packaging has experienced dual-in-line (DIP) encapsulation, four limits lead-in wires flat (QPF) encapsulation, ball array encapsulation (BGA) and chip size (CSP) encapsulation etc., size is more and more littler, electronic device develops into more complicated system in package circuit (SIP) also by discrete device, integrated circuit, SOC (system on a chip) (SOC).SIP uses little assembling and interconnection technique, can be integrated into various integrated circuits such as cmos circuit, GaAs circuit or opto-electronic device, MEMS device and all kinds of passive component such as resistance, electric capacity, inductance, filter, coupler etc. in the packaging body, thereby can effectively and the most cheaply use various process combination, realize the function of machine system.
The electronics of ceramic material excellence, machinery, thermodynamic property are widely used in fields such as substrate, encapsulation and microwave device, are the important channels of realizing system in package.Ceramic substrate is that ceramic powders is made the accurate and fine and close green band of thickness, on the green band, utilize technologies such as punching or laser drilling, micropore slip casting, accurate conductor paste printing to produce the circuitry needed figure, and passive component and functional circuit can be buried in people's multilayer ceramic substrate, overlap together then, sintering is made three-dimensional high-density circuit at a certain temperature.Ceramic material is except having good high speed, microwave property, and a kind of as the level Hermetic Package material also can be the micro-electromechanical system (MEMS) device level Hermetic Package is provided.
(Micro Electro Mechanical Systems, MEM) technology is whole system to be integrated in realize various physics, chemistry and biological transducer and actuator on the single chip to MEMS (micro electro mechanical system).Wherein operative sensor is that the physical quantity of measuring three directions (X, Y, Z) changes, as three axis accelerometer, magnetic sensor etc.Except on chip, carrying out integrated system (System On Chip, SOC) directly measure outside the physical quantity of three directions, can also be folk prescription with sensor design to the chip of measuring, by carry out three-dimensional encapsulation with the system integration together (System in Package, SIP).The chip Surface Mount technology (SMT) of two dimensional surface is very ripe, but the three-dimensional chip encapsulation is especially carried out chip vertical paster encapsulation and is still new challenge.The present invention just is being based on multilayer ceramic substrate IC or MEMS chip is being carried out the encapsulation of vertical paster realization multi-chip module, can make the physical quantity on the chip measuring vertical direction.
Summary of the invention
The object of the invention is to provide a kind of ceramic substrate that is used for three-dimension packaging, and the metallization of the through hole by multilayer ceramic substrate for the vertical Surface Mount of side chip provides metallized pad, thereby realizes the vertical Surface Mount of chip.
Another object of the present invention is a level Hermetic Package performance of utilizing ceramic substrate for IC and MEMS device provide level Hermetic Package, guarantees the performance of MEMS device, realizes high performance multi-chip module encapsulation.
A further object of the present invention provides a kind of method of utilizing above-mentioned ceramic substrate to carry out three-dimension packaging, by the high-density wiring of multilayer ceramic substrate, planar or carry out the Surface Mount of a plurality of chips in the cavity of plane, realizes the high-density packages of a plurality of chips.
For addressing the above problem, the invention provides a kind of ceramic substrate that is used for the multichip system three-dimension packaging, it comprises multi-layered ceramic, form first cavity in the horizontal plane of described multi-layered ceramic to accommodate first chip, the top of described first cavity is provided with cover plate, described cover plate is with described first cavity and the sealing of first chip, the sidewall of described multi-layered ceramic offers second cavity perpendicular to described first cavity to accommodate second chip, pad, described pad and the described first cavity electric interconnection with described second chip interconnect are set in described second cavity.
The aforesaid ceramic substrate that is used for the multichip system three-dimension packaging is offered through hole on described second cavity.
The aforesaid ceramic substrate that is used for the multichip system three-dimension packaging, described cover plate seals described first cavity and first chip by seal.
The aforesaid ceramic substrate that is used for the multichip system three-dimension packaging, the material of described seal are Au/Sn, Cu/Sn, Ag/Sn, Ni/Sn metal eutectic material, also can be glass paste or organic material.
The aforesaid ceramic substrate that is used for the multichip system three-dimension packaging, described cover plate are glass cover-plate, ceramic cover plate or metal cover board.
A kind of ceramic substrate that utilizes carries out the multichip system three-dimension packaging method, and it may further comprise the steps:
1) curtain coating of ceramic chips, punching and via metal filling, substrate metal wiring
A. the ceramic chips that goes out of curtain coating requires densification, thickness evenly and certain intensity arranged;
B. through hole between the punching cambium layer in the ceramic chips surface, and, be sidewall pad metal reserved location in the punching of the sidewall of ceramic chips; On the ceramic chips of appointment, go out first cavity and second cavity, the through hole that forms is metallized.
C. printing conductive slurry on ceramic chips forms wire structures;
2) ceramic chips is aimed at back lamination, burning, reprocessing and scribing altogether;
A. the laminated ceramic chips after will metallizing carries out accurate contraposition, and compacting is fixing;
B. under specific temperature, multilayer ceramic substrate is burnt till shape altogether;
Metalized is carried out in the position of the ceramic substrate pad after c. will burning altogether;
D. the ceramic substrate of justifying is diced into single ceramic substrate;
3) a plurality of IC of assembling and MEMS chip on ceramic substrate
A. Surface Mount second chip in second cavity of described ceramic substrate makes it to form the Surface Mount of vertical direction;
B. Surface Mount first chip in first cavity of described ceramic substrate forms multi-chip module jointly with second chip in described second cavity;
C. cover plate is covered above described first cavity, form level Hermetic Package.
The aforesaid ceramic substrate that utilizes carries out the multichip system three-dimension packaging method, and in the step 1), the ceramic chips material that is adopted is a low-temperature co-burning ceramic material, also can adopt the High Temperature Co Fired Ceramic material.
The aforesaid ceramic substrate that utilizes carries out the multichip system three-dimension packaging method, and when described ceramic substrate adopted LTCC, interconnecting conductor comprised that through hole adopts slurries such as gold, silver, copper; When described ceramic substrate adopts High Temperature Co Fired Ceramic, adopt tungsten or molybdenum as the interconnecting metal material.
The aforesaid ceramic substrate that utilizes carries out the multichip system three-dimension packaging method, and in step 3), the mounting method of IC or MEMS chip is lead-in wire bonding or flip chip bonding mode.
The aforesaid ceramic substrate that utilizes carries out the multichip system three-dimension packaging method, in step 3), also be included in and transplant soldered ball on the pad of described ceramic substrate bottom surface or be Background Grid array packages (LGA, Land GridArray) form, be used for the encapsulation that whole module is carried out next stage.
The beneficial effect that the present invention reached: the ceramic substrate that is used for the multi-chip module system in package of the present invention, can provide level Hermetic Package for multi-chip module, the vertical Surface Mount of chip can be provided simultaneously.Thereby realize the vertical paster of IC chip or MEMS chip, form the system module of high reliability, three-dimensional encapsulation.
Description of drawings
Fig. 1 is the multi-chip module module diagram that utilizes the multilayer ceramic substrate encapsulation;
Fig. 2 is the ceramic chips curtain coating of multilayer ceramic substrate, punching, metallization and wiring process schematic diagram;
Fig. 3 is sintering and a metalized schematic diagram behind the laminated ceramic chips contraposition lamination;
Fig. 4 is that ceramic substrate is cut apart the scribing schematic diagram;
Fig. 5 is the chip schematic diagram of Surface Mount perpendicular interconnection in ceramic substrate second cavity;
Fig. 6 is the interior lead-in wire bonding mode Surface Mount chip schematic diagram that adopts of first cavity of ceramic substrate;
Fig. 7 is that cover plate and ceramic substrate are welded as module the level Hermetic Package schematic diagram is provided;
Fig. 8 is that base plate bottom is transplanted BGA lead-free solder ball schematic diagram.
Embodiment
For making purpose of the present invention, encapsulating structure and feature thereof are had further understanding, conjunction with figs. is described in detail as follows:
A kind of ceramic substrate that is used for the multichip system three-dimension packaging of the present invention, it comprises multi-layered ceramic 6, form first cavity 2 in the horizontal plane of described multi-layered ceramic 6 to accommodate first chip, the top of described first cavity 2 is provided with cover plate 1, described cover plate 1 is with described first cavity 2 and 4 sealings of first chip, it is characterized in that: the sidewall of described multi-layered ceramic 6 offers second cavity 3 perpendicular to described first cavity 2 to accommodate second chip 9, pad, described pad and the described first cavity electric interconnection with described second chip interconnect are set in described second cavity 3.Described cover plate seals described first cavity 2 and first chip 4 by seal 5.
Be production technology below, the production technology and the set of devices process of assembling of the three-dimension packaging ceramic substrate that is used for multichip system described in conjunction with ceramic substrate.
In Fig. 2, at first carry out the curtain coating of ceramics green ceramic chip, ceramics densification, the thickness that requires curtain coating to go out is even and certain intensity is arranged, and each layer ceramic thickness after burning altogether also will adhere to specification.Through hole 21 between each layer ceramic chips assigned address punching cambium layer, and get areole 31 in the position of the pad of sidewall, be sidewall pad metal reserved location; Go out first cavity 2 and second cavity 3 in the centre of specific green lamella and the position of sidewall.The interlayer through hole and the specific through hole of sidewall that form are metallized, carry out the silver slurry as LTCC and carry out orifice.The printing conductive slurry forms wire structures on ceramic chips, and LTCC adopts the silver wiring.
In Fig. 3, each layer ceramic chips carried out contraposition, accurately laminated together fixing after the contraposition, under specific temperature, multilayer ceramic substrate is burnt till shape altogether, be about 850 ℃ as the LTCC firing temperature.The common burning last handling process of ceramic substrate is that metalized is carried out in the position that will need on the substrate to weld, and carries out the chemical nickel plating gold as pad, seal 5 positions, makes it satisfy the needs of chip routing, flip chip bonding and cover plate for sealing.
Fig. 4 is that the justifying ceramic substrate is scratched into single ceramic substrate, is used for mounting of chip.
Fig. 5 is a chip of assembling vertical Surface Mount at second cavity of ceramic substrate, at first ceramic substrate is vertically placed, the sidewall that needs the Surface Mount chip up, on the sidewall pad, make chip and ceramic substrate form good electric interconnection after substrate refluxed together with chip upside-down mounting after applying scaling powder on the salient point of for example MEMS magnetic sensor chip.Chip can be filled down the end as required and fill glue, and with epoxy resin or silica gel protected chip surface.At this moment, the MEMS Magnetic Sensor can be measured the magnetic field intensity of Z-direction.
Fig. 6 is the ceramic substrate horizontal positioned, the a plurality of chips of Surface Mount in first cavity, one or more chip list are attached in substrate first cavity, utilize the mode and the substrate interconnection of lead-in wire 8 bondings, the chip 4 of Surface Mount can be the optical MEMS device, also can be special integrated chip (ASIC, Application SpecificIntegrated Circuits), form system module after first chip 4 and second chip 9 form electric interconnection.Chip can be filled down the end as required and fill glue, and with epoxy resin or silica gel protected chip surface.
Utilize metal cover board, ceramic cover plate or glass cover-plate to cover on cavity among Fig. 7, form level Hermetic Package.For example, utilize the becket and the becket on the cover plate 1 that prepare on the cavity to form the Sn/Au eutectic weldering, if adopt glass cover-plate to provide window for the optical MEMS device in the cavity.
Fig. 8 can transplant lead-free solder ball 7 on the pad of ceramic substrate bottom surface, whole module may be carried out the encapsulation of next stage.
Below disclose the present invention with preferred embodiment, so it is not in order to restriction the present invention, and all employings are equal to replaces or technical scheme that the equivalent transformation mode is obtained, all drops within protection scope of the present invention.
Claims (10)
1. ceramic substrate that is used for the multichip system three-dimension packaging, it comprises multi-layered ceramic, form first cavity in the horizontal plane of described multi-layered ceramic to accommodate first chip, the top of described first cavity is provided with cover plate, described cover plate is with described first cavity and the sealing of first chip, it is characterized in that: the sidewall of described multi-layered ceramic offers second cavity perpendicular to described first cavity to accommodate second chip, pad, described pad and the described first cavity electric interconnection with described second chip interconnect are set in described second cavity.
2. the ceramic substrate that is used for the multichip system three-dimension packaging according to claim 1 is characterized in that: offer through hole on described second cavity.
3. the ceramic substrate that is used for the multichip system three-dimension packaging according to claim 1 is characterized in that: described cover plate seals described first cavity and first chip by seal.
4. the ceramic substrate that is used for the multichip system three-dimension packaging according to claim 3 is characterized in that: the material of described seal is Au/Sn, Cu/Sn, Ag/Sn, Ni/Sn metal eutectic material, also can be glass paste or organic material.
5. according to each described ceramic substrate that is used for the multichip system three-dimension packaging of claim 1-4, it is characterized in that: described cover plate is glass cover-plate, ceramic cover plate or metal cover board.
6. one kind is utilized ceramic substrate to carry out the multichip system three-dimension packaging method, it is characterized in that: may further comprise the steps:
1) curtain coating of ceramic chips, punching and via metal filling, substrate metal wiring;
A. the ceramic chips that goes out of curtain coating requires densification, thickness evenly and certain intensity arranged;
B. through hole between the punching cambium layer in the ceramic chips surface, and, be sidewall pad metal reserved location in the punching of the sidewall of ceramic chips; On the ceramic chips of appointment, go out first cavity and second cavity, the through hole that forms is metallized;
C. printing conductive slurry on ceramic chips forms wire structures;
2) ceramic chips is aimed at back lamination, burning, reprocessing and scribing altogether;
A. the laminated ceramic chips after will metallizing carries out accurate contraposition, and compacting is fixing;
B. under specific temperature, multilayer ceramic substrate is burnt till shape altogether;
Metalized is carried out in the position of the ceramic substrate pad after c. will burning altogether;
D. the ceramic substrate of justifying is diced into single ceramic substrate;
3) a plurality of IC of assembling and MEMS chip on ceramic substrate;
A. Surface Mount second chip in second cavity of described ceramic substrate makes it to form the Surface Mount of vertical direction;
B. Surface Mount first chip in first cavity of described ceramic substrate forms multi-chip module jointly with second chip in described second cavity;
C. cover plate is covered above described first cavity, form level Hermetic Package.
7. the ceramic substrate that utilizes according to claim 6 carries out the multichip system three-dimension packaging method, it is characterized in that in the step 1) that the ceramic chips material that is adopted is a low-temperature co-burning ceramic material, also can adopt the High Temperature Co Fired Ceramic material.
8. the ceramic substrate that utilizes according to claim 6 carries out the multichip system three-dimension packaging method, it is characterized in that: when described ceramic substrate adopted LTCC, interconnecting conductor comprised that through hole adopts slurries such as gold, silver, copper; When described ceramic substrate adopts High Temperature Co Fired Ceramic, adopt tungsten or molybdenum as the interconnecting metal material.
9. the ceramic substrate that utilizes according to claim 6 carries out the multichip system three-dimension packaging method, it is characterized in that: in step 3), the mounting method of IC or MEMS chip is lead-in wire bonding or flip chip bonding mode.
10. the ceramic substrate that utilizes according to claim 6 carries out the multichip system three-dimension packaging method, it is characterized in that: in step 3), also be included in and transplant soldered ball on the pad of described ceramic substrate bottom surface or be the Background Grid array packages form, be used for the encapsulation that whole module is carried out next stage.
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| CN115332226A (en) * | 2022-10-14 | 2022-11-11 | 北京华封集芯电子有限公司 | Packaging structure based on ceramic intermediate layer and manufacturing method thereof |
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