CN101710938A - Image signal processor, image processing system and image processing method - Google Patents

Abstract

The invention provides an image signal processor, an image processing system and an image processing method; the image signal processor comprises a memory which is provided with a first numerical value pixel storage space; an access module which is used for storing the received image pixel to be processed to the memory and obtaining a first pixel block from the image pixel which is stored in the memory and is to be processed; and an image processing module for carrying out arithmetic processing to the first pixel block and obtaining a target output pixel block. The invention can effectively save the storage space of the image signal processor and reduce the chip cost.

Description

Image-signal processor, image processing system and image processing method

Technical field

The present invention relates to image processing field, relate in particular to a kind of image-signal processor, image processing system and image processing method.

Background technology

Image-signal processor (ISP, Image Signal Processor) is core processing module in the digital camera equipment such as (Digital Camera), image-signal processor carries out a series of calculation process to the image pixel that imageing sensor (Sensor) collects, as noise reduction, color range adjustment, sharpening etc., thereby present to user's better pictures quality.

Traditional image-signal processor is based on to the processing of image pixel that the mode of line scanning (line-scan) realizes, promptly, with the pixel of each two field picture according to from left to right, from top to bottom order sends to each the image processing submodule in the image-signal processor successively, by each image processing submodule the image pixel that receives is carried out calculation process, each image processing submodule can be based on following three kinds of algorithms to the computing of image pixel: 1, based on zero dimension filtering (0-D filter) algorithm of pixel itself; 2, be one-dimensional filtering (1-D filter) algorithm of the block of pixels (block) of 1 * Y based on size, promptly need the same delegation pixel of pending pixel to participate in computing; 3, be two-dimensional filtering (2-D filter) algorithm of the block of pixels of X * Y based on size, promptly need pending pixel pixel all around to participate in computing.For the image processing submodule that adopts the two-dimensional filtering algorithm, owing to need to wait for next line or the pixel arrival of several row down, could satisfy the condition of computing, therefore, this image processing submodule need be provided with a large amount of memory space (line buffer) and come storage pixel.

Be illustrated in figure 1 as in the prior art structural representation based on the image-signal processor of line scanning, image-signal processor among Fig. 1 comprises four image processing submodules, wherein the first image processing submodule, the 3rd image processing submodule and the 4th image processing submodule all adopt the two-dimensional filtering algorithm to the image pixel computing, therefore, all need to be provided with jumbo memory in the first image processing submodule, the 3rd image processing submodule and the 4th image processing submodule and come storage pixel.In image-signal processor, may need a plurality of above-mentioned jumbo memories, the size of this memory can because of the algorithm of each image processing submodule based on the increase of height of block of pixels increase, the also increase of the maximum picture width that can need support because of image-signal processor and increasing, and the algorithm of image processing submodule based on color space also can further increase the expense of memory, this will increase the image-signal processor area of chip greatly, thereby increase the cost of chip.

Summary of the invention

In view of this, the embodiment of the invention provides a kind of image-signal processor, image processing system and image processing method, can effectively save the memory space of image-signal processor, thereby has reduced the cost of chip.

For addressing the above problem, on the one hand, the embodiment of the invention provides a kind of image-signal processor, comprising:

Memory has first numerical value pixel memory space;

Access module, the pending image pixel that is used for receiving is stored in described memory, and obtains first block of pixels from the described pending image pixel of described memory stores;

Image processing module is used for described first block of pixels is carried out calculation process, obtains target output pixel piece;

Described image processing module comprises: at least one image processing submodule;

The size of described first numerical value is determined according to following factor:

During each image processing submodule computing based on the size of second block of pixels;

The size of described target output pixel piece; And

The maximum picture width that described image-signal processor need be supported;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels; And

The size of described target output pixel piece.

The big or small BUF of described first numerical value is: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

Wherein, X _iWhen being i image processing submodule computing based on the height of second block of pixels, N ₁Be total number of described image processing submodule, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

Described access module comprises:

Send submodule, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of pending image are sent to described image processing module.

The embodiment of the invention also provides a kind of image processing system, comprising:

Imageing sensor is used for gathering first block of pixels from image to be collected;

Image-signal processor is used for described first block of pixels is carried out calculation process, obtains target output pixel piece;

Described image-signal processor comprises: at least one image processing submodule;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

Described image processing system also comprises:

Enable control module, be used to control the image processing submodule that current needs participate in calculation process and be in initiate mode.

Described image processing system also comprises:

Configuration module, when being used for according to current each image processing submodule computing that is in initiate mode based on the size of second block of pixels and the size of described target output pixel piece, determine the size of described first block of pixels, and send to described imageing sensor.

Described imageing sensor comprises:

Send submodule, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of described image to be collected are sent to described image-signal processor.

The embodiment of the invention also provides a kind of image processing method, may further comprise the steps:

The pending image pixel that receives is stored in the memory, and described memory has first numerical value pixel memory space;

From the described pending image pixel of described memory stores, obtain first block of pixels;

Described first block of pixels is carried out calculation process, obtain target output pixel piece;

The size of described first numerical value is determined according to following factor:

During each image processing submodule computing based on the size of second block of pixels;

The size of described target output pixel piece; And

The maximum picture width that needs support;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

The big or small BUF of described first numerical value is: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

X wherein _iWhen being i image processing submodule computing based on the height of second block of pixels, N ₁Be total number of described image processing submodule, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

Embodiments of the invention have following beneficial effect:

The pending image pixel that receives is stored in the special memory, and from described memory, obtain one by one block of pixels, the size of this block of pixels by in the image-signal processor during current each image processing submodule computing that is in initiate mode based on the size of block of pixels and the size decision of the target output pixel piece of described image-signal processor, therefore, the block of pixels that each image processing submodule receives promptly is to satisfy the block of pixels of self computing demand, no longer need to be provided with a large amount of memory spaces in each image processing submodule and go to store the pixel that other do not participate in current computing, when relating to the bigger computing of pixel bit wide in the image processing submodule, can save the memory space of image-signal processor effectively, thereby reduce chip cost;

In addition, imageing sensor can be gathered block of pixels by the mode of block scan, it is required that the block of pixels that collects directly satisfies the computing of image-signal processor, at this moment, need not to introduce special memory in the image-signal processor, this has not only greatly saved the memory space of image-signal processor, and, can also in the scope that imageing sensor allows, support the image processing of size arbitrarily.

Because the image processing submodule is handled based on block of pixels, be not subjected to the influence of the maximum picture width that product will support, therefore on existing image processing submodule basis, as long as the design of upgrading memory module and increase storage space, just can support bigger picture size, this has accelerated the construction cycle of new product, has saved the R﹠D costs of product.

Description of drawings

Fig. 1 is based on the structural representation of the image-signal processor of line scanning in the prior art;

Fig. 2 is the structural representation of the image-signal processor of the embodiment of the invention;

Fig. 3 is the Pixel calcualting result schematic diagram of the embodiment of the invention;

Fig. 4 is the another structural representation of the image-signal processor of the embodiment of the invention;

Fig. 5 is the structural representation of the image processing system of the embodiment of the invention;

Fig. 6 is another structural representation of the image processing system of the embodiment of the invention;

Fig. 7 is the another structural representation of the image processing system of the embodiment of the invention;

Fig. 8 is the schematic flow sheet of the image processing method of the embodiment of the invention.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.

Referring to Fig. 2, Fig. 2 is the structural representation of the image-signal processor of the embodiment of the invention, and described image-signal processor comprises: memory 101, access module 102 and image processing module 103;

Described memory 101 has first numerical value pixel memory space;

Described access module 102, the pending image pixel that is used for receiving is stored in described memory 101, and obtains first block of pixels from the described pending image pixel of described memory 101 storages; The input and output of the pixel of the described memory 101 of described access module 102 management, the read-write mechanism of managing the memory space of described memory 101 in other words.

Described image processing module 103 is used for described first block of pixels is carried out calculation process, obtains target output pixel piece.

Described image processing module 103 comprises at least one image processing submodule 1031, and each image processing submodule 1031 is responsible for respectively processing such as image execution noise reduction, color range adjustment, sharpenings; Described image processing submodule 1031 is when being in initiate mode, adopt the default filtering algorithm of self that the block of pixels that receives is carried out calculation process, described default filtering algorithm can be the zero dimension filtering algorithm that based on size is 1 * 1 second block of pixels (promptly based on pixel itself), based on size be 1 * Y second block of pixels the one-dimensional filtering algorithm and be the two-dimensional filtering algorithm of second block of pixels of X * Y based on size, wherein, X is the height (being the line number of pixel in described second block of pixels) of described second block of pixels, and Y is the width (being the columns of pixel in described second block of pixels) of described second block of pixels.

In some cases, the user may not need all images processing sub 1031 in the described image processing module 103 all pending image to be carried out calculation process, for example, suppose to comprise in the image processing module 103 three image processing submodules 1031, the user only needs first image processing submodule 1031 and 1031 pairs of images of the 3rd image processing submodule to carry out calculation process, therefore, can only enable first image processing submodule 1031 and the 3rd image processing submodule 1031 as required, close second image processing submodule 1031; When image is handled, first block of pixels that at first will get access to sends to first image processing submodule 1031, after 1031 pairs of described first block of pixels of described first image processing submodule are carried out calculation process, block of pixels after obtaining handling, and the block of pixels after will handling sends to the 3rd image processing submodule 1031,1031 pairs of block of pixels that receive of described the 3rd image processing submodule are carried out calculation process, then can obtain the target output pixel piece of image-signal processor, because second image processing submodule 1031 is in closed condition, therefore, do not participate in computing this moment.

In addition, because the image processing submodule 1031 that adopts the two-dimensional filtering algorithm is when carrying out calculation process to image pixel, need pending pixel pixel on every side to participate in computing, also just can't handle the borderline pixel of block of pixels, therefore adopt the block of pixels of exporting after image processing submodule 1031 computings of two-dimensional filtering algorithm littler than the block of pixels of this image processing submodule 1031 of input, for example, the size of importing the block of pixels of a certain image processing submodule 1031 is 10 * 10, this image processing submodule 1031 is that 5 * 5 second block of pixels is carried out calculation process based on size, at this moment, owing to can't handle to the borderline pixel of 10 * 10 block of pixels, therefore, the size of the block of pixels of exporting after described image processing submodule 1031 computings only is 6 * 6.Referring to Fig. 3, Fig. 3 is the Pixel calcualting result schematic diagram of the embodiment of the invention, wherein, the A pixel is to be that 5 * 5 block of pixels calculates by the size that is positioned at frame of broken lines, other solid black pixels identical with the A pixel can be that 5 * 5 block of pixels calculates by size all, therefore, this size is that effective output result of 10 * 10 block of pixels only is 6 * 6 solid black block of pixels part for size.

The size of the memory space of above-mentioned memory 101, the size of promptly described first numerical value can be determined according to following factor:

During each image processing submodule 1031 computing based on the size of second block of pixels;

The size of the target output pixel piece of described image-signal processor; And

The maximum picture width that described image-signal processor need be supported;

According to above-mentioned first numerical value determining cause element really, the computing formula that can obtain first numerical value is as follows: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

Wherein, BUF is described first numerical value, X _iWhen being i image processing submodule 1031 computings based on the height of second block of pixels, N ₁Be total number of described image processing submodule 1031, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

In the formula $P=\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1)$ The height (being the line number of pixel in the block of pixels) of representing the block of pixels that described image processing module 103 computings need be imported, the height of the block of pixels that described image processing module 103 computings need be imported during according to each image processing submodule 1031 computing based on the size of second block of pixels and the size of described target output pixel piece determine;

The size of the block of pixels that need import when supposing described image processing module 103 computings is 14 * 20, the height that is the block of pixels that need import of described image processing module 103 computings is 14, the maximum picture width that described image-signal processor need be supported is 960, according to the aforementioned calculation formula, can draw, the memory space of described memory 101 is at least (14-1) * 960, the line number of the pixel of storage is 13 in described memory 101, and when the pixel of the 14th row arrived, 102 of described access modules can obtain size from described memory 101 be 14 * 20 block of pixels; Certainly, the memory space of described memory 101 also can be set to greater than (14-1) * 960.Consider that from the angle of the cost that reduces image-signal processor size that can described memory 101 is set to (14-1) * 960; Yet, the size of described memory 101 is set to (14-1) * 960, may on realizing, algorithm have complicated logic, therefore realize that from algorithm angle is considered easily, size that also can described memory 101 is set to 14 * 960 or bigger, the line number of pixel of storage reaches at 14 o'clock in described memory 101, and 102 of described access modules can obtain size from described memory 101 be 14 * 20 block of pixels; Can select suitable balance point between the two in chip cost and design complexities, the size of described memory 101 is set.

The size of described first block of pixels that above-mentioned access module 102 obtains can be determined according to following factor:

During current each image processing submodule 1031 computing that is in initiate mode based on the size of second block of pixels; And

The size of the target output pixel piece of described image-signal processor.

The computing formula of the size of described first block of pixels is as follows:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

For example definite process of the size of described first block of pixels is elaborated below.

Suppose to comprise in the image-signal processor four image processing submodules, the image processing submodule of current participation computing (promptly being in the image processing submodule of initiate mode) is respectively: the first image processing submodule, the second image processing submodule and the 4th image processing submodule, and the 3rd image processing submodule does not participate in the computing of present image pixel; Wherein, the first image processing submodule adopts the zero dimension filtering algorithm based on pixel itself that image pixel is carried out calculation process, it is that the one-dimensional filtering algorithm of 1 * 7 block of pixels carries out calculation process to image pixel that the second image processing submodule adopts based on size, it is that the two-dimensional filtering algorithm of 5 * 5 block of pixels carries out calculation process to image pixel that the 4th image processing submodule adopts based on size, in addition, the size of supposing the target output pixel piece of described image-signal processor is 8 * 8;

The computational process of the size of first block of pixels is as follows:

The size of the target output pixel piece of described image-signal processor is 8 * 8, the size that is the block of pixels exported after described the 4th image processing submodule computing is 8 * 8, in addition, because it is that 5 * 5 block of pixels is carried out calculation process to image pixel that described the 4th image processing submodule is based on size, then can draw, the size of the block of pixels that need import during described the 4th image processing submodule computing should be 12 * 12;

Because described the 3rd image processing submodule is in closed condition, the input of described the 4th image processing submodule is the output of the described second image processing submodule, therefore, the size of the block of pixels of exporting after the described second image processing submodule computing is 12 * 12, in addition, because it is that 1 * 7 block of pixels is carried out calculation process to image pixel that the described second image processing submodule is based on size, then can draw, the size of the block of pixels that need import during the described second image processing submodule computing should be 12 * 18, and the size of the block of pixels of exporting after the promptly described first image processing submodule computing is 12 * 18;

In addition, because the described first image processing submodule is based on pixel (i.e. 1 * 1 block of pixels) itself image pixel is carried out calculation process, then can draw, the size of the block of pixels that need import during the described first image processing submodule computing should be 12 * 18, thereby the size that can obtain first block of pixels that described access module 102 need obtain is 12 * 18.

According to the aforementioned calculation formula, can obtain the size of first numerical value equally:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1)=8+[(5-1)+(1-1)+(1-1)]=12;$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1)=8+[(5-1)+(7-1)+(1-1)]=18.$

In the prior art based on the image-signal processor of line scanning (line-scan) mode when pending image pixel is transferred to each image processing submodule, be according to from top to bottom, from left to right order sends line by line, if image processing submodule 1031 is the block of pixels of X * Y based on size image pixel is carried out computing, then in this image processing submodule 1031 memory space being set at least is (X-1) * C _MAXThe memory stores pixel, could satisfy the condition of computing, wherein C _MAXBe the maximum picture width that described image-signal processor need be supported, may need a plurality of above-mentioned memories in the described image-signal processor, therefore, can cause the cost of described image-signal processor to increase;

And, different with the image processing mode based on line scanning in the prior art, the embodiment of the invention provides a kind of image processing mode based on block scan (block-scan), the pending image pixel that image-signal processor in the embodiment of the invention will receive is stored in the special memory, and from described memory, obtain one by one block of pixels, the size of this block of pixels by in the image-signal processor during current each image processing submodule computing that is in initiate mode based on the size of block of pixels and the size decision of the target output pixel piece of described image-signal processor, therefore, the block of pixels that each image processing submodule receives promptly is to satisfy the block of pixels of self computing demand, no longer need to be provided with a large amount of memory spaces in each image processing submodule and go to store the pixel that other do not participate in current computing, because the image pixel that imageing sensor collects adopts the less BP of bit wide (Bayer Pattern) form more, therefore, when relating to the bigger computing of pixel bit wide in the image processing submodule, can save the memory space of image-signal processor effectively, thereby reduce chip cost;

When imageing sensor sends to image-signal processor at the image pixel that will collect, can send the frame synchronizing signal of pending image and the line synchronizing signal of pixel to image-signal processor simultaneously; Access module 102 in the image-signal processor is when obtaining first block of pixels, also need to generate and the corresponding block sync signal of described first block of pixels, the frame synchronizing signal that will work as described first block of pixels, block sync signal and pending image simultaneously sends to image processing module 103.

Referring to Fig. 4, be illustrated in figure 4 as a structural representation again of the image-signal processor of the embodiment of the invention, on the basis of embodiment shown in Figure 2, described access module 102 comprises:

Send submodule 1021, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of pending image are sent to described image processing module 103.

After each image processing submodule 1031 in the image processing module 103 received block sync signal and frame synchronizing signal, an image processing submodule 1031 was transmitted described block sync signal and frame synchronizing signal backward.

In some cases, described image processing submodule 1031 is when carrying out calculation process to block of pixels, the positional information that also may need this block of pixels, for example, be used for carrying out the image processing submodule of eliminating halation, when image is removed the processing of halation, just need obtain the absolute coordinate information of block of pixels in entire image, could carry out calculation process.At this moment, described image processing submodule 1031 can be according to block sync signal that receives and frame synchronizing signal, the positional information of calculating pixel piece.Concrete, described image processing submodule 1031 can calculate the positional information of current pending block of pixels according to the block sync signal and the frame synchronizing signal of the size of pending image, object pixel block size, current pending block of pixels.

Above-mentioned access module 102 is responsible for receiving the image pixel that imageing sensor (image collecting device) sends, the order of described imageing sensor images acquired pixel is: with the pixel in each two field picture according to from left to right, from top to bottom order gathers line by line, and the image pixel that collects sent to described image-signal processor according to above-mentioned acquisition order, therefore, described image-signal processor also be according to from left to right, from top to bottom order receives pending image pixel line by line, promptly described access module 102 is to receive pending image pixel line by line; Described access module 102 is stored in the image pixel that receives in the described memory 101, pixel in described memory 101 satisfies obtaining of described first block of pixels when requiring, from described memory 101, obtain described first block of pixels and send to described image processing module 103, described access module 102 obtains described first block of pixels from described memory 101 order is: obtain described first block of pixels successively according to order from left to right, whenever obtain described first block of pixels, then to left one row, obtain next described first block of pixels, after current line finishes, translation delegation continues to obtain described first block of pixels downwards.

In addition, when described access module 102 obtains described first block of pixels, if comprise the pixel on the image boundary in described first block of pixels, when then obtaining described first block of pixels, need to consider the expansion of boundary pixel, generally, the extended method of boundary pixel is following two kinds, a kind of method is to duplicate borderline pixel as the pixel outside the border, and a kind of mode is along pixel boundary to be overturn in the mirror image mode with interior pixel in the border to copy to beyond the border.

Described access module 102 whenever sends described first block of pixels, then needs to do the carrying of a memory-mapped or data, promptly collects the pending image pixel that available memory space is used for newly receiving and stores described memory 101 into.

Last image processing submodule with above-mentioned image-signal processor is used for image is carried out JPEG (Joint Photographic Experts Group below, JPEG (joint photographic experts group)) encoding compression is an example, and the image-signal processor of the embodiment of the invention is described.

Generally, the image of imageing sensor output is the image of BP form, and each pixel has only the one-component in the R/G/B component in the image of BP form, promptly only adopts a sampled value to represent current pixel, and the pixel bit wide is less; And, the JPEG encoding compression is based on the image of yuv format, the bit wide of the pixel in the image of yuv format is more much bigger than the bit wide of the pixel in the image of BP form, for example, corresponding 4 the Y components of per 4 pixels, 2 U components and 2 V components in the image of YUV422 form, the bit wide of pixel are 2 times of image of BP number; In addition, during the JPEG encoding compression, need be 8 * 8 block of pixels based on size;

Can carry out the JPEG encoding compression in order to guarantee last image processing submodule, under line-scan mode, need in this image processing submodule, memory be set, to store the pixel of 8 row, thereby can be divided into size and be 8 * 8 block of pixels, the data of storing in this memory are the bigger yuv format of pixel bit wide, therefore need the capacity setting of memory bigger;

And, the image-signal processor of the embodiment of the invention, a memory of data that is used to store the BP form only need be set at first get final product, the size of memory during according to each the image processing submodule computing in the image-signal processor based on the size of second block of pixels and the size of the target output pixel piece of described image-signal processor determine; When the columns of the maximum image of handling at needs was big more, with respect to image-signal processor of the prior art, the memory space that the image-signal processor in the embodiment of the invention is saved was just many more.

The image-signal processor that provides by the foregoing description, the pending image pixel that receives is stored in the special memory, and from described memory, obtain one by one block of pixels, the size of this block of pixels by in the image-signal processor during current each image processing submodule computing that is in initiate mode based on the size of block of pixels and the size decision of the target output pixel piece of described image-signal processor, therefore, the block of pixels that each image processing submodule receives promptly is to satisfy the block of pixels of self computing demand, no longer need to be provided with a large amount of memory spaces in each image processing submodule and go to store the pixel that other do not participate in current computing, when relating to the bigger computing of pixel bit wide in the image processing submodule, can save the memory space of image-signal processor effectively, thereby reduce chip cost; In addition, because the image processing submodule is handled based on block of pixels, be not subjected to the influence of the maximum picture width that product will support, therefore on existing image processing submodule basis, as long as the design of upgrading memory module and increase storage space, just can support bigger picture size, this has accelerated the construction cycle of new product, has saved the R﹠D costs of product.

In the foregoing description, imageing sensor (being image collecting device) be according to from left to right, from top to bottom order images acquired pixel line by line, and send to image-signal processor successively, in the described image-signal processor, one memory need be set, the image pixel that receives is stored; Certainly, described imageing sensor also can be according to the mode images acquired pixel of block scan, directly will satisfy the block of pixels that described visual information processor calculation process requires, send to described image-signal processor, at this moment, the memory 101 in the foregoing description also can save, thereby, further reduce the memory space of image-signal processor, saved chip cost.

Referring to Fig. 5, be illustrated in figure 5 as the structural representation of the image processing system of the embodiment of the invention, described image processing system comprises:

Imageing sensor 200 is used for gathering first block of pixels from image to be collected;

Image-signal processor 100 is used for described first block of pixels is carried out calculation process, obtains target output pixel piece;

Described image-signal processor 100 comprises: at least one image processing submodule 1031;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule 1031 computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

The computing formula of the size of first block of pixels is:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

The method of above-mentioned imageing sensor 200 images acquired is specially: according to the described positional information of image pixel in entire image to be collected, gather described first block of pixels successively according to order from left to right, block of pixels of every collection, then to the columns of right translation target pixel block width, continue to gather next block of pixels, until the capable end of current pixel, then the line number of downward translation object pixel tile height continues to gather block of pixels.

The image processing system that provides by the foregoing description, can gather block of pixels by the mode of block scan, it is required that the block of pixels that collects directly satisfies the computing of image-signal processor, at this moment, not only greatly saved the memory space of image-signal processor, and, with regard to image-signal processor, can also in the scope that imageing sensor allows, support the image processing of size arbitrarily.

Certainly, also need to have the device that the described image processing submodule 1031 of control is opened or closed in the described image processing system, referring to Fig. 6, described image processing system also comprises:

Enable control module 300, be used to control the image processing submodule 1031 that current needs participate in calculation process and be in initiate mode.

In addition, the size of described first block of pixels that described imageing sensor 200 need obtain is that the size of the block of pixels of needs input during according to described image-signal processor 100 current computings is determined, the size of the block of pixels that described image-signal processor 100 current computings need be exported then be during according to current each image processing submodule 1031 computing that is in initiate mode based on the size of second block of pixels and the size of the target output pixel piece of described image-signal processor 100 determine, therefore, described image processing system also comprises:

Configuration module 400, when being used for according to current each image processing submodule 1031 computing that is in initiate mode based on the size of second block of pixels and the size of the target output pixel piece of described image-signal processor, determine the size of described first block of pixels, and send to described imageing sensor 200.

Generally, above-mentionedly enable the firmware firmware that control module 300 and configuration module 400 all are arranged in image processing system) on.

In addition, described imageing sensor 200 also needs to generate the block sync signal of described first block of pixels when obtaining described first block of pixels, and the frame synchronizing signal of image to be collected, and send to image-signal processor 100, as shown in Figure 7, described imageing sensor 200 comprises:

Send submodule 201, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of described image to be collected are sent to described image-signal processor.

Described imageing sensor 200 whenever obtains one first block of pixels, just generates a block sync signal; Whenever finish the collection of a two field picture, just generate a frame synchronizing signal.

After each image processing submodule 1031 in the image processing module 103 received block sync signal and frame synchronizing signal, an image processing submodule 1031 was transmitted described block sync signal and frame synchronizing signal backward.

In some cases, image processing submodule 1031 in the described image-signal processor is when carrying out calculation process to block of pixels, perhaps when target pixel block is recombinated, the positional information that needs block of pixels, at this moment, described image processing submodule 1031 can be according to block sync signal that receives and frame synchronizing signal, the positional information of calculating pixel piece.Concrete, described image processing submodule 1031 is according to the block sync signal of the size of pending image, the current pending block of pixels that receives, and the frame synchronizing signal that receives, calculate the positional information of current pending block of pixels in whole pending image.The size of described pending image is provided by described configuration module 400.

Referring to Fig. 8, Fig. 8 is the schematic flow sheet of the image processing method of the embodiment of the invention, said method comprising the steps of:

Step 801 is stored in the pending image pixel that receives in the memory, and described memory has first numerical value pixel memory space;

The size of described first numerical value is determined according to following factor:

During each image processing submodule computing based on the size of second block of pixels;

The size of described target output pixel piece; And

The maximum picture width that needs support;

Step 802 is obtained first block of pixels from the described pending image pixel of described memory stores;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

Step 803 is carried out calculation process to described first block of pixels, obtains target output pixel piece;

The big or small BUF of described first numerical value is: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

X wherein _iWhen being i image processing submodule computing based on the height of second block of pixels, N ₁Be total number of described image processing submodule, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

The computing formula of the size of described first block of pixels is:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

The method that provides by the foregoing description, from the pending image pixel that receives, obtain block of pixels one by one, the size of this block of pixels by in the image-signal processor during current each image processing submodule computing that is in initiate mode based on the size of block of pixels and the size decision of the target output pixel piece of described image-signal processor, therefore, the block of pixels that each image processing submodule receives promptly is to satisfy the block of pixels of self computing demand, no longer need to be provided with a large amount of memory spaces in each image processing submodule and go to store the pixel that other do not participate in current computing, saved the memory space of image-signal processor effectively.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (12)

1. an image-signal processor is characterized in that, comprising:

Memory has first numerical value pixel memory space;

Access module, the pending image pixel that is used for receiving is stored in described memory, and obtains first block of pixels from the described pending image pixel of described memory stores;

Image processing module is used for described first block of pixels is carried out calculation process, obtains target output pixel piece;

Described image processing module comprises: at least one image processing submodule;

The size of described first numerical value is determined according to following factor:

During each image processing submodule computing based on the size of second block of pixels;

The size of described target output pixel piece; And

The maximum picture width that described image-signal processor need be supported;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels; And

The size of described target output pixel piece.

2. image-signal processor according to claim 1 is characterized in that, the big or small BUF of described first numerical value is: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

Wherein, X _iWhen being i image processing submodule computing based on the height of second block of pixels, N ₁Be total number of described image processing submodule, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

3. image-signal processor according to claim 1 is characterized in that:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

4. image-signal processor according to claim 1 is characterized in that, described access module comprises:

Send submodule, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of pending image are sent to described image processing module.

5. an image processing system is characterized in that, comprising:

Imageing sensor is used for gathering first block of pixels from image to be collected;

Image-signal processor is used for described first block of pixels is carried out calculation process, obtains target output pixel piece;

Described image-signal processor comprises: at least one image processing submodule;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

6. image processing system according to claim 5 is characterized in that:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

7. image processing system according to claim 5 is characterized in that, also comprises:

Enable control module, be used to control the image processing submodule that current needs participate in calculation process and be in initiate mode.

8. image processing system according to claim 5 is characterized in that, also comprises:

Configuration module, when being used for according to current each image processing submodule computing that is in initiate mode based on the size of second block of pixels and the size of described target output pixel piece, determine the size of described first block of pixels, and send to described imageing sensor.

9. image processing system according to claim 5 is characterized in that, described imageing sensor comprises:

Send submodule, be used for the block sync signal of described first block of pixels, described first block of pixels and the frame synchronizing signal of described image to be collected are sent to described image-signal processor.

10. an image processing method is characterized in that, may further comprise the steps:

The pending image pixel that receives is stored in the memory, and described memory has first numerical value pixel memory space;

From the described pending image pixel of described memory stores, obtain first block of pixels;

Described first block of pixels is carried out calculation process, obtain target output pixel piece;

The size of described first numerical value is determined according to following factor:

During each image processing submodule computing based on the size of second block of pixels;

The size of described target output pixel piece; And

The maximum picture width that needs support;

The size of described first block of pixels is determined according to following factor:

During current each image processing submodule computing that is in initiate mode based on the size of second block of pixels;

The size of described target output pixel piece.

11. image processing method according to claim 10 is characterized in that, the big or small BUF of described first numerical value is: $\mathrm{BUF}\≥[(P+\underset{i=1}{\overset{N_1}{\mathrm{\Σ}}}(X_i-1))-1]\×C_{\mathrm{MAX}};$

X wherein _iWhen being i image processing submodule computing based on the height of second block of pixels, N ₁Be total number of described image processing submodule, P is the height of described target output pixel piece, C _MAXThe maximum picture width that need support for described image-signal processor.

12. image processing method according to claim 10 is characterized in that:

The height R of described first block of pixels is: $R=P+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(X_i-1);$

The width C of described first block of pixels is: $C=Q+\underset{i=1}{\overset{N_2}{\mathrm{\Σ}}}(Y_i-1);$

Wherein, P and Q are respectively the height and the width of described target output pixel piece, X _iAnd Y _iWhen being respectively current i image processing submodule computing that is in initiate mode based on the height and the width of second block of pixels, N ₂Be the current total number that is in the image processing submodule of initiate mode.

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