CN101699776A - Down link synchronization method applied to CDMA20001x system - Google Patents

Down link synchronization method applied to CDMA20001x system Download PDF

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CN101699776A
CN101699776A CN200910193793A CN200910193793A CN101699776A CN 101699776 A CN101699776 A CN 101699776A CN 200910193793 A CN200910193793 A CN 200910193793A CN 200910193793 A CN200910193793 A CN 200910193793A CN 101699776 A CN101699776 A CN 101699776A
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down link
mould value
received signal
chip
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高原
许鸿辉
施英
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Comba Network Systems Co Ltd
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Comba Telecom Systems China Ltd
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Abstract

The invention discloses a down link synchronization method applied to a CDMA20001x system, comprising the following steps: buffering receiving signals rI (s+k) and rQ (s+k) with the s moment as a start and the total length being M chips and dividing the receiving signals into P segments, each of which has length of X chips; carrying out accumulation after multiplying the data on the first segment of the receiving signals by the conjugate point by point on the first segment of a corresponding local PN sequence, and obtaining a P point accumulation result; padding zeros at the end of the P point accumulation result until N point and then carrying out FFT to obtain an N point transformation result; computing the squares of the moduli of the N point transformation result and searching the maximum of the squares of the moduli of the N point; and comparing the maximum of the squares of the moduli with a preset threshold, if the maximum exceeds the threshold, successfully capturing the PN phase, or enabling s to be equal to s+1 and returning to the initial step. The method can realize reliable down link synchronization when the receiving signals have larger frequency offsets and Ec/N0 of the pilot channel is lower.

Description

A kind of down link synchronisation method that is applied to the CDMA20001x system
Technical field
The present invention relates to the method for synchronous of spread spectrum communication system, be specifically related to the down-going synchronous implementation method of a kind of CDMA20001x of being applied to system.
Background technology
In the cellular wireless mobile communication field, cdma system has many exclusive technical advantages, and it can better resist channel disturbance and increase the confidentiality of information, becomes the key technology of 3G physical layer.For Resistant DS Spread Spectrum System, for obtaining spreading code phase place that the ideal system performance just requires receiving-transmitting sides (error must in the magnitude of part chip) fully synchronously, receiver must be known the instantaneous phase of transmitter spreading code accurately and rapidly and the spreading code that this locality generates is aimed at it, just can carry out demodulation accurately.
In the CDMA20001x system, each base station all will send special pilot channel so that the travelling carriage in this sub-district carries out synchronously, pilot channel is directly repeated to constitute by pseudo noise (PN) sequence period of I, Q two-way, travelling carriage utilizes this pilot channel, carry out the PN sequence phase capturing, it is synchronous to obtain descending timing.Downlink pilot frequency channel transmitting terminal baseband model as shown in Figure 1.
The proper polynomial that the CDMA20001x system is used for the PN sequence on I road and Q road is respectively:
P I(x)=x 15+x 13+x 9+x 8+x 7+x 5+1
P Q(x)=x 15+x 12+x 11+x 10+x 6+x 5+x 4+x 3+1
Corresponding generator polynomial is:
i ( n ) = i ( n - 15 ) ⊕ i ( n - 10 ) ⊕ i ( n - 8 ) ⊕ i ( n - 7 ) ⊕ i ( n - 6 ) ⊕ i ( n - 2 )
q ( n ) = q ( n - 15 ) ⊕ q ( n - 12 ) ⊕ q ( n - 11 ) ⊕ q ( n - 10 ) ⊕ q ( n - 9 )
⊕ q ( n - 5 ) ⊕ q ( n - 4 ) ⊕ q ( n - 3 )
Symbol
Figure G2009101937932D0000014
Expression mould 2 adds computing.The generation of PN sequence generally uses linear feedback shift register (LFSR) to realize that the PN sequence LFSR structure chart on I road and Q road as shown in Figure 2.
The m sequence period length of 15 grades of shift register generations is 2 15-1, insert one 0 in continuous 14 0 backs, as the PN sequence start position, carry out then unipolarity to ambipolar mapping (bit 0 is mapped as+1; Bit 1 is mapped as-1) cycle of obtaining is 2 15The PN sequence of (32768 chips), the periodicity emphasis that joins end to end recurrence is sent.
The descrambling flow process of receiver as shown in Figure 3.Suppose that receiver is the received signal of an initial buffer memory M chip lengths with a certain moment s, the real part and the imaginary part of establishing this signal are respectively r I(s+k), r Q(s+k), k=0 wherein, 1,2 ... M-1 utilizes the local plural PN sequence P that generates I(k), P Q(k) descrambling to received signal, the I behind the descrambling, Q road signal are:
y I(s+k)=r I(s+k))·P I(k)+r Q(s+k)·P Q(k);
y Q(s+k)=r Q(s+k)·P I(k)-r I(s+k)·P Q(k);k=0,1,2…M-1
Existing method for synchronous generally is that received signal starting point s is slided on whole PN sequence period, to each possible synchronization point s, with the M point scrambling sequence y of correspondence I(s+k), y Q(s+k) (k=0,1,2 ... M-1) add up, be designated as θ (s):
θ ( s ) = Σ k = 0 M - 1 y I ( s + k ) + j · Σ k = 0 M - 1 y Q ( s + k ) .
Again accumulation result is asked for mould value square, then in a PN sequence period, is made | θ (s) | 2Maximum moment s is received signal PN sequence phase synchronization point
Figure G2009101937932D0000022
s ^ = arg max s | θ ( s ) | 2 .
In the real system, the E of received signal c/ N 0(E cBe the average chip energy of received signal, N 0Be noise power spectral density) may be very low, and the pilot channel that is used for the PN sequence capturing has only accounted for the part of total transmit signal power; In addition, may there be bigger radio frequency crystal oscillator frequency deviation in travelling carriage or be in the vehicle-mounted high-speed mobile environment.These all will increase the difficulty of PN sequence capturing.
For the conventional synchronization method, at low E c/ N 0Situation under, need to increase correlation length (promptly increasing M above) in the hope of improving acquisition performance; But exist at receiving terminal under the situation of frequency shift (FS), the long more frequency shift (FS) of correlation length is also big more to the influence of catching the result.Therefore, the conventional synchronization method can't be taken into account the performance of two aspects simultaneously.
Summary of the invention
In order to overcome the existing in prior technology defective, purpose of the present invention is exactly the down link synchronisation method of a kind of CDMA20001x of being applied to of proposition system.For conventional method, the present invention can exist the bigger frequency shift (FS) and the E of pilot channel in received signal c/ N 0When low, realize that reliable down is synchronous; And can be according to the channel circumstance of reality, configuration parameter flexibly, better utilization hardware resource.
Purpose of the present invention is achieved through the following technical solutions: the down link synchronisation method of a kind of CDMA20001x of being applied to system may further comprise the steps:
Step 1, buffer memory are the received signal r of M chip for initial total length with s constantly I(s+k), r Q(s+k), and with it be divided into the P section, every segment length X chip, M=PX;
Step 2, make l=0, with received signal l segment data with add up after the conjugation pointwise of corresponding local PN sequence l section is multiplied each other, obtain 1 accumulation result;
Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result;
Step 4, with the P point accumulation result end zero padding of step 2, step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, N is 2 integral number power;
Step 5, N point transformation result is asked for mould value square respectively;
The maximum of step 6, search N point mould value square;
Step 7, with mould value square maximum and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place; Otherwise s=s+1, chip of received signal original position time-delay returns step 1.
In above-mentioned method for synchronous, step 6 also writes down the position that mould value square maximum occurs in N point mould value square
Figure G2009101937932D0000031
After described step 7 is successfully caught the PN phase place, also carry out:
Step 8, according to mould value square maximum position
Figure G2009101937932D0000032
To received signal and the frequency offseting value that exists between the local PN sequence
Figure G2009101937932D0000033
Carry out following estimation:
When
Figure G2009101937932D0000034
The time,
Figure G2009101937932D0000035
When
Figure G2009101937932D0000036
The time,
Figure G2009101937932D0000037
T wherein cChip period for single-time sampling.
Compare with existing traditional catching method, advantage of the present invention and beneficial effect are:
1) the segmentation correlated results is carried out the FFT conversion, and square maximizing as a result of search N point mould value, compare with default thresholding, can judge whether this phase place is the locking phase of PN sequence; Thereby the total correlation length M no longer is subjected to the restriction of frequency shift (FS).Through actual verification, this method can exist in received signal ± frequency shift (FS) in the 10kHz scope and the E of pilot channel c/ N 0During 〉=-27dB, realize that reliable down is synchronous.
2) the present invention is adapted at realizing on the programming device.In programming device, use matched filter to realize the relevant accumulating operation of segmentation of received signal and local PN sequence.
3) if the N value is too little, the peak value during the PN Phase synchronization has bigger shake (being called the grid effect), influences acquisition performance; The present invention will be to P accumulation result (θ before the FFT conversion 0(s), θ 1(s) ..., θ P-1(s)) the end zero padding increases the FFT points N to N point (N 〉=P, and be 2 integral number power), further improves acquisition performance and frequency offset estimation accuracy.
4) when successfully catching the PN phase place, can carry out the estimation of frequency offseting value.
Description of drawings
Fig. 1 is the schematic diagram of CDMA20001x system transmitting terminal baseband pilot signal;
Fig. 2 generates the schematic diagram of I, Q two-way PN sequence for the CDMA20001x system;
Fig. 3 carries out the schematic diagram of descrambling to baseband signal for the multiple PN sequence of receiving terminal utilization;
Fig. 4 carries out the schematic diagram of related operation to received signal for the present invention;
Fig. 5 is the schematic diagram of realization flow of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.
Embodiment
The present invention can realize on programming device, the process of carrying out related operation to received signal as shown in Figure 4, detailed process is as shown in Figure 5; Specifically may further comprise the steps:
Step 1, buffer memory are the received signal r of M chip for initial total length with s constantly I(s+k), r Q(s+k) (k=0,1,2 ..., M-1), and it is divided into the P section, every segment length X chip, M=PX.
Step 2, make l=0, with received signal l segment data with add up after the conjugation pointwise of corresponding local PN sequence l section is multiplied each other, obtain 1 accumulation result:
θ l ( s ) = Σ k = 0 X - 1 [ r I ( s + X · l + k ) · P I ( X · l + k ) + r Q ( s + X · l + k ) · P Q ( X · l + k ) ]
+ j · Σ k = 0 X - 1 [ r Q ( s + X · l + k ) · P I ( X · l + k ) + r I ( s + X · l + k ) · P Q ( X · l + k ) ] ;
Above-mentioned adding up can be realized by matched filter in programming device.
Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result.
Step 4, with the P point accumulation result (θ of step 2, step 3 gained 0(s), θ 1(s) ..., θ P-1(s)) the end zero padding is carried out the FFT conversion to N point (P<N, N are 2 integral number power), obtains N point transformation Z as a result FFT(k) | s(k=0,1 ..., N-1).
Wherein, the FFT conversion can be used special-purpose FFT chip or use Nlog in programming device 2N complex multiplier and 2Nlog 2N complex adder realizes.
Step 5, with N point transformation Z as a result FFT(k) | sAsk for mould value square respectively, the mould value of being asked for square is designated as | Z FFT(k) | s| 2(k=0,1 ..., N-1).Wherein, asking for of mould value square can be by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass realization.
Step 6, search N point mould value square | Z FFT| s| 2Maximum, be designated as metric (s), and the position of record mould value square maximum appearance in N point mould value square
metric ( s ) = | Z DFT ( k ^ ) | s | 2 ; k ^ = arg max k ( | Z DFT ( k ) | s | 2 ) , k = 0,1 · · · N - 1 ;
Wherein square peaked search of mould value adopts N-1 comparator to realize.
Step 7, with mould value square maximum metric (s) and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place, forwards step 8 to; Otherwise s=s+1, chip of received signal original position time-delay returns step 1.Wherein mould value square maximum and default thresholding relatively realizes by 1 comparator.
Step 8, according to mould value square maximum position
Figure G2009101937932D0000054
Figure G2009101937932D0000055
To received signal and the frequency offseting value that exists between the local PN sequence
Figure G2009101937932D0000056
Carry out following estimation:
When k ^ < N 2 The time, f ^ 0 = k ^ N &CenterDot; X &CenterDot; T c ; When N 2 &le; k ^ &le; N - 1 The time, f ^ 0 = - N - k ^ N &CenterDot; X &CenterDot; T c .
T wherein cBeing the chip period of single-time sampling, is 1/1228800 second in the system;
Figure G2009101937932D00000511
Be invariant.The estimation of frequency offseting value adopts 1 comparator, 1 multiplier to realize.
The foregoing description is an example with the single-time sampling, is preferred implementation of the present invention, but embodiments of the present invention are not restricted to the described embodiments, for example the principle of multiple sampling with realize and can on the described basis of present embodiment, simple extension obtain; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify, and all should be the substitute mode of equivalence, is included within protection scope of the present invention.

Claims (6)

1. down link synchronisation method that is applied to the CDMA20001x system is characterized in that may further comprise the steps:
Step 1, buffer memory are the received signal r of M chip for initial total length with s constantly I(s+k), r Q(s+k), and with it be divided into the P section, every segment length X chip, M=PX;
Step 2, make l=0, with received signal l segment data with add up after the conjugation pointwise of corresponding local PN sequence l section is multiplied each other, obtain 1 accumulation result;
Step 3, l=l+1, repeating step 2 until l=P-1, obtains P-1 point accumulation result;
Step 4, with the P point accumulation result end zero padding of step 2, step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, N is 2 integral number power;
Step 5, N point transformation result is asked for mould value square respectively;
The maximum of step 6, search N point mould value square;
Step 7, with mould value square maximum and default thresholding relatively if surpass thresholding, is then successfully caught the PN phase place; Otherwise s=s+1, chip of received signal original position time-delay returns step 1.
2. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: described being accumulated in the programming device of step 2 realized by matched filter.
3. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: the described FFT conversion of step 4 is used special-purpose FFT chip or use Nlog in programming device 2N complex multiplier and 2Nlog 2N complex adder realizes.
4. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: asking for by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass of the described mould value of step 5 square realizes.
5. the down link synchronisation method that is applied to the CDMA20001x system according to claim 1 is characterized in that: square peaked search of the described mould value of step 6 adopts N-1 comparator to realize.
6. according to each described down link synchronisation method that is applied to the CDMA20001x system among the claim 1-5, it is characterized in that step 6 also writes down the position that mould value square maximum occurs in N point mould value square After described step 7 is successfully caught the PN phase place, also carry out:
Step 8, according to mould value square maximum position
Figure F2009101937932C0000012
Figure F2009101937932C0000013
To received signal and the frequency offseting value that exists between the local PN sequence
Figure F2009101937932C0000014
Carry out following estimation:
When
Figure F2009101937932C0000021
The time,
Figure F2009101937932C0000022
When The time,
Figure F2009101937932C0000024
T wherein cChip period for single-time sampling.
CN2009101937932A 2009-11-10 2009-11-10 Down link synchronization method applied to CDMA20001x system Expired - Fee Related CN101699776B (en)

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CN102098074A (en) * 2011-02-15 2011-06-15 北京理工大学 High-dynamic weak-signal rapid capture method for direct sequence spread spectrum system
CN102098074B (en) * 2011-02-15 2014-04-09 北京理工大学 High-dynamic weak-signal rapid capture method for direct sequence spread spectrum system
CN102833204A (en) * 2012-08-24 2012-12-19 西安空间无线电技术研究所 Frequency offset estimation implementation method
CN102833204B (en) * 2012-08-24 2015-02-11 西安空间无线电技术研究所 Frequency offset estimation implementation method
CN108051829A (en) * 2017-11-06 2018-05-18 深圳开阳电子股份有限公司 A kind of satellite navigation receiver and its navigation bit synchronization method and apparatus
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CN115174336A (en) * 2022-07-20 2022-10-11 成都中科微信息技术研究院有限公司 Frequency offset estimation method, medium and device of DVB-RCS2 system
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