CN101697414A - Universal controller for power electronic devices of distributed generation systems - Google Patents

Abstract

The invention relates to a digital simulation modeling technology of distributed generation systems, in particular to a universal controller for power electronic devices of the distributed generation systems. In order to improve the convenience, the compatibility and the efficiency of the modeling of the power electronic devices of the distributed generation systems, the invention adopts the technical scheme that the universal controller for the power electronic devices of the distributed generation systems comprises a signal acquiring module and a signal filtering module, wherein the signal acquiring module is used for acquiring current and voltage signals of a distributed power supply, a distributed energy storage device, an AC bus and a DC bus, and the current and voltage signals are output to a bus structure through the signal filtering module; the bus structure mainly comprises a universal controller operation mode selecting and analyzing module, and the working modes of a channel structure P and a channel structure Q are determined through mode identifications. The universal controller is mainly used for the digital simulation of the power electronic devices of the distributed generation systems.

Description

Universal controller for power electronic devices of distributed generation systems

Technical field

The present invention relates to distributed generation system Digital Simulation modeling technique.Specifically relate to the universal controller for power electronic devices of distributed generation systems model building method.

Technical background

Distributed generation system refer generally to generated output at small modular, the distributing of several KW to 50MW, be arranged near the user electricity generation system for user's power supply.A large amount of distributed power sources is linked into when being incorporated into the power networks in the transmission and distribution networks can produce appreciable impact to the dynamic characteristic of electric power system.Widely used photovoltaic generation, silent oscillation distributed source such as fuel cell have very little inertia time constant, reduced the rotation energy storage in the system, needs and energy storage device cooperate when big disturbance takes place in system provides effective power to support, this has very big difference with traditional energy exchange mode based on electric rotating machine, most of distributed power sources and energy-storage travelling wave tube are to be linked among the alternating current-direct current electrical network by power electronic equipment, digital simulation technique is main means of analyzing the complicated dynamic behaviour of distribution system that contains distributed generation system, is the basis of realizing system emulation and set up the universal controller for power electronic devices model.

Various distributed power sources, energy-storage travelling wave tube are also in continuous development and change, different element characteristics has determined the controlled target of the power electronic equipment that connects to have nothing in common with each other, if the programmed algorithm of in Digital Simulation, being correlated with at the model development of each power electronic equipment control system, will cause a lot of inconvenience to development of Simulation System, be unfavorable for improving the reliability of simulated program.

At the multifarious characteristics of power electronic equipment, people have proposed multiple generalization power electronic device hardware configuration design, as research institution of USN (ONR) a kind of power electronics building blocks technology (Power Electronic BuildingBlock-PEBB) is proposed, American National National Renewable Energy Laboratory (NERL) has been developed a kind of senior power electronics interface (Advanced Power Electronics Interfaces-APEI) that is used for distributed generation system, make integrated a high level that reaches of power electronic device, but these work all are at the Power Electronic Circuit hardware designs, not to controller architecture detailed design in addition; In the distributed generation system simulation technical field, some power electronic equipment controller models that propose are scattered relatively at present, can't adapt to simulation model variation and general-purpose demand simultaneously.Therefore set up and power electronic equipment controller generalization digital simulation model that the generalization hardware unit is complementary, to reducing the complexity of distributed generation system simulation modeling, the be incorporated into the power networks model tormulation form of system of standardization distributed power generation has great importance.

Summary of the invention

For overcoming the deficiencies in the prior art, the objective of the invention is to guarantee under the prerequisite of requirement of engineering precision, a kind of general purpose controller simulation model that is suitable for realizing the control of distributed generation system power electronics is provided, this simulation model can by typical electric power system business software storehouse compatibility, improve the convenience of power electronic devices of distributed generation systems modeling, and improve the efficient of distributed generation system total system simulation modeling, dwindle the product design cycle and reduce cost.

Universal controller for power electronic devices of distributed generation systems comprises:

Signals collecting and filtration module, signal acquisition module are used to gather distributed power source, distributed energy storage device, ac bus, the electric current of dc bus, voltage signal, and output to bus structures by filtration module;

Comprise mainly in the bus structures that the general purpose controller operator scheme selects analysis module, determine the mode of operation of P, Q channel design, and the output modulation signal of P, Q passage is carried out amplitude limiting processing, saturated conditions occurs to prevent modulation signal by pattern identification;

The P channel design: PWM converter q vector control structure and DC-DC converter constant voltage control structure are unified among the control channel, are the P channel design;

The Q channel design: the d vector control structure of PWM converter is the Q channel design.

Described P channel design comprises the outer ring controller of P passage extending controller, P passage, the interior ring controller of P passage that links to each other successively, and P passage extending controller is provided with sagging control switch DROOP, MPPT maximum power point tracking algorithm controls MPPT, P passage output set point switch;

The SET_FREQ bus frequency setting signal of analysis module is selected in sagging control switch DROOP reception from the bus frequency BUS_FREQ signal of signals collecting and filtration module, from operator scheme;

MPPT maximum power point tracking algorithm controls MPPT receives direct voltage VDC_FLITER, the direct current IDC_FLITER signal from signals collecting and filtration module;

P passage output set point switch receives power P _ FLITER, the direct voltage VDC_FLITER signal from signals collecting and filtration module, SET_VMPPT signal from MPPT maximum power point tracking algorithm controls MPPT, from SET_UP2 signal from sagging control switch DROOP, select the pattern identification OUT_P_PATH_MODE signal of analysis module from operator scheme, and receive permanent power control reference value SET_P, dc capacitor voltage reference value SET_VDC signal;

The outer ring controller of P passage receives the pattern identification OUT_P_PATH_MODE signal of selecting analysis module from operator scheme;

Ring controller receives the q axle component Iq_FLITER signal from signals collecting and filtration module in the P passage.

Described Q channel design comprises the outer ring controller of Q passage extending controller, Q passage, the interior ring controller of Q passage that links to each other successively, and Q passage extending controller is provided with the sagging control switch DROOP of Q passage, Q passage output set point switch;

The sagging control switch DROOP of Q passage receives from voltage magnitude BUS_VOLTM, distributed power source or the energy-storage travelling wave tube of signals collecting and filtration module or the top-cross that is incorporated into the power networks stream bus port voltage amplitude SET_VOLTM signal;

Q passage output set point switch receives voltage magnitude BUS_VOLTM, the power Q_FLITER signal from signals collecting and filtration module, from pattern identification OUT_Q_PATH_MODE signal, the OUT_P_PATH_MODE signal of operator scheme selection analysis module, permanent power control reference value SET_Q, mask pattern SET_ZERO signal.

The outer ring controller of Q passage receives the pattern identification OUT_Q_PATH_MODE signal of selecting analysis module from operator scheme;

Ring controller receives the d axle component Id_FLITER signal from signals collecting and filtration module in the Q passage.

Bus structures are carried out amplitude limiting processing to the output modulation signal of P, Q passage, and the amplitude limit mode is determined that by following formula output Dq, Dd are the modulation signal after the amplitude limiting processing:

$D_q=\mathrm{sig}\left(D_1\right)\&times;\sqrt{D_m^2-{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}}$

${\mathrm{<figure-callout\; id="2"\; label="D\; m"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_m^{}=\left\{\begin{array}{cc}{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+D_d^2& (0<{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}<\mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX})\\ \mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX}& ({\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}\&GreaterEqual;\mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+D_d^2)\end{array}\right..$

$D_d=\left\{\begin{array}{cc}{D}_2& (0<{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_2<\mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX})\\ \mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX}& ({\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_2\&GreaterEqual;\mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;D_2)\end{array}\right.$

The present invention has following technique effect:

Combine by each several part control module and a series of logic selector channel, can be combined into corresponding control structure according to different logic selection modes, realize the control purpose of various power electronic equipments, thus the present invention reduce the complexity of distributed generation system simulation modeling;

The signal that general purpose controller of the present invention goes for the multiple classes of multiterminal such as distributed power source, energy-storage travelling wave tube, AC side, DC side inserts, inner control module energy plug and play, thereby the present invention also has characteristics easy to use.

Description of drawings

Fig. 1: universal controller for power electronic devices of distributed generation systems model logic module figure.

Fig. 2: universal controller for power electronic devices of distributed generation systems model functional block diagram.

Fig. 3: signals collecting and filtration module structure chart.

Fig. 4: phase-locked loop module structure chart.

Fig. 5: operator scheme analysis chart.

General purpose controller operator scheme analysis module _ variable-definition table among Fig. 5

??ID	Data type	Data name	Describe
				??1	??Bool	??CONTROL_MPPT	MPPT maximum power point tracking algorithm controls sign
??2	??Bool	??CONTROL_BOOST	DC-DC convertor controls sign
				??3	??Bool	??SWITCH_DROOP	Sagging control switch sign
??4	??Bool	??SWITCH_VF	Constant frequency and constant voltage control switch sign
				??5	??Bool	??SWITCH_POWER	Permanent power control switching sign
??6	??Bool	??SWITCH_VOLT	Constant voltage control switch sign
				??7	??Bool	??CONTROL_P_PATH	P channel start sign
??8	??Bool	??CONTROL_Q_PATH	Q channel start sign
				??9	??Bool	??OUT_P_PATH_MODE	P channel pattern sign
??10	??Bool	??OUT_Q_PATH_MODE	Q channel pattern sign

Operator scheme analysis module _ mode number definition

Mode number	Describe
		??OUT_P_PATH_MODE＝1	MPPT maximum power point tracking algorithm (BOOSTER pattern)

Mode number	Describe
		??OUT_P_PATH_MODE＝2	DC-DC converter constant voltage control (BOOSTER pattern)
??OUT_P_PATH_MODE＝3	The sagging control of PWM converter (CONVERTER pattern)
		??OUT_P_PATH_MODE＝4	PWM converter constant frequency and constant voltage control (CONVERTER pattern)
??OUT_P_PATH_MODE＝5	The permanent power control of PWM converter (CONVERTER pattern)
		??OUT_P_PATH_MODE＝6	PWM converter constant voltage control (CONVERTER pattern)
Mode number	Describe
		??OUT_Q_PATH_MODE＝1	The sagging control of PWM converter (CONVERTER pattern)
??OUT_Q_PATH_MODE＝2	PWM converter constant frequency and constant voltage control (CONVERTER pattern)
		??OUT_Q_PATH_MODE＝3	The permanent power control of PWM converter (CONVERTER pattern)
??OUT_Q_PATH_MODE＝4	PWM converter constant voltage control (CONVERTER pattern)

Fig. 6: P channel design figure.

Fig. 7: P passage output set point is selected principle schematic.

Fig. 8: Q channel design figure.

Fig. 9: Q passage output set point is selected principle schematic.

Fig. 6, P passage _ variable-definition table among Fig. 7

??ID	Data type	Data name	Describe
				??1	??double	??KMPPT	MPPT algorithm PI proportional gain
??2	??double	??TMPPT	MPPT algorithm PI time constant
				??3	??double	??SET_FREQ	Bus frequency reference value fref
??4	??double	??BUS_FREQ	Bus frequency f s
				??5	??double	??SET_P	Active power reference value Pref
??6	??double	??SET_VDC	Direct voltage reference value Vdc_ref
				??7	??double	??SET_VMPPT	MPPT algorithm output dc voltage reference value VMPPT_ref
??8	??double	??SET_UP1	The permanent parameter control of P passage branch road is selected output valve

??ID	Data type	Data name	Describe
				??9	??double	??SET_UP2	DROOP_V/F module output valve
??10	??double	??P_FLITER	Active power sampling filter value
				??11	??double	??VDC_FLITER	Direct voltage sampling filter value
??12	??double	??IDC_FLITER	Direct current sampling filter value
				??13	??double	??SET_Uq	P passage microgrid control branch road is selected output valve
??14	??double	??Uq	The permanent parameter of P passage is selected output valve
				??15	??double	??Kq	Outer ring controller PI proportional gain
??16	??double	??Tq	Outer ring controller PI time constant
				??17	??double	??VOUT_MAX	The outer ring controller upper limit
??18	??double	??VOUT_MIN	Outer ring controller lower limit
				??19	??double	??SET_Iq	Interior ring controller reference value
??20	??double	??Iq_FLITER	Electric current q component samples filter value
				??21	??double	??Kiq	Interior ring controller PI proportional gain
??22	??double	??Tiq	Interior ring controller PI time constant
				??23	??double	??VIN_MAX	The interior ring controller upper limit
??24	??double	??VIN_MIN	Interior ring controller lower limit
				??25	??double	??Dq	P passage output modulation signal

Fig. 8, Q passage _ variable-definition table among Fig. 9

??ID	Data type	Data name	Describe
				??5	??double	??SET_VOLTM	Busbar voltage amplitude reference value Vref
??6	??double	??BUS_VOLTM	Busbar voltage amplitude Vs
				??7	??double	??SET_Q	Reactive power reference qref Qef

??ID	Data type	Data name	Describe
				??8	??double	??SET_ZERO	Null value is provided with
??10	??double	??SET_UP3	The permanent parameter control of Q passage branch road is selected output valve
				??11	??double	??SET_UP4	DROOP_V/F module output valve
??12	??double	??Q_FLITER	Reactive power sampling filter value
				??14	??double	??SET_Ud	Q passage microgrid control branch road is selected output valve
??15	??double	??Ud	The permanent parameter of Q passage is selected output valve
				??16	??double	??Kd	Outer ring controller PI proportional gain
??17	??double	??Td	Outer ring controller PI time constant
				??18	??double	??VOUT_MAX	The outer ring controller upper limit
??19	??double	??VOUT_MIN	Outer ring controller lower limit
				??20	??double	??SET_Id	Interior ring controller reference value
??21	??double	??Id_FLITER	Electric current d component samples filter value
				??22	??double	??Kid	Interior ring controller PI proportional gain
??23	??double	??Tid	Interior ring controller PI time constant
				??24	??double	??VIN_MAX	The interior ring controller upper limit
??25	??double	??VIN_MIN	Interior ring controller lower limit
				??26	??double	??Dd	Q passage output modulation signal

Embodiment

The power electronic equipment controller generalization digital simulation model that foundation and generalization and hardware unit are complementary, to reducing the complexity of distributed generation system simulation modeling, the be incorporated into the power networks model tormulation form of system of standardization distributed power generation has great importance.

In distributed generation system, though the controlled target of various power electronic equipments is different, but structure that it is main and control method still have certain rules can seek, sum up this regularity, extract the tangible universal electric power electronic installation of modular characteristics general purpose controller model, significant to the exploitation of simplifying stable simulated program.

The present invention is directed to the characteristics of distributed power source, distributed energy-storage system, and the control strategy demand of distributed power generation grid-connected system employing, design universal controller for power electronic devices of distributed generation systems model as depicted in figs. 1 and 2, be called for short the general purpose controller model.This model is combined by each several part control module and a series of logic selector channel, can be combined into corresponding control structure according to different logic selection modes, realizes the control purpose of various power electronic equipments.The general purpose controller model is divided into: current control layer, power key-course, three logical levels of microgrid key-course:

1) current control layer: the core is interior ring controller in the current control layer, its critical function is to gather distributed power source, distributed energy storage device, AC network, the electric current of dc bus, voltage signal, the control of realization line switching, because the time constant of interior ring controller is about (100 μ s), in stability analysis, generally can save, if but fault and disturbance occur in the near-end of inverter, then need to take into account the effect of this part, otherwise phantom error can increase.

2) power key-course: the power key-course is mainly realized the trend control of access point, imports corresponding set value of the power, the reference value of ring controller in the output current key-course.

3) microgrid key-course: the microgrid key-course is mainly realized two purposes, and one is to realize distributed generation system under the state of islet operation, the redistributing and controlling of system power trend; Another is a maximal power tracing of realizing photovoltaic generating system or wind generator system, its core is an extending controller, comprise the control of sagging control, constant frequency and constant voltage (V/f), MPPT control, input signal is ac bus voltage magnitude, frequency, distributed power source and energy storage device or DC bus-bar voltage, electric current.

In order to realize the control effect of above-mentioned each key-course, general purpose controller is divided into according to function: signals collecting and filtration module, bus structures, P channel design, Q channel design.The inner link that has between different functional modules and the logical level is as shown in table 1.The P channel design is made up of three submodules of ring controller in P_PATH extending controller, the outer ring controller of P_PATH, the P_PATH in the table, and they belong to microgrid key-course, power key-course, current control layer; Q channel design and P channel design have symmetry, and appropriate section is described similar.In addition, it is P, the corresponding extending controller of Q passage, the outer ring controller sign that supplies a pattern that general purpose controller operator scheme in the bus structures is selected analysis module, to determine which kind of pattern general purpose controller is operated under, as DC-DC converter pattern (being called for short the BOOSTER pattern), PWM converter pattern (being called for short the CONVERTER pattern), and accept the output modulation signal of P, Q passage, and output signal is carried out amplitude limiting processing, saturated conditions appears to prevent modulation signal.

What 1) distributed generation system power electronic controller commonly used adopted is many ring control structures, for example general employing of PWM converter encircled d, q vector control more, general many rings or the monocycle constant voltage control mode of adopting of DC-DC converter, is identical from control structure PWM converter q vector control structure with DC-DC converter constant voltage control structure, the present invention is unified in both among the control channel, is called the P channel design;

2) the present invention is called the Q channel design with the d vector control structure of PWM converter.

3) signals collecting and filtration module are mainly used in and gather distributed power source, distributed energy storage device, ac bus, the electric current of dc bus, voltage signal.

4) mainly comprise general purpose controller operator scheme selection analysis module in the bus structures, determine the mode of operation of P, Q channel design by pattern identification.And the output modulation signal of P, Q passage carried out amplitude limiting processing, saturated conditions appears to prevent modulation signal.

Table 1 functional module and logical level contact figure

Compare with existing power electronic devices of distributed generation systems controller model, the signal that general purpose controller goes for the multiple classes of multiterminal such as distributed power source, energy-storage travelling wave tube, AC side, DC side inserts, inner control module has " plug and play " characteristics, can assemble, connect use according to the specific requirement of simulation calculation, and model structure has extensibility, along with the continuous development of distributed generation system, can increase new functional module to adapt to new demand.

Below in conjunction with drawings and the specific embodiments the present invention is further described.

The concrete controller model of the universal controller for power electronic devices of distributed generation systems modelling that utilizes the present invention to propose needs five part work: (1) signals collecting and filtering operation; (2) operator scheme analysis; (3) export the operating state of determining the P channel design according to pattern; (4) export the operating state of determining the Q channel design according to pattern; (5) modulation signal amplitude limiting processing.Be illustrated with regard to the realization of each several part content respectively below:

(1) signals collecting and filtering operation:

Gather distributed power source, distributed energy storage device, ac bus, the electric current of dc bus, voltage signal, be used for distributed power source operation control or the side control of being incorporated into the power networks, different mode signal processing method difference:

1. if general purpose controller is used for analog D C-DC converter control system, then be called the BOOSTER pattern: gather direct voltage VDC_FLITER, direct current IDC_FLITER realizes two closed loop voltage stabilizing controls of general DC-DC converter, perhaps photovoltaic array side maximal power tracing control.

2. if general purpose controller is used to simulate PWM converter control system, then be called the COVERTER pattern: gather distributed power source side, the top-cross that is incorporated into the power networks stream voltage synchronized component VX, VY, defeated as phase-locked loop pll extraction voltage phase angle θ, simultaneously to voltage, electric current synchronous coordinate system xy component VX, VY, IX, IY carries out coordinate transform, the electric current d axle component Id_FLITER that acquisition model control is required, q axle component Iq_FLITER, voltage magnitude BUS_VOLTM, power P _ FLITER, Q_FLITER, and bus frequency BUS_FREQ.

(2) operator scheme analysis

The operator scheme analysis is one of embodiment of model generalization feature, determines the mode of operation of P, Q channel design by pattern identification.Pattern identification comprises: MPPT maximum power point tracking algorithm controls sign CONTROL_MPPT, DC-DC convertor controls sign CONTROL_BOOST, sagging control switch sign SWITCH_DROOP, constant frequency and constant voltage control switch sign SWITCH_VF, permanent power control switching sign SWITCH_POWER, constant voltage control switch sign SWITCH_VOLT, P channel start sign CONTROL_P_PATH, Q channel start sign CONTROL_Q_PATH, P channel pattern sign OUT_P_PATH_MODE, Q channel pattern output OUT_Q_PATH_MODE, export the result by logical operation or corresponding pattern:

1.OUT_P_PATH_MODE=1, start MPPT maximum power point tracking algorithm (BOOSTER pattern);

2.OUT_P_PATH_MODE=2, start DC-DC converter constant voltage control (BOOSTER pattern);

3.OUT_P_PATH_MODE=3, and OUT_Q_PATH_MODE=1, start the sagging control of PWM converter (CONVERTER pattern);

4.OUT_P_PATH_MODE=4, and OUT_Q_PATH_MODE=2, start PWM converter constant frequency and constant voltage control (CONVERTER pattern);

5.OUT_P_PATH_MODE=5, and OUT_Q_PATH_MODE=3, start the permanent power control of PWM converter (CONVERTER pattern);

6.OUT_P_PATH_MODE=6, and OUT_Q_PATH_MODE=4, start PWM converter constant voltage control (CONVERTER pattern).

Concrete logical operation principle can be selected analysis module with reference to general purpose controller operator scheme shown in the accompanying drawing 5, below is the corresponding relation between pattern identification value and the control model:

The mapping table of table 2 pattern identification value and P passage control model

	??CONTROL ??_MPPT	??CONTROL ??_BOOST	??CONTROL ??_P_PATH	??SWITC ??H_VF	??SWITCH ??_DROOP	??SWITCH ??_POWER	?SWITCH ?_VOLT
								MPPT maximum power point tracking control OUT_P_PATH_ MODE=1	??1	??1	??1	??0	??0	??0	??0
DC-DC converter constant voltage control OUT_P_PATH_ MODE=2	??0	??1	??1	??0	??0	??0	??1
								The permanent power control of PWM converter OUT_P_PATH_ MODE=3	??0	??0	??1	??0	??0	??1	??0
The sagging control of PWM converter OUT_P_PATH_ MODE=4	??0	??0	??1	??0	??1	??0	??0
								PWM converter constant frequency and constant voltage control OUT_P_PATH_ MODE=5	??0	??0	??1	??1	??0	??0	??0
PWM converter perseverance	??0	??0	??1	??0	??0	??0	??1

	??CONTROL ??_MPPT	??CONTROL ??_BOOST	??CONTROL ??_P_PATH	??SWITC ??H_VF	??SWITCH ??_DROOP	??SWITCH ??_POWER	?SWITCH ?_VOLT
								Voltage control OUT_P_PATH_ MODE=6

The mapping table of table 3 pattern identification value and Q passage control model

	??CONTROL ??_Q_PATH	??SWITCH ??_VF	??SWITCH ??_DROOP	??SWITCH ??_POWER	??SWITCH ??_VOLT
						MPPT maximum power point tracking control OUT_Q_PATH_MODE=0	??0	??0	??0	??0	??0
DC-DC converter constant voltage control OUT_Q_PATH_MODE=0	??0	??0	??0	??0	??0
						The permanent power control of PWM converter OUT_Q_PATH_MODE=1	??1	??0	??0	??1	??0
The sagging control of PWM converter OUT_Q_PATH_MODE=2	??1	??0	??1	??0	??0
						PWM converter constant frequency and constant voltage control OUT_Q_PATH_MODE=3	??1	??1	??0	??0	??0
PWM converter constant voltage control OUT_Q_PATH_MODE=4	??1	??0	??0	??0	??1

(3) P channel design operating state is determined

According to OUT_P_PATH_MODE output result, can determine P passage mode of operation, its mode of operation is embodied in the operating state of three submodules of ring controller in P_PATH extending controller, the outer ring controller of P_PATH, the P_PATH.

If P_PATH extending controller output SET_Uq adopts one of SET_UP2, SET_P, SET_VDC, then the P passage is operated under the CONVERTER pattern, SET_UP2 is sagging/constant frequency and constant voltage controller reference value, SET_P is permanent power control reference value, if SET_Uq adopts SET_VMPPT or SET_VDC, then be operated under the BOOSTER pattern, SET_VMPPT is a maximal power tracing module output voltage reference value, SET_VDC is the dc capacitor voltage reference value, and SET_UP1 is one of SET_VMPPT, SET_P, SET_VDC.

Concrete selection principle can be selected principle schematic with reference to the output of P passage shown in the accompanying drawing 7 set point, it below is the P passage operating state tabulation of determining by OUT_P_PATH_MODE output result and acquired signal, correspondingly, correspondence also provides the different mode reference value and takes different acquired signal in the table.

The tabulation of table 4P passage operating state

	??OUT_P_PATH ??_MODE＝1	??OUT_P_PATH ??_MODE＝2	??OUT_P_PATH ??_MODE＝3	??OUT_P_PATH ??_MODE＝4	??OUT_P_PATH ??_MODE＝5	??OUT_P_PATH ??_MODE＝6
							??SET ??_V ??MPP ??T	BOOSTER type collection signal is VDC_FLITER IDC_FLITER	??/	??/	??/	??/	??/
??SET ??_VD ??C	??/	BOOSTER type collection signal is VDC_FLITER	??/	??/	??/	CONVERTER type collection signal is VDC_FLITER
							??SET	??/	??/	??/	??/	??CONVERTE	??/
??_P					R type collection signal is P_FLITER
							??SET ??_UP ??2	??/	??/	CONVERTER type collection signal is BUS_FREQ	CONVERTE R type collection signal is BUS_FREQ	??/	??/

(4) Q channel design operating state is determined

According to OUT_Q_PATH_MODE and OUT_P_PATH_MODE output result, determine Q passage mode of operation jointly, its mode of operation is embodied in the operating state of three submodules of ring controller in Q_PATH extending controller, the outer ring controller of Q_PATH, the Q_PATH.

If Q_PATH extending controller output SET_Ud adopts SET_ZERO=0, the then corresponding conductively-closed of Q passage, the P channel design is operated under the BOOSTER pattern, if Q_PATH extending controller output SET_Ud adopts SET_Q, SET_UQ2, one of SET_VOLTM, then the Q channel design is operated under the CONVERTER pattern, SET_UQ2 is sagging/constant frequency and constant voltage controller reference value, SET_Q is permanent power control reference value, SET_VOLTM is a distributed power source, or energy-storage travelling wave tube, or the top-cross stream bus port voltage amplitude that is incorporated into the power networks, SET_UQ1 is SET_ZERO, SET_Q, one of SET_VOLTM.

Concrete selection principle can be selected principle schematic with reference to the output of P passage shown in the accompanying drawing 9 set point, it below is the Q passage operating state tabulation of determining by OUT_P_PATH_MODE output result, OUT_Q_PATH_MODE output results acquisition signal, correspondingly, correspondence also provides the different mode reference value and takes different acquired signal in the table.

The tabulation of table 5Q passage operating state

	OUT_P_PATH _ MODE=1,2 and OUT_Q_PATH _ MODE=0	OUT_P_PATH _ MODE=3,4,5,6 and OUT_Q_PATH _ MODE=1	OUT_P_PATH _ MODE=3,4,5,6 and OUT_Q_PATH _ MODE=2	OUT_P_PATH _ MODE=3,4,5,6 and OUT_Q_PATH _ MODE=3	OUT_P_PATH _ MODE=3,4,5,6 and OUT_Q_PATH _ MODE=4
						?SET_ZERO	Mask pattern	??/	??/	??/	??/
?SET_Q	??/	??/	??/	CONVERTER type collection signal is Q_FLITER	??/
						?SET_VOLTM	??/	??/	??/	??/	CONVERTER type collection signal is BUS_VOLTM
?SET_UQ2	??/	CONVERTER type collection signal is BUS_VOLTM	CONVERTER type collection signal is BUS_VOLTM	??/	??/

(5) modulation signal amplitude limiting processing

P, the Q passage is finally exported modulation signal D ₁, D ₂, for saturated phenomenon appears in anti-stop signal, need be to output D ₁, D ₂Carry out amplitude limiting processing, the amplitude limit mode is determined that by following formula (1) output Dq, Dd are the modulation signal after the amplitude limiting processing.

$D_q=\mathrm{sig}\left(D_1\right)\&times;\sqrt{D_m^2-{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}}$

${\mathrm{<figure-callout\; id="2"\; label="D\; m"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_m^{}=\left\{\begin{array}{cc}{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+D_d^2& (0<{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}<\mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX})\\ \mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX}& ({\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+{\mathrm{<figure-callout\; id="2"\; label="D\; d"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_d^{}\&GreaterEqual;\mathrm{<figure-callout\; id="1"\; label="VD"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">VD</figure-callout>}1\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;{\mathrm{<figure-callout\; id="1"\; label="D"\; filenames="H2009100710349E0000032.png,H2009100710349E0000041.png"\; state="\{\{state\}\}">D</figure-callout>}}_1^2+D_d^2)\end{array}\right.---\left(1\right)$

$D_d=\left\{\begin{array}{cc}{D}_2& (0<{\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_2<\mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX})\\ \mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX}& ({\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">D</figure-callout>}}_2\&GreaterEqual;\mathrm{<figure-callout\; id="2"\; label="VD"\; filenames="H2009100710349E0000081.png"\; state="\{\{state\}\}">VD</figure-callout>}2\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;D_2)\end{array}\right.$

Can the output modulation signal be used according to the different mode of controller employing:

1.BOOSTER pattern adopts modulation signal Dq control DC-DC converter circuit switch.

2.CONVERTER pattern adopts modulation signal Dq, Dd control PWM converter switch.

List the part document that those skilled in the art can use for reference below in implementing process of the present invention:

1, relevant " the multiring structure method for designing of distributed generation system PWM converter vector control and controller " basic principle knowledge can be referring to document:

Advanced?Power?Electronic?Interfaces?for?Distributed?Energy?Systems?Part?1：Systems?andTopologies/W.Kramer，S.Chakraborty，B.Kroposki，H.Thomas//National?Renewable?EnergyLaboratory?Report?No.SR-560-38017。

Stability?of?A?Microgrid/Jayawarna，N.；Wu，X.；Zhang，Y.；Jenkins，N.；Barnes，M.//3rd?IETInternational?Conference?on?Power?Electronics，Machines?and?Drives(PEMD?2006)，(CP514)：316-320。

2, can be referring to document about " MPPT maximum power point tracking algorithm ":

Comparison?of?Photovoltaic?Array?Maximum?Power?Point?Tracking?Techniques/Trishan?Esram，Patrick.L.Chapman//IEEE?Trans.on?Energy?Conversion，2007，22(2)：439-499

3, can be referring to document about " the permanent power control of PWM, sagging control, constant frequency and constant voltage control, constant voltage are controlled ":

A?Stability?Algorithm?for?the?Dynamic?Analysis?of?Inverter?Dominated?Unbalanced?LVMicrogrids/Nikos?L.Soultanis，Stavros?A.Papathanasiou，Nikos?D，Hatziargyriou//IEEE?Trans.on?Power?Systems，2007，22(1)：294-304

Doubly-Fed?Induction?Machine?Models?for?Stability?Assessment?of?Wind?Farms/Markus?A.P¨oller//Proceedings?of?the?2003?IEEE?PowerTech?Conference，Bologna，2003

4, can be referring to document about " control of DC-DC converter constant voltage ":

Direct?Drive?Synchronous?Machine?Models?for?Stability?Assessment?of?Wind?Farms/SebastianAchilles，Markus?P¨oller//Proceedings?of?the?Fourth?International?Workshop?on?Large?ScaleIntegration?of?Wind?Power?and?Transmission?Networks?for?Offshore?Wind?Farms，Billund，Denmark，October?20-212003

Need to prove in addition, the present invention is open and that disclose, and all combinations and method can produce by using for reference this paper disclosure, although combination of the present invention and method are to be described by detailed implementation process, but those skilled in the art obviously can not break away from content of the present invention, method and apparatus as herein described is spliced in the spirit and scope or change, or increase and decrease some parts, more particularly, the replacement that all are similar and change apparent to those skilled in the artly, they are regarded as being included in spirit of the present invention, among scope and the content.

Claims (4)

1. a universal controller for power electronic devices of distributed generation systems is characterized in that, comprising:

Signals collecting and filtration module, signal acquisition module are used to gather distributed power source, distributed energy storage device, ac bus, the electric current of dc bus, voltage signal, and output to bus structures by filtration module;

Comprise mainly in the bus structures that the general purpose controller operator scheme selects analysis module, determine the mode of operation of P, Q channel design, and the output modulation signal of P, Q passage is carried out amplitude limiting processing, saturated conditions occurs to prevent modulation signal by pattern identification;

The P channel design: PWM converter q vector control structure and DC-DC converter constant voltage control structure are unified among the control channel, are the P channel design;

The Q channel design: the d vector control structure of PWM converter is the Q channel design.

2. 1 described universal controller for power electronic devices of distributed generation systems as requested, it is characterized in that, described P channel design comprises the outer ring controller of P passage extending controller, P passage, the interior ring controller of P passage that links to each other successively, and P passage extending controller is provided with sagging control switch DROOP, MPPT maximum power point tracking algorithm controls MPPT, P passage output set point switch;

The SET_FREQ bus frequency setting signal of analysis module is selected in sagging control switch DROOP reception from the bus frequency BUS_FREQ signal of signals collecting and filtration module, from operator scheme;

MPPT maximum power point tracking algorithm controls MPPT receives direct voltage VDC_FLITER, the direct current IDC_FLITER signal from signals collecting and filtration module;

P passage output set point switch receives power P _ FLITER, the direct voltage VDC_FLITER signal from signals collecting and filtration module, SET_VMPPT signal from MPPT maximum power point tracking algorithm controls MPPT, SET_UP2 signal from sagging control switch DROOP, select the pattern identification OUT_P_PATH_MODE signal of analysis module from operator scheme, and receive permanent power control reference value SET_P, dc capacitor voltage reference value SET_VDC signal;

The outer ring controller of P passage receives the pattern identification OUT_P_PATH_MODE signal of selecting analysis module from operator scheme;

Ring controller receives the q axle component Iq_FLITER signal from signals collecting and filtration module in the P passage.

3. 1 described universal controller for power electronic devices of distributed generation systems as requested, it is characterized in that, described Q channel design comprises the outer ring controller of Q passage extending controller, Q passage, the interior ring controller of Q passage that links to each other successively, and Q passage extending controller is provided with the sagging control switch DROOP of Q passage, Q passage output set point switch;

The sagging control switch DROOP of Q passage receives from voltage magnitude BUS_VOLTM, distributed power source or the energy-storage travelling wave tube of signals collecting and filtration module or the top-cross that is incorporated into the power networks stream bus port voltage amplitude SET_VOLTM signal;

Q passage output set point switch receives voltage magnitude BUS_VOLTM, the power Q_FLITER signal from signals collecting and filtration module, from pattern identification OUT_Q_PATH_MODE signal, the OUT_P_PATH_MODE signal of operator scheme selection analysis module, permanent power control reference value SET_Q, mask pattern SET_ZERO signal;

The outer ring controller of Q passage receives the pattern identification OUT_Q_PATH_MODE signal of selecting analysis module from operator scheme;

Ring controller receives the d axle component Id_FLITER signal from signals collecting and filtration module in the Q passage.

4. 1 described universal controller for power electronic devices of distributed generation systems as requested, it is characterized in that bus structures are carried out amplitude limiting processing to the output modulation signal of P, Q passage, the amplitude limit mode is determined by following formula, output Dq, Dd are the modulation signal after the amplitude limiting processing:

$D_q=\mathrm{sig}\left(D_1\right)\&times;\sqrt{D_m^2-D_d^2}$

$D_m^2=\left\{\begin{array}{cc}{D}_1^2+D_d^2& (0<D_1^2+D_d^2<\mathrm{VD}1\_\mathrm{MAX})\\ \mathrm{VD}1\_\mathrm{MAX}& (D_1^2+D_d^2\&GreaterEqual;\mathrm{VD}1\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;D_1^2+D_d^2)\end{array}\right.$

$D_d=\left\{\begin{array}{cc}{D}_2& (0<D_2<\mathrm{VD}2\_\mathrm{MAX})\\ \mathrm{VD}2\_\mathrm{MAX}& (D_2\&GreaterEqual;\mathrm{VD}2\_\mathrm{MAX})\\ 0& (0\&GreaterEqual;D_2)\end{array}\right.$

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