CN101694644A - Embedded flash controller - Google Patents
Embedded flash controller Download PDFInfo
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- CN101694644A CN101694644A CN200910232953A CN200910232953A CN101694644A CN 101694644 A CN101694644 A CN 101694644A CN 200910232953 A CN200910232953 A CN 200910232953A CN 200910232953 A CN200910232953 A CN 200910232953A CN 101694644 A CN101694644 A CN 101694644A
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Abstract
The invention relates to an embedded flash controller, which comprises a configuration register, a clock controller and a flash control signal generating circuit. The clock controller is used for transforming external clock into reference clock needed by the flash control signal generating circuit, the flash control signal generating circuit generates corresponding control signals inside the embedded flash controller through a state machine and controls timing sequences of the control signals, and the flash control signal generating circuit mainly consists of a clock counter, a time sequence comparator, a flash operation type judging state machine and a flash control signal generating state machine. The embedded flash controller has the advantages of simple realization of hardware, relatively strong portability and simple software operation.
Description
Technical field
The present invention relates to a kind of embedded flash memory, be specifically related to a kind of controller that is used to control embedded flash memory programming and erase operation.
Background technology
Current development along with ic manufacturing technology, the integrated level of chip is more and more higher, on the one hand, the integrated function of same chip gets more and more, by the different software of arranging in pairs or groups, same chip can be used as different purposes, as both doing USB flash disk, can do smart card again, program will meet the agreement of USB when doing USB flash disk, the communications protocol that will meet smart card when doing smart card, on the other hand, production debugging, upgrading needs update software, and this program that just requires to be embedded in chip internal can be upgraded accordingly according to different application, and the way that adopts is that chip internal embeds programmable embedded flash memory EmbFlash now, by embedded flash controller embedded flash memory EmbFlash internal program is wiped and programmed and reach the purpose of refresh routine, and there is the hardware complexity in existing embedded flash controller, portable poor, the deficiency of software complexity.
Summary of the invention
The object of the invention provides that a kind of hardware is simple, portability is strong, software operation simple embedded flash controller.
For achieving the above object, the technical solution used in the present invention is: a kind of embedded flash controller comprises:
Configuration register, this configuration register have first control section, second control section, control bit and zone bit; First control section is used to dispose the action type of embedded flash memory; Second control section is used to dispose the fiducial value of second comparer; Control bit is used to enable first counter; Whether zone bit is used for the sign operation and finishes;
Clock controller is used for external clock is converted to the required reference clock of flash memory control signal generative circuit, has first counter, second counter, first comparer, second comparer; First counter is provided with the counting that external timing signal is carried out eight frequency divisions according to control bit; First comparer is used to cooperate first counter that external clock is carried out elementary frequency reducing, the elementary frequency reducing clock after the acquisition frequency reducing; Second counter disposes corresponding frequency division according to the fiducial value of second control section elementary frequency reducing clock is counted; Second comparer cooperates second counter that elementary frequency reducing clock is carried out secondary frequency reducing according to the fiducial value of second control section, obtains the reference clock of frequency reducing once more;
Flash memory control signal generative circuit enables the inner control signal corresponding of embedded flash memory and controls the sequential of described control signal by state machine, and described flash memory control signal generative circuit comprises:
(1) clock counter is used for reference clock is counted;
(2) timing comparator is controlled control signal according to the value of clock counter and the time sequence parameter of control signal;
(3) the flash disk operation type is judged state machine, and response CPU is to the operation of first control section of configuration configuration register, thereby the inner control signal corresponding of triggering embedded flash memory realizes the judgement to outside action type;
(4) the flash memory control signal generates state machine, comprising:
First state responds first control section and enables corresponding first control signal, second control signal, and gives timing comparator first reference time, and clock counter begins reference clock is counted simultaneously;
Second state is when the numerical value of clock counter equaled for first reference time, the clock counter zero clearing, trigger second state simultaneously, this state enables the 3rd control signal, and gives timing comparator second reference time, and clock counter begins reference clock is counted simultaneously;
The third state is when the numerical value of clock counter equaled for second reference time, the clock counter zero clearing, trigger the third state simultaneously, this state enables the 4th control signal, and gives timing comparator the 3rd reference time, and clock counter begins reference clock is counted simultaneously;
Four condition is when the numerical value of clock counter equaled for the 3rd reference time, the clock counter zero clearing, trigger four condition simultaneously, invalid the 4th control signal of this state, and give timing comparator the 4th reference time, clock counter begins reference clock is counted simultaneously;
The 5th state is when the numerical value of clock counter equaled for the 4th reference time, the clock counter zero clearing, trigger the 5th state simultaneously, invalid first control signal of this state, and give the timing comparator Wucan and examine the time, clock counter begins reference clock is counted simultaneously;
The 6th state, when equaling Wucan, the numerical value of clock counter examines the time, the clock counter zero clearing, trigger the 6th state simultaneously, invalid second control signal of this state, the 3rd control signal, and give timing comparator the 6th reference time, clock counter begins reference clock is counted simultaneously;
Idle condition, when the numerical value of clock counter equaled for the 6th reference time, zone bit is effective, triggers idle condition simultaneously, and operation is this time finished.
Related content in the technique scheme is explained as follows:
1, in the such scheme, described first counter is 3 a counter.
2, in the such scheme, second counter is 6 a counter.
Principle of work of the present invention is: according to system works frequency and the required sequential requirement of flash disk operation, configuration register is configured, clock controller produces the lower reference clock of frequency according to the Configuration Values of system works frequency and configuration register; Dispose first control section then, the write operation type, flash memory control signal generative circuit starts, and the sequential operation that enables the inner control signal corresponding of embedded flash memory and control described control signal is finished, and generates look-at-me.
Because the technique scheme utilization, the present invention compared with prior art has following advantage and effect:
1, the present invention can be by the control to reference time and control signal, as passing through the fiducial value of simple plus-minus status number and change comparer, develop new controller, thereby reach the purpose that the embedded flash memory that satisfies multiple model required and realized multiple function, have very strong portability.
2, the present invention starts hardware control by the simple configuration register, and hardware control is realized function corresponding automatically, and is all simple in the realization of hardware and software.
Description of drawings
Accompanying drawing 1 is a principle of the invention block diagram;
Accompanying drawing 2 is provided with synoptic diagram for configuration register of the present invention;
Accompanying drawing 3 is embedded flash memory internal operation control signal sequential chart of the present invention;
Accompanying drawing 4 is this flash memory of the present invention control signal generative circuit workflow synoptic diagram;
Accompanying drawing 5 is used workflow diagram for the present invention.
In the above accompanying drawing, 10, control module; 11, CPU; 12, interruptable controller; 13, embedded flash memory; 14, internal bus; 101, configuration register; 102, clock controller; 103, flash memory control signal generative circuit; 201, first control section; 202, second control section; 203, control bit; 204, zone bit; 501, first state; 502, second state; 503, the third state; 504, four condition; 505, the 5th state; 506, the 6th state; 507, idle condition; 508, the flash disk operation type is judged state machine; 1001, first control signal; 1002, second control signal; 1003, the 3rd control signal; 1004, the 4th control signal; T
13S, first reference time; T
34S, second reference time; T
4h, the 3rd reference time; T
41h, the 4th reference time; T
13h, Wucan examines the time; T
h, the 6th reference time.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment: a kind of embedded flash controller
A kind of embedded flash controller, as shown in Figure 1, its outside comprises:
CPU11 is used to carry out the firmware instructions that is stored on the internal storage, finishes control and management to embedded flash memory 13;
Internal bus 14 is used for data information, address information and control information;
Interruptable controller 12 is used to provide look-at-me to CPU11, makes CPU11 carry out interrupt routine, and interruptable controller 12 and CPU11 are through 14 two-way connections of internal bus;
This flash controller inside comprises:
Configuration register 101, as shown in Figure 2, this configuration register has first control section 201, second control section 202, control bit 203 and zone bit 204; First control section 201 is used to dispose the action type of embedded flash memory, and by CMD0, CMD1, CMD2, CMD3, CMD4, CMD5, six control bits of CMD6, the various combination of six control bits decides action type; Second control section 202 is used to dispose the fiducial value of second comparer (305), has six to be respectively DIV0, DIV1, DIV2, DIV3; DIV4, DIV5 store fiducial value; Control bit 203 is the PRDIV8 position, is used to enable first counter 301; Whether zone bit 204 is CCIF, be used for the sign operation and finish;
Clock controller 102 is used for external clock is converted to the required reference clock ref_clk of flash memory control signal generative circuit, has first counter, second counter, first comparer, second comparer; First counter is 3 a counter, and the counting that external timing signal is carried out eight frequency divisions is set according to control bit 203; First comparer is used to cooperate first counter that external clock is carried out elementary frequency reducing, the elementary frequency reducing clock after the acquisition frequency reducing; Second counter is 6 a counter, disposes corresponding frequency division according to the fiducial value of second control section 202 elementary frequency reducing clock is counted; Second comparer cooperates second counter that elementary frequency reducing clock is carried out secondary frequency reducing according to the fiducial value of second control section, obtains the reference clock of frequency reducing once more;
Flash memory control signal generative circuit enables the inner control signal corresponding of embedded flash memory and controls the sequential of described control signal by state machine, and described flash memory control signal generative circuit comprises:
(1) clock counter is used for reference clock ref_clk is counted;
(2) timing comparator is controlled control signal according to the value of clock counter and the time sequence parameter of control signal;
(3) the flash disk operation type is judged state machine 508, and response CPU11 is to the operation of first control section of configuration configuration register, thereby the inner control signal corresponding of triggering embedded flash memory realizes the judgement to outside action type;
(4) the flash memory control signal generates state machine, shown in accompanying drawing 3,4, comprising:
The third state 503 is when the numerical value of clock counter equals the second reference time T
34S, the clock counter zero clearing triggers the third state simultaneously, and this state enables the 4th control signal 1004, and gives the 3rd reference time of timing comparator T
4h, the 3rd reference time T
4hAs the retention time of the 4th control signal 1004, clock counter begins reference clock is counted simultaneously;
Four condition 504 is when the numerical value of clock counter equals the 3rd reference time T
4h, the clock counter zero clearing triggers four condition 504 simultaneously, invalid the 4th control signal 1004 of this state, and give the 4th reference time of timing comparator T
41h, the 4th reference time T
41hEnable to be cancelled the retention time constantly as first control signal, 1001 to the 4th control signals 1004; Clock counter begins reference clock is counted simultaneously;
The 5th state 505 is when the numerical value of clock counter equals the 4th reference time T
41h, the clock counter zero clearing triggers the 5th state 505 simultaneously, invalid first control signal 1001 of this state, and give the timing comparator Wucan and examine time T
13h, Wucan is examined time T
13hEnable to be cancelled the retention time constantly as the 3rd control signal 1003 to first control signals 1001; Clock counter begins reference clock is counted simultaneously;
The 6th state 506 is examined time T when the numerical value of clock counter equals Wucan
13h, the clock counter zero clearing triggers the 6th state 506 simultaneously, invalid second control signal 1002 of this state, the 3rd control signal 1003, and give the 6th reference time of timing comparator T
h, the 6th reference time T
hAs two interval times that continued operation is required, clock counter begins reference clock ref_clk is counted simultaneously;
Flash memory control signal generative circuit also can be realized other functions by state group of above principle expansion 2, for example erase feature etc.
The application flow of present embodiment embedded flash controller 10 as shown in Figure 5, detailed process is as follows:
A) configuring chip pattern pin makes system's ROM program start in this chip.The ROM program can not be changed, and the ROM program is mainly used in the configuration of UART, is used for receiving routine data from the UART mouth, and returns accepting state by the UART mouth.
B) reset after, the ROM program run, the configuration interface register is provided with corresponding baud rate, wait for to receive the order of main frame then.
C) main frame is sent out the order of shaking hands earlier, confirms whether the ROM program is ready to, and after the success of shaking hands, main frame is pressed flow process, the router data, and chip receives routine data, and a continuation address space of routine data being write SRAM in the chip.
D) behind the complete end of transmission of routine data, the program in the ROM will jump to SRAM internal program data, carry out the flash disk operation program.The flash disk operation program writes embedded flash memory 13 to system program.
E) the flash disk operation program writes embedded flash memory 13 to system program by control flash controller 10.
F) the flash disk operation program is according to system works frequency and the required sequential requirement of flash disk operation, configuration register 101 in the flash controller 10 is configured, clock controller 102 produces the lower reference clock Ref_clk of frequency according to the Configuration Values of system works frequency and configuration register 101;
G) CPU11 through internal bus to flash controller 10 corresponding address one-writing system application programs, write operation type simultaneously, flash memory control signal generative circuit 103 starts.
H) flash memory control signal generative circuit 103 enables embedded flash memory 13 inner control signal corresponding and controls the sequential of described control signal by state machine, and system application is write in the embedded flash memory 13.
J) repeat h, finish up to all programmings.
K) behind the electricity, reconfigure the chip mode chip under, make system start executive system utilities from embedded flash memory 13.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (1)
1. embedded flash controller is characterized in that: comprising:
Configuration register (101), this configuration register (101) have first control section (201), second control section (202), control bit (203) and zone bit (204); First control section (201) is used to dispose the action type of embedded flash memory; Second control section (202) is used to dispose the fiducial value of second comparer; Control bit (203) is used to enable first counter; Whether zone bit (204) is used for the sign operation and finishes;
Clock controller (102) is used for external clock is converted to the required reference clock (ref_clk) of flash memory control signal generative circuit (103), has first counter, second counter, first comparer, second comparer; First counter carries out eight frequency division counters according to being provided with of control bit (203) to external timing signal; First comparer is used to cooperate first counter that external clock is carried out elementary frequency reducing, the elementary frequency reducing clock after the acquisition frequency reducing; Second counter disposes corresponding frequency division according to the fiducial value of second control section (202) elementary frequency reducing clock is counted; Second comparer cooperates second counter that elementary frequency reducing clock is carried out secondary frequency reducing according to the fiducial value of second control section, obtains the reference clock (ref_clk) of frequency reducing once more;
Flash memory control signal generative circuit (103) enables the inner control signal corresponding of embedded flash memory (13) and controls the sequential of described control signal by state machine, and described flash memory control signal generative circuit (103) comprising:
(1) clock counter is used for described reference clock (ref_clk) is counted;
(2) timing comparator is controlled control signal according to the value of clock counter and the time sequence parameter of control signal;
(3) the flash disk operation type is judged state machine (508), and response CPU (11) is to the operation of first control section (201) of configuration configuration register (101), thereby the inner control signal corresponding of triggering embedded flash memory (13) realizes the judgement to outside action type;
(4) the flash memory control signal generates state machine, comprising:
First state (501) responds first control section and enables corresponding first control signal (1001), second control signal (1002), and gives first reference time of timing comparator (T
13S), clock counter begins reference clock is counted simultaneously;
Second state (502) is when the numerical value of clock counter equals the first reference time (T
13S), the clock counter zero clearing triggers second state simultaneously, and this state enables the 3rd control signal (1003), and gives second reference time of timing comparator (T
34S), clock counter begins reference clock is counted simultaneously;
The third state (503) is when the numerical value of clock counter equals the second reference time (T
34S), the clock counter zero clearing triggers the third state simultaneously, and this state enables the 4th control signal (1004), and gives the 3rd reference time of timing comparator (T
4h), clock counter begins reference clock is counted simultaneously;
Four condition (504) is when the numerical value of clock counter equals the 3rd reference time (T
4h), the clock counter zero clearing triggers four condition simultaneously, invalid the 4th control signal of this state (1004), and give the 4th reference time of timing comparator (T
41h), clock counter begins reference clock is counted simultaneously;
The 5th state (505) is when the numerical value of clock counter equals the 4th reference time (T
41h), the clock counter zero clearing triggers the 5th state simultaneously, invalid first control signal of this state (1001), and give the timing comparator Wucan and examine the time (T
13h), clock counter begins reference clock is counted simultaneously;
The 6th state (506) is examined the time (T when the numerical value of clock counter equals Wucan
13h), the clock counter zero clearing triggers the 6th state simultaneously, invalid second control signal of this state (1002), the 3rd control signal (1003), and give the 6th reference time of timing comparator (T
h), clock counter begins reference clock is counted simultaneously;
Idle condition (507) is when the numerical value of clock counter equals the 6th reference time (T
h), zone bit (204) is effective, triggers idle condition (507) simultaneously, and operation is this time finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910232953XA CN101694644B (en) | 2009-09-22 | 2009-09-22 | Embedded flash controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910232953XA CN101694644B (en) | 2009-09-22 | 2009-09-22 | Embedded flash controller |
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| CN101694644A true CN101694644A (en) | 2010-04-14 |
| CN101694644B CN101694644B (en) | 2011-04-13 |
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|---|---|---|---|
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411989A (en) * | 2010-09-22 | 2012-04-11 | 株式会社东芝 | Semiconductor integrated circuit and method of controlling memory |
| CN102930901A (en) * | 2011-08-08 | 2013-02-13 | 安凯(广州)微电子技术有限公司 | Controller used for memory and method for using controller |
| CN103593312A (en) * | 2012-08-13 | 2014-02-19 | 炬力集成电路设计有限公司 | Time sequence control method and NAND FLASH controller |
-
2009
- 2009-09-22 CN CN200910232953XA patent/CN101694644B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411989A (en) * | 2010-09-22 | 2012-04-11 | 株式会社东芝 | Semiconductor integrated circuit and method of controlling memory |
| CN102411989B (en) * | 2010-09-22 | 2015-02-25 | 株式会社东芝 | Semiconductor integrated circuit and method of controlling memory device |
| CN102930901A (en) * | 2011-08-08 | 2013-02-13 | 安凯(广州)微电子技术有限公司 | Controller used for memory and method for using controller |
| CN102930901B (en) * | 2011-08-08 | 2015-04-15 | 安凯(广州)微电子技术有限公司 | Controller used for memory and method for using controller |
| CN103593312A (en) * | 2012-08-13 | 2014-02-19 | 炬力集成电路设计有限公司 | Time sequence control method and NAND FLASH controller |
| WO2014026572A1 (en) * | 2012-08-13 | 2014-02-20 | 炬力集成电路设计有限公司 | Timing sequence control method and nand flash controller |
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| Publication number | Publication date |
|---|---|
| CN101694644B (en) | 2011-04-13 |
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Address after: Room C2031, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Patentee after: Suzhou Guoxin Technology Co., Ltd. Address before: Room C2031, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Patentee before: C*Core Technology (Suzhou) Co., Ltd. |