CN101685601B - Level generating circuit for plasma display - Google Patents
Level generating circuit for plasma display Download PDFInfo
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- CN101685601B CN101685601B CN 200810223468 CN200810223468A CN101685601B CN 101685601 B CN101685601 B CN 101685601B CN 200810223468 CN200810223468 CN 200810223468 CN 200810223468 A CN200810223468 A CN 200810223468A CN 101685601 B CN101685601 B CN 101685601B
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Abstract
The invention provides a level generating circuit for a plasma display, which comprises a level outputting module and a level providing module, wherein the level outputting module comprises a high level inputting end, a reference level end and a scanning chip, and is used for outputting a level through either the high level inputting end or the reference level end under the control of the scanning chip; the level providing module comprises a first switch for controlling to provide a low level and a second switch for controlling to provide a high level; and the first switch and the second switch are electrically connected to the high level inputting end and the reference level end of the level outputting module respectively. The level generating circuit also comprises a level generating module and a third switch, wherein the level generating module comprises a transformer, and one of two output ends of the transformer is used for providing a level for the high level inputting end according to a power supply level; and the third switch is electrically connected between the second switch and the other output end of the transformer.
Description
Technical field
The present invention relates to a kind of level generating circuit, more specifically, relate to a kind of level generating circuit that is used for plasma display.
Background technology
Chromatic alternating-current plasma (AC-PDP) is to develop according to the ultimate principle of gas discharge, realizes showing by the ultraviolet excitation light-emitting phosphor that gas discharge sends.At present, three-electrode surface discharge type AC-PDP is the most competitive a kind of PDP type, adopt addressing and display separation (ADS) technology to realize what gray scale showed mostly for this AC-PDP, be about to a TV Field and be divided into successively luminous 8 or 10 or 12 son fields, each son field is formed by preparatory stage, address period and the phase of keeping, and just can realize 256 grades gray scale demonstration by the combination of suitable son.
Three electrode quadrature shapes of three-electrode surface discharge type AC-PDP are distributed on the front-back baseboard, and discharge is then carried out between two substrates.The prebasal plate horizontal distribution and is kept electrode (X electrode) and scan electrode (Y electrode), and addressing electrode (A electrode) is vertically distributing on metacoxal plate.X electrode and Y electrode are parallel to each other, and with A electrode quadrature.
Fig. 1 is the drive waveforms of son in the ADS Driving technique, as shown in the figure, is divided into preparatory stage, address period and keeps the phase.In the preparatory stage, three electrodes cooperatively interact, and wipe the wall electric charge that a son field is left over, and make full frame all display units reach consistent original state; In address period, driving circuit carries out addressing to each row according to elder generation's strange back idol, top-down order, and writes image coded data at the A electrode, and the unit that all will be shown in this child field has accumulated suitable wall electric charge; In the phase of keeping, X electrode and Y electrode alternately add high pressure, make the unit generation discharge that has accumulated the wall electric charge in address period, thereby realize the demonstration of image.
Preparatory stage is when beginning, institute's making alive all is 0V on three electrodes, but, last when finishing of last or the last son field phase of keeping be added on the X electrode because keeping pulse, keep discharge back negative wall electric charge of accumulation on the X electrode, on the Y electrode, accumulated positive wall electric charge, therefore, on the Y electrode, add wide positive ramp voltage Vsetup earlier much larger than firing voltage, make between X and Y electrode and discharge, discharge and accumulated positive wall electric charge and negative wall electric charge on latter two electrode respectively, on the Y electrode, add a wide negative ramp voltage VY subsequently, on the X electrode, add a positive plateau voltage Vb, make between X and the Y electrode and slowly reach firing voltage, discharge, neutralize wall electric charge positive on X and the Y electrode and negative wall electric charge, make the state of full frame all unit reach the consistent state that extinguishes at last, address period subsequently just can be addressed to each unit accurately.Traditional Y driving circuit as shown in Figure 2, decline ramp voltage-Vy of sweep time voltage Vsc and preparatory stage produces by Switching Power Supply respectively, wherein,-VY is connected to YG by power switch pipe Qrampdn, Vsc is connected to scanning chip YP end (high voltage input terminal) by power switch pipe QscanH, and then is connected to scanning chip YG end (reference voltage end) by power switch pipe QsanL.Though prior art has well solved the problem that driving voltage is provided for scan electrode, itself circuit structure complexity, and used a large amount of power tubes as switch, increased the manufacturing cost of circuit, so still have very big room for improvement.
Summary of the invention
The purpose of this invention is to provide a kind of new level generating circuit that is used for plasma display, with minimizing power tube element number, thereby save circuit cost, and reduce the complexity of circuit.
For achieving the above object, the invention provides a kind of level generating circuit that is used for plasma display, comprise the level output module, comprise high level input end, datum end and scanning chip, one that is used under the control of scanning chip via high level input end and datum end is come output level; Level provides module, comprise being used to control and low level first switch is provided and is used to control the second switch that high level is provided, first switch and second switch are electrically connected to the high level input end and the datum end of level output module respectively, described level generating circuit also comprises: the level generation module, comprise transformer, one in two output terminals of transformer is used for providing level according to power level to the high level input end; And the 3rd switch, be connected electrically between in two output terminals of second switch and transformer another.
In addition, described level generating circuit also comprises energy recovery circuit, and it comprises: electric capacity and inductance are connected to ground; First branch road comprises the 4th switch, is connected to the high level input end; And second branch road, comprise the 5th switch, be connected to the datum end.
Wherein, described first switch, second switch, the 3rd switch, the 4th switch and the 5th switch are controlled by controller respectively.
The invention has the beneficial effects as follows provides a kind of level generating circuit that is used for plasma display.As can be seen, the present invention designs the circuit of more simplifying under the constant prerequisite of principle, thereby has reduced the number of power tube element, because the power tube price is considerable, so the present invention can reduce the manufacturing cost of this circuit significantly.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is X, the Y of a son field in the prior art and the driven waveform of three electrodes of A.
Fig. 2 is the level generating circuit figure that is used for plasma display of prior art.
Fig. 3 is the level generating circuit figure that is used for plasma display according to an exemplary embodiment of the present invention.
Embodiment
Below with reference to accompanying drawings, explain embodiments of the invention.
The driving circuit of simplifying mainly is to drive acclivity voltage and decline ramp voltage generation circuit and plateau voltage Vsc generation sweep time circuit part at Y, and other parts are constant, simplify circuit as shown in Figure 3.At first by the sweep time voltage Vscan_Vy of switching power circuit generation with respect to reference voltage Vy, Vscan_Vy links to each other with the YP end, and Vy is connected to YG by switch Qrampupdn, link to each other by electric capacity between Vscan_Vy and the Vy, promptly and the transformation Vsc as a result that is always transformer of the voltage difference between the Vy.When the preparatory stage arrives, power switch pipe QsusHY opens, the YG terminal voltage equals Vs, switching tube Qrampupdn opens simultaneously, Vy will equal the YG terminal voltage, i.e. Vs is because the Vscan_Vy that Switching Power Supply produces is with respect to Vy, then YP voltage=Vscan_Vy=Vsc+Vs realizes preparatory stage acclivity voltage waveform.QsusLY opens when switching tube, and YP voltage is forgotten about it 0 current potential, and then Vy=-Vsc when switch Qrampupdn opens, just can realize the ramp voltage waveform that descends.Owing to need not produce Vy voltage separately, therefore simplify circuit structure.
In addition, adopt different paths respectively with the screen capacitor discharge in energy recovery circuit input, as shown in Figure 3, i.e. the form of two branch roads, thus the Pass switching tube removed, therefore greatly reduce the complexity of circuit, provide cost savings.
Particularly, referring to Fig. 1, Fig. 1 is the drive waveforms of a certain son field on driving circuit X, Y, A three electrodes.10. 9. 8. 7. 6. 5. 4. 3. 2. 1. label be each stage of an a son interior drive waveforms.Wherein 5. 4. 3. 2. 1. be the preparatory stage, 6. 7. 8. the stage be address period, the several stages of back is the phase of keeping.
Referring to Fig. 3, when one or one at first, promptly the stage among Fig. 1 is 1., voltage on the Y is 0, and at this moment, the level output module switches to the YG end by SCAN IC, power switch pipe QsusLY opens, and YG is connected to GND by Qscan, realizes that the Y output voltage is 0V; Stage 2. in, other switch closures, switch Qrampupdn opens, Vy voltage is pulled to 0 current potential like this; Stage 3. in, power switch pipe QsusHY opens, the YG terminal voltage equals Vs, and switching tube Qrampupdn opens simultaneously, and Vy will equal the YG terminal voltage, be Vs, because the VSC_Vy that Switching Power Supply produces is with respect to Vy, then YP voltage=Vscan_Vy=Vsc+Vs realizes preparatory stage acclivity voltage waveform, slowly the purpose that rises is not take place to neutralize most wall electric charge on the strong basis of discharging, and very strong bias light can not take place; Stage 4. in, power switch pipe QsusLY opens, other switches cut out, Y output is connected to GND, making output voltage is 0V; Stage 5. in, switching tube QsusLY opens, YP voltage is pulled to 0 current potential, Vy=-Vsc then, when switch Qrampupdn opened, YG equaled-Vsc, had realized the decline ramp voltage waveform, the purpose that the slope descends also is in order to neutralize most wall electric charge on the basis that strong discharge is not taking place, and very strong bias light can not take place; The 6. the stage be the scanning address phase, as shown in Figure 3, during this period, permanent between voltage and the YG on the unit that is not addressed to for Vsc, at this moment, switch QsusLY and switch Qrampupdn need be opened, when switch QsusLY opens, the YP terminal potential is 0, and the Vy end is-Vsc, when Qrampupdn also opens, the YG end is-Vsc, therefore realize the scanning plateau voltage, this voltage potential is 0V, shown in the address period of Fig. 1; 7. stage is the addressing negative pulse, and the capable Y driving circuit at the place, unit that is addressed to can be exported to negative pulse of this row, and this negative pulse is to pulled down to-Vsc from address period voltage; In the 8. stage, switch QsusLY opens, and other switches cut out, and Y output is connected to GND, and making output voltage is 0V, keeps the address period plateau voltage; Next carry out the transition to the phase of keeping, 9. keeping pulse height is Vs in order to keep rising edge of a pulse the stage, at this moment, the energy recovery circuit part can be worked, at first switching tube QerH opens, and capacitor C er is gone up charge stored be transferred on the Y electrode, gives the screen charging, it is about 80% of Vs that this part electric charge makes the voltage on the Y electrode, next switching tube QsusHY opens, and other switches cut out, and moves the amplitude of keeping rising edge of a pulse to Vs; Ensuing 10. the stage is a negative edge of keeping pulse, keep voltage and need move 0 current potential to, do not waste in order to make energy, electric charge is stored in the storage capacitor by switching tube QerL, move output voltage amplitude to 0 current potential by switching tube QsusLY more subsequently, next repeat rising, step-down operation, finish whole keeping the phase, enter the driving process of next son field subsequently, repeat 10 processes that similar front was said, the Y that finishes all son fields drives, and cooperates X to drive simultaneously and the A driving, finishes the demonstration of a field picture.
The present invention is by adopting a kind of new circuit structure in a word, drive in preparatory stage acclivity voltage and the decline ramp voltage generation circuit at Y, traditional circuit VSC and Vy voltage have been replaced with the voltage VSC_Vy that floats on Vy, reduced circuit complexity, simultaneously also reduce circuit power consumption, improved work efficiency.And,, also reduced the cost of circuit owing to reduced the power tube number.
The above is embodiments of the invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Every power consumption information feedback with display is to the technical scheme of main frame, any modification of being done, is equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (6)
1. level generating circuit that is used for plasma display comprises:
The level output module comprises high level input end, datum end and scanning chip, and one that is used under the control of described scanning chip via described high level input end and described datum end is come output level;
Level provides module, comprise being used to control and low level first switch is provided and is used to control the second switch that high level is provided, described first switch is electrically connected to the described high level input end of described level output module, described second switch is electrically connected to the described datum end of described level output module
It is characterized in that, also comprise:
The level generation module comprises transformer, and one in two output terminals of described transformer is used for providing level according to power level to described high level input end, wherein, is connected with first electric capacity between two output terminals of described transformer; And
The 3rd switch is connected electrically between in two output terminals of described second switch and described transformer another.
2. the level generating circuit that is used for plasma display according to claim 1 is characterized in that, also comprises energy recovery circuit, and described energy recovery circuit comprises:
Second electric capacity and inductance are connected to ground;
First branch road comprises the 4th switch, is connected to described high level input end;
And
Second branch road comprises the 5th switch, is connected to described datum end.
3. the level generating circuit that is used for plasma display according to claim 2 is characterized in that, described first switch, second switch, the 3rd switch, the 4th switch and the 5th switch are controlled by controller respectively.
4. the level generating circuit that is used for plasma display according to claim 1 and 2 is characterized in that, described scanning chip comprises a plurality of switches, is used for selecting one the level and the output of described high level input end and described datum end.
5. the level generating circuit that is used for plasma display according to claim 4, it is characterized in that, described scanning chip comprises two switches, one of them is serially connected between the output terminal of described high level input end and described level output module, and in described two switches another is serially connected between the described output terminal of described datum end and described level output module.
6. the level generating circuit that is used for plasma display according to claim 2 is characterized in that, described first switch, second switch, the 3rd switch, the 4th switch and the 5th switch are power switch pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810223468 CN101685601B (en) | 2008-09-28 | 2008-09-28 | Level generating circuit for plasma display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810223468 CN101685601B (en) | 2008-09-28 | 2008-09-28 | Level generating circuit for plasma display |
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| CN101685601A CN101685601A (en) | 2010-03-31 |
| CN101685601B true CN101685601B (en) | 2011-06-08 |
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| CN 200810223468 Expired - Fee Related CN101685601B (en) | 2008-09-28 | 2008-09-28 | Level generating circuit for plasma display |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101950531B (en) * | 2010-09-30 | 2012-09-05 | 四川虹欧显示器件有限公司 | Scanning-sustaining electrode drive circuit, plasma display and drive circuit thereof |
Citations (6)
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|---|---|---|---|---|
| CN1421838A (en) * | 2001-11-29 | 2003-06-04 | Lg电子株式会社 | Continuous pulse generator of plasma display panel |
| EP1341144A1 (en) * | 2002-03-01 | 2003-09-03 | Magnetek S.p.A. | Power circuit for a plasma display |
| CN1615504A (en) * | 2002-01-11 | 2005-05-11 | 曹普衡 | Driving circuit for energy recovery in plasma display panel |
| CN1639760A (en) * | 2002-02-25 | 2005-07-13 | 汤姆森许可贸易公司 | Supply and drive means for a plasma panel using transformers |
| CN1848640A (en) * | 2005-04-14 | 2006-10-18 | 三星Sdi株式会社 | Plasma display device, power device thereof, and driving method thereof |
| KR20070028842A (en) * | 2005-09-08 | 2007-03-13 | 엘지전자 주식회사 | Sustain electrode driver of plasma display panel where dc/dc converter is integrated and method for driving sustain electrode |
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- 2008-09-28 CN CN 200810223468 patent/CN101685601B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1421838A (en) * | 2001-11-29 | 2003-06-04 | Lg电子株式会社 | Continuous pulse generator of plasma display panel |
| CN1615504A (en) * | 2002-01-11 | 2005-05-11 | 曹普衡 | Driving circuit for energy recovery in plasma display panel |
| CN1639760A (en) * | 2002-02-25 | 2005-07-13 | 汤姆森许可贸易公司 | Supply and drive means for a plasma panel using transformers |
| EP1341144A1 (en) * | 2002-03-01 | 2003-09-03 | Magnetek S.p.A. | Power circuit for a plasma display |
| CN1848640A (en) * | 2005-04-14 | 2006-10-18 | 三星Sdi株式会社 | Plasma display device, power device thereof, and driving method thereof |
| KR20070028842A (en) * | 2005-09-08 | 2007-03-13 | 엘지전자 주식회사 | Sustain electrode driver of plasma display panel where dc/dc converter is integrated and method for driving sustain electrode |
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Granted publication date: 20110608 Termination date: 20160928 |